1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Support for NXT2002 and NXT2004 - VSB/QAM
4 *
5 * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com>
6 * Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org>
7 * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net>
8 * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com>
9 */
10
11 /*
12 * NOTES ABOUT THIS DRIVER
13 *
14 * This Linux driver supports:
15 * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002)
16 * AverTVHD MCE A180 (NXT2004)
17 * ATI HDTV Wonder (NXT2004)
18 *
19 * This driver needs external firmware. Please use the command
20 * "<kerneldir>/scripts/get_dvb_firmware nxt2002" or
21 * "<kerneldir>/scripts/get_dvb_firmware nxt2004" to
22 * download/extract the appropriate firmware, and then copy it to
23 * /usr/lib/hotplug/firmware/ or /lib/firmware/
24 * (depending on configuration of firmware hotplug).
25 */
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28 /* Max transfer size done by I2C transfer functions */
29 #define MAX_XFER_SIZE 256
30
31 #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
32 #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw"
33 #define CRC_CCIT_MASK 0x1021
34
35 #include <linux/kernel.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/slab.h>
39 #include <linux/string.h>
40
41 #include <media/dvb_frontend.h>
42 #include "nxt200x.h"
43
44 struct nxt200x_state {
45
46 struct i2c_adapter* i2c;
47 const struct nxt200x_config* config;
48 struct dvb_frontend frontend;
49
50 /* demodulator private data */
51 nxt_chip_type demod_chip;
52 u8 initialised:1;
53 };
54
55 static int debug;
56 #define dprintk(args...) do { if (debug) pr_debug(args); } while (0)
57
i2c_writebytes(struct nxt200x_state * state,u8 addr,u8 * buf,u8 len)58 static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len)
59 {
60 int err;
61 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len };
62
63 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
64 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
65 __func__, addr, err);
66 return -EREMOTEIO;
67 }
68 return 0;
69 }
70
i2c_readbytes(struct nxt200x_state * state,u8 addr,u8 * buf,u8 len)71 static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len)
72 {
73 int err;
74 struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len };
75
76 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
77 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
78 __func__, addr, err);
79 return -EREMOTEIO;
80 }
81 return 0;
82 }
83
nxt200x_writebytes(struct nxt200x_state * state,u8 reg,const u8 * buf,u8 len)84 static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg,
85 const u8 *buf, u8 len)
86 {
87 u8 buf2[MAX_XFER_SIZE];
88 int err;
89 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
90
91 if (1 + len > sizeof(buf2)) {
92 pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
93 __func__, reg, len);
94 return -EINVAL;
95 }
96
97 buf2[0] = reg;
98 memcpy(&buf2[1], buf, len);
99
100 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
101 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
102 __func__, state->config->demod_address, err);
103 return -EREMOTEIO;
104 }
105 return 0;
106 }
107
nxt200x_readbytes(struct nxt200x_state * state,u8 reg,u8 * buf,u8 len)108 static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len)
109 {
110 u8 reg2 [] = { reg };
111
112 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
113 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
114
115 int err;
116
117 if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
118 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
119 __func__, state->config->demod_address, err);
120 return -EREMOTEIO;
121 }
122 return 0;
123 }
124
nxt200x_crc(u16 crc,u8 c)125 static u16 nxt200x_crc(u16 crc, u8 c)
126 {
127 u8 i;
128 u16 input = (u16) c & 0xFF;
129
130 input<<=8;
131 for(i=0; i<8; i++) {
132 if((crc^input) & 0x8000)
133 crc=(crc<<1)^CRC_CCIT_MASK;
134 else
135 crc<<=1;
136 input<<=1;
137 }
138 return crc;
139 }
140
nxt200x_writereg_multibyte(struct nxt200x_state * state,u8 reg,u8 * data,u8 len)141 static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
142 {
143 u8 attr, len2, buf;
144 dprintk("%s\n", __func__);
145
146 /* set multi register register */
147 nxt200x_writebytes(state, 0x35, ®, 1);
148
149 /* send the actual data */
150 nxt200x_writebytes(state, 0x36, data, len);
151
152 switch (state->demod_chip) {
153 case NXT2002:
154 len2 = len;
155 buf = 0x02;
156 break;
157 case NXT2004:
158 /* probably not right, but gives correct values */
159 attr = 0x02;
160 if (reg & 0x80) {
161 attr = attr << 1;
162 if (reg & 0x04)
163 attr = attr >> 1;
164 }
165 /* set write bit */
166 len2 = ((attr << 4) | 0x10) | len;
167 buf = 0x80;
168 break;
169 default:
170 return -EINVAL;
171 break;
172 }
173
174 /* set multi register length */
175 nxt200x_writebytes(state, 0x34, &len2, 1);
176
177 /* toggle the multireg write bit */
178 nxt200x_writebytes(state, 0x21, &buf, 1);
179
180 nxt200x_readbytes(state, 0x21, &buf, 1);
181
182 switch (state->demod_chip) {
183 case NXT2002:
184 if ((buf & 0x02) == 0)
185 return 0;
186 break;
187 case NXT2004:
188 if (buf == 0)
189 return 0;
190 break;
191 default:
192 return -EINVAL;
193 break;
194 }
195
196 pr_warn("Error writing multireg register 0x%02X\n", reg);
197
198 return 0;
199 }
200
nxt200x_readreg_multibyte(struct nxt200x_state * state,u8 reg,u8 * data,u8 len)201 static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
202 {
203 int i;
204 u8 buf, len2, attr;
205 dprintk("%s\n", __func__);
206
207 /* set multi register register */
208 nxt200x_writebytes(state, 0x35, ®, 1);
209
210 switch (state->demod_chip) {
211 case NXT2002:
212 /* set multi register length */
213 len2 = len & 0x80;
214 nxt200x_writebytes(state, 0x34, &len2, 1);
215
216 /* read the actual data */
217 nxt200x_readbytes(state, reg, data, len);
218 return 0;
219 break;
220 case NXT2004:
221 /* probably not right, but gives correct values */
222 attr = 0x02;
223 if (reg & 0x80) {
224 attr = attr << 1;
225 if (reg & 0x04)
226 attr = attr >> 1;
227 }
228
229 /* set multi register length */
230 len2 = (attr << 4) | len;
231 nxt200x_writebytes(state, 0x34, &len2, 1);
232
233 /* toggle the multireg bit*/
234 buf = 0x80;
235 nxt200x_writebytes(state, 0x21, &buf, 1);
236
237 /* read the actual data */
238 for(i = 0; i < len; i++) {
239 nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
240 }
241 return 0;
242 break;
243 default:
244 return -EINVAL;
245 break;
246 }
247 }
248
nxt200x_microcontroller_stop(struct nxt200x_state * state)249 static void nxt200x_microcontroller_stop (struct nxt200x_state* state)
250 {
251 u8 buf, stopval, counter = 0;
252 dprintk("%s\n", __func__);
253
254 /* set correct stop value */
255 switch (state->demod_chip) {
256 case NXT2002:
257 stopval = 0x40;
258 break;
259 case NXT2004:
260 stopval = 0x10;
261 break;
262 default:
263 stopval = 0;
264 break;
265 }
266
267 buf = 0x80;
268 nxt200x_writebytes(state, 0x22, &buf, 1);
269
270 while (counter < 20) {
271 nxt200x_readbytes(state, 0x31, &buf, 1);
272 if (buf & stopval)
273 return;
274 msleep(10);
275 counter++;
276 }
277
278 pr_warn("Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n");
279 return;
280 }
281
nxt200x_microcontroller_start(struct nxt200x_state * state)282 static void nxt200x_microcontroller_start (struct nxt200x_state* state)
283 {
284 u8 buf;
285 dprintk("%s\n", __func__);
286
287 buf = 0x00;
288 nxt200x_writebytes(state, 0x22, &buf, 1);
289 }
290
nxt2004_microcontroller_init(struct nxt200x_state * state)291 static void nxt2004_microcontroller_init (struct nxt200x_state* state)
292 {
293 u8 buf[9];
294 u8 counter = 0;
295 dprintk("%s\n", __func__);
296
297 buf[0] = 0x00;
298 nxt200x_writebytes(state, 0x2b, buf, 1);
299 buf[0] = 0x70;
300 nxt200x_writebytes(state, 0x34, buf, 1);
301 buf[0] = 0x04;
302 nxt200x_writebytes(state, 0x35, buf, 1);
303 buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89;
304 buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0;
305 nxt200x_writebytes(state, 0x36, buf, 9);
306 buf[0] = 0x80;
307 nxt200x_writebytes(state, 0x21, buf, 1);
308
309 while (counter < 20) {
310 nxt200x_readbytes(state, 0x21, buf, 1);
311 if (buf[0] == 0)
312 return;
313 msleep(10);
314 counter++;
315 }
316
317 pr_warn("Timeout waiting for nxt2004 to init.\n");
318
319 return;
320 }
321
nxt200x_writetuner(struct nxt200x_state * state,u8 * data)322 static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)
323 {
324 u8 buf, count = 0;
325
326 dprintk("%s\n", __func__);
327
328 dprintk("Tuner Bytes: %*ph\n", 4, data + 1);
329
330 /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip.
331 * direct write is required for Philips TUV1236D and ALPS TDHU2 */
332 switch (state->demod_chip) {
333 case NXT2004:
334 if (i2c_writebytes(state, data[0], data+1, 4))
335 pr_warn("error writing to tuner\n");
336 /* wait until we have a lock */
337 while (count < 20) {
338 i2c_readbytes(state, data[0], &buf, 1);
339 if (buf & 0x40)
340 return 0;
341 msleep(100);
342 count++;
343 }
344 pr_warn("timeout waiting for tuner lock\n");
345 break;
346 case NXT2002:
347 /* set the i2c transfer speed to the tuner */
348 buf = 0x03;
349 nxt200x_writebytes(state, 0x20, &buf, 1);
350
351 /* setup to transfer 4 bytes via i2c */
352 buf = 0x04;
353 nxt200x_writebytes(state, 0x34, &buf, 1);
354
355 /* write actual tuner bytes */
356 nxt200x_writebytes(state, 0x36, data+1, 4);
357
358 /* set tuner i2c address */
359 buf = data[0] << 1;
360 nxt200x_writebytes(state, 0x35, &buf, 1);
361
362 /* write UC Opmode to begin transfer */
363 buf = 0x80;
364 nxt200x_writebytes(state, 0x21, &buf, 1);
365
366 while (count < 20) {
367 nxt200x_readbytes(state, 0x21, &buf, 1);
368 if ((buf & 0x80)== 0x00)
369 return 0;
370 msleep(100);
371 count++;
372 }
373 pr_warn("timeout error writing to tuner\n");
374 break;
375 default:
376 return -EINVAL;
377 break;
378 }
379 return 0;
380 }
381
nxt200x_agc_reset(struct nxt200x_state * state)382 static void nxt200x_agc_reset(struct nxt200x_state* state)
383 {
384 u8 buf;
385 dprintk("%s\n", __func__);
386
387 switch (state->demod_chip) {
388 case NXT2002:
389 buf = 0x08;
390 nxt200x_writebytes(state, 0x08, &buf, 1);
391 buf = 0x00;
392 nxt200x_writebytes(state, 0x08, &buf, 1);
393 break;
394 case NXT2004:
395 nxt200x_readreg_multibyte(state, 0x08, &buf, 1);
396 buf = 0x08;
397 nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
398 buf = 0x00;
399 nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
400 break;
401 default:
402 break;
403 }
404 return;
405 }
406
nxt2002_load_firmware(struct dvb_frontend * fe,const struct firmware * fw)407 static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
408 {
409
410 struct nxt200x_state* state = fe->demodulator_priv;
411 u8 buf[3], written = 0, chunkpos = 0;
412 u16 rambase, position, crc = 0;
413
414 dprintk("%s\n", __func__);
415 dprintk("Firmware is %zu bytes\n", fw->size);
416
417 /* Get the RAM base for this nxt2002 */
418 nxt200x_readbytes(state, 0x10, buf, 1);
419
420 if (buf[0] & 0x10)
421 rambase = 0x1000;
422 else
423 rambase = 0x0000;
424
425 dprintk("rambase on this nxt2002 is %04X\n", rambase);
426
427 /* Hold the micro in reset while loading firmware */
428 buf[0] = 0x80;
429 nxt200x_writebytes(state, 0x2B, buf, 1);
430
431 for (position = 0; position < fw->size; position++) {
432 if (written == 0) {
433 crc = 0;
434 chunkpos = 0x28;
435 buf[0] = ((rambase + position) >> 8);
436 buf[1] = (rambase + position) & 0xFF;
437 buf[2] = 0x81;
438 /* write starting address */
439 nxt200x_writebytes(state, 0x29, buf, 3);
440 }
441 written++;
442 chunkpos++;
443
444 if ((written % 4) == 0)
445 nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4);
446
447 crc = nxt200x_crc(crc, fw->data[position]);
448
449 if ((written == 255) || (position+1 == fw->size)) {
450 /* write remaining bytes of firmware */
451 nxt200x_writebytes(state, chunkpos+4-(written %4),
452 &fw->data[position-(written %4) + 1],
453 written %4);
454 buf[0] = crc << 8;
455 buf[1] = crc & 0xFF;
456
457 /* write crc */
458 nxt200x_writebytes(state, 0x2C, buf, 2);
459
460 /* do a read to stop things */
461 nxt200x_readbytes(state, 0x2A, buf, 1);
462
463 /* set transfer mode to complete */
464 buf[0] = 0x80;
465 nxt200x_writebytes(state, 0x2B, buf, 1);
466
467 written = 0;
468 }
469 }
470
471 return 0;
472 };
473
nxt2004_load_firmware(struct dvb_frontend * fe,const struct firmware * fw)474 static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
475 {
476
477 struct nxt200x_state* state = fe->demodulator_priv;
478 u8 buf[3];
479 u16 rambase, position, crc=0;
480
481 dprintk("%s\n", __func__);
482 dprintk("Firmware is %zu bytes\n", fw->size);
483
484 /* set rambase */
485 rambase = 0x1000;
486
487 /* hold the micro in reset while loading firmware */
488 buf[0] = 0x80;
489 nxt200x_writebytes(state, 0x2B, buf,1);
490
491 /* calculate firmware CRC */
492 for (position = 0; position < fw->size; position++) {
493 crc = nxt200x_crc(crc, fw->data[position]);
494 }
495
496 buf[0] = rambase >> 8;
497 buf[1] = rambase & 0xFF;
498 buf[2] = 0x81;
499 /* write starting address */
500 nxt200x_writebytes(state,0x29,buf,3);
501
502 for (position = 0; position < fw->size;) {
503 nxt200x_writebytes(state, 0x2C, &fw->data[position],
504 fw->size-position > 255 ? 255 : fw->size-position);
505 position += (fw->size-position > 255 ? 255 : fw->size-position);
506 }
507 buf[0] = crc >> 8;
508 buf[1] = crc & 0xFF;
509
510 dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]);
511
512 /* write crc */
513 nxt200x_writebytes(state, 0x2C, buf,2);
514
515 /* do a read to stop things */
516 nxt200x_readbytes(state, 0x2C, buf, 1);
517
518 /* set transfer mode to complete */
519 buf[0] = 0x80;
520 nxt200x_writebytes(state, 0x2B, buf,1);
521
522 return 0;
523 };
524
nxt200x_setup_frontend_parameters(struct dvb_frontend * fe)525 static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
526 {
527 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
528 struct nxt200x_state* state = fe->demodulator_priv;
529 u8 buf[5];
530
531 /* stop the micro first */
532 nxt200x_microcontroller_stop(state);
533
534 if (state->demod_chip == NXT2004) {
535 /* make sure demod is set to digital */
536 buf[0] = 0x04;
537 nxt200x_writebytes(state, 0x14, buf, 1);
538 buf[0] = 0x00;
539 nxt200x_writebytes(state, 0x17, buf, 1);
540 }
541
542 /* set additional params */
543 switch (p->modulation) {
544 case QAM_64:
545 case QAM_256:
546 /* Set punctured clock for QAM */
547 /* This is just a guess since I am unable to test it */
548 if (state->config->set_ts_params)
549 state->config->set_ts_params(fe, 1);
550 break;
551 case VSB_8:
552 /* Set non-punctured clock for VSB */
553 if (state->config->set_ts_params)
554 state->config->set_ts_params(fe, 0);
555 break;
556 default:
557 return -EINVAL;
558 break;
559 }
560
561 if (fe->ops.tuner_ops.calc_regs) {
562 /* get tuning information */
563 fe->ops.tuner_ops.calc_regs(fe, buf, 5);
564
565 /* write frequency information */
566 nxt200x_writetuner(state, buf);
567 }
568
569 /* reset the agc now that tuning has been completed */
570 nxt200x_agc_reset(state);
571
572 /* set target power level */
573 switch (p->modulation) {
574 case QAM_64:
575 case QAM_256:
576 buf[0] = 0x74;
577 break;
578 case VSB_8:
579 buf[0] = 0x70;
580 break;
581 default:
582 return -EINVAL;
583 break;
584 }
585 nxt200x_writebytes(state, 0x42, buf, 1);
586
587 /* configure sdm */
588 switch (state->demod_chip) {
589 case NXT2002:
590 buf[0] = 0x87;
591 break;
592 case NXT2004:
593 buf[0] = 0x07;
594 break;
595 default:
596 return -EINVAL;
597 break;
598 }
599 nxt200x_writebytes(state, 0x57, buf, 1);
600
601 /* write sdm1 input */
602 buf[0] = 0x10;
603 buf[1] = 0x00;
604 switch (state->demod_chip) {
605 case NXT2002:
606 nxt200x_writereg_multibyte(state, 0x58, buf, 2);
607 break;
608 case NXT2004:
609 nxt200x_writebytes(state, 0x58, buf, 2);
610 break;
611 default:
612 return -EINVAL;
613 break;
614 }
615
616 /* write sdmx input */
617 switch (p->modulation) {
618 case QAM_64:
619 buf[0] = 0x68;
620 break;
621 case QAM_256:
622 buf[0] = 0x64;
623 break;
624 case VSB_8:
625 buf[0] = 0x60;
626 break;
627 default:
628 return -EINVAL;
629 break;
630 }
631 buf[1] = 0x00;
632 switch (state->demod_chip) {
633 case NXT2002:
634 nxt200x_writereg_multibyte(state, 0x5C, buf, 2);
635 break;
636 case NXT2004:
637 nxt200x_writebytes(state, 0x5C, buf, 2);
638 break;
639 default:
640 return -EINVAL;
641 break;
642 }
643
644 /* write adc power lpf fc */
645 buf[0] = 0x05;
646 nxt200x_writebytes(state, 0x43, buf, 1);
647
648 if (state->demod_chip == NXT2004) {
649 /* write ??? */
650 buf[0] = 0x00;
651 buf[1] = 0x00;
652 nxt200x_writebytes(state, 0x46, buf, 2);
653 }
654
655 /* write accumulator2 input */
656 buf[0] = 0x80;
657 buf[1] = 0x00;
658 switch (state->demod_chip) {
659 case NXT2002:
660 nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
661 break;
662 case NXT2004:
663 nxt200x_writebytes(state, 0x4B, buf, 2);
664 break;
665 default:
666 return -EINVAL;
667 break;
668 }
669
670 /* write kg1 */
671 buf[0] = 0x00;
672 nxt200x_writebytes(state, 0x4D, buf, 1);
673
674 /* write sdm12 lpf fc */
675 buf[0] = 0x44;
676 nxt200x_writebytes(state, 0x55, buf, 1);
677
678 /* write agc control reg */
679 buf[0] = 0x04;
680 nxt200x_writebytes(state, 0x41, buf, 1);
681
682 if (state->demod_chip == NXT2004) {
683 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
684 buf[0] = 0x24;
685 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
686
687 /* soft reset? */
688 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
689 buf[0] = 0x10;
690 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
691 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
692 buf[0] = 0x00;
693 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
694
695 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
696 buf[0] = 0x04;
697 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
698 buf[0] = 0x00;
699 nxt200x_writereg_multibyte(state, 0x81, buf, 1);
700 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
701 nxt200x_writereg_multibyte(state, 0x82, buf, 3);
702 nxt200x_readreg_multibyte(state, 0x88, buf, 1);
703 buf[0] = 0x11;
704 nxt200x_writereg_multibyte(state, 0x88, buf, 1);
705 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
706 buf[0] = 0x44;
707 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
708 }
709
710 /* write agc ucgp0 */
711 switch (p->modulation) {
712 case QAM_64:
713 buf[0] = 0x02;
714 break;
715 case QAM_256:
716 buf[0] = 0x03;
717 break;
718 case VSB_8:
719 buf[0] = 0x00;
720 break;
721 default:
722 return -EINVAL;
723 break;
724 }
725 nxt200x_writebytes(state, 0x30, buf, 1);
726
727 /* write agc control reg */
728 buf[0] = 0x00;
729 nxt200x_writebytes(state, 0x41, buf, 1);
730
731 /* write accumulator2 input */
732 buf[0] = 0x80;
733 buf[1] = 0x00;
734 switch (state->demod_chip) {
735 case NXT2002:
736 nxt200x_writereg_multibyte(state, 0x49, buf, 2);
737 nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
738 break;
739 case NXT2004:
740 nxt200x_writebytes(state, 0x49, buf, 2);
741 nxt200x_writebytes(state, 0x4B, buf, 2);
742 break;
743 default:
744 return -EINVAL;
745 break;
746 }
747
748 /* write agc control reg */
749 buf[0] = 0x04;
750 nxt200x_writebytes(state, 0x41, buf, 1);
751
752 nxt200x_microcontroller_start(state);
753
754 if (state->demod_chip == NXT2004) {
755 nxt2004_microcontroller_init(state);
756
757 /* ???? */
758 buf[0] = 0xF0;
759 buf[1] = 0x00;
760 nxt200x_writebytes(state, 0x5C, buf, 2);
761 }
762
763 /* adjacent channel detection should be done here, but I don't
764 have any stations with this need so I cannot test it */
765
766 return 0;
767 }
768
nxt200x_read_status(struct dvb_frontend * fe,enum fe_status * status)769 static int nxt200x_read_status(struct dvb_frontend *fe, enum fe_status *status)
770 {
771 struct nxt200x_state* state = fe->demodulator_priv;
772 u8 lock;
773 nxt200x_readbytes(state, 0x31, &lock, 1);
774
775 *status = 0;
776 if (lock & 0x20) {
777 *status |= FE_HAS_SIGNAL;
778 *status |= FE_HAS_CARRIER;
779 *status |= FE_HAS_VITERBI;
780 *status |= FE_HAS_SYNC;
781 *status |= FE_HAS_LOCK;
782 }
783 return 0;
784 }
785
nxt200x_read_ber(struct dvb_frontend * fe,u32 * ber)786 static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber)
787 {
788 struct nxt200x_state* state = fe->demodulator_priv;
789 u8 b[3];
790
791 nxt200x_readreg_multibyte(state, 0xE6, b, 3);
792
793 *ber = ((b[0] << 8) + b[1]) * 8;
794
795 return 0;
796 }
797
nxt200x_read_signal_strength(struct dvb_frontend * fe,u16 * strength)798 static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
799 {
800 struct nxt200x_state* state = fe->demodulator_priv;
801 u8 b[2];
802 u16 temp = 0;
803
804 /* setup to read cluster variance */
805 b[0] = 0x00;
806 nxt200x_writebytes(state, 0xA1, b, 1);
807
808 /* get multreg val */
809 nxt200x_readreg_multibyte(state, 0xA6, b, 2);
810
811 temp = (b[0] << 8) | b[1];
812 *strength = ((0x7FFF - temp) & 0x0FFF) * 16;
813
814 return 0;
815 }
816
nxt200x_read_snr(struct dvb_frontend * fe,u16 * snr)817 static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr)
818 {
819
820 struct nxt200x_state* state = fe->demodulator_priv;
821 u8 b[2];
822 u16 temp = 0, temp2;
823 u32 snrdb = 0;
824
825 /* setup to read cluster variance */
826 b[0] = 0x00;
827 nxt200x_writebytes(state, 0xA1, b, 1);
828
829 /* get multreg val from 0xA6 */
830 nxt200x_readreg_multibyte(state, 0xA6, b, 2);
831
832 temp = (b[0] << 8) | b[1];
833 temp2 = 0x7FFF - temp;
834
835 /* snr will be in db */
836 if (temp2 > 0x7F00)
837 snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
838 else if (temp2 > 0x7EC0)
839 snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
840 else if (temp2 > 0x7C00)
841 snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
842 else
843 snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
844
845 /* the value reported back from the frontend will be FFFF=32db 0000=0db */
846 *snr = snrdb * (0xFFFF/32000);
847
848 return 0;
849 }
850
nxt200x_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)851 static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
852 {
853 struct nxt200x_state* state = fe->demodulator_priv;
854 u8 b[3];
855
856 nxt200x_readreg_multibyte(state, 0xE6, b, 3);
857 *ucblocks = b[2];
858
859 return 0;
860 }
861
nxt200x_sleep(struct dvb_frontend * fe)862 static int nxt200x_sleep(struct dvb_frontend* fe)
863 {
864 return 0;
865 }
866
nxt2002_init(struct dvb_frontend * fe)867 static int nxt2002_init(struct dvb_frontend* fe)
868 {
869 struct nxt200x_state* state = fe->demodulator_priv;
870 const struct firmware *fw;
871 int ret;
872 u8 buf[2];
873
874 /* request the firmware, this will block until someone uploads it */
875 pr_debug("%s: Waiting for firmware upload (%s)...\n",
876 __func__, NXT2002_DEFAULT_FIRMWARE);
877 ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE,
878 state->i2c->dev.parent);
879 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
880 if (ret) {
881 pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
882 __func__);
883 return ret;
884 }
885
886 ret = nxt2002_load_firmware(fe, fw);
887 release_firmware(fw);
888 if (ret) {
889 pr_err("%s: Writing firmware to device failed\n", __func__);
890 return ret;
891 }
892 pr_info("%s: Firmware upload complete\n", __func__);
893
894 /* Put the micro into reset */
895 nxt200x_microcontroller_stop(state);
896
897 /* ensure transfer is complete */
898 buf[0]=0x00;
899 nxt200x_writebytes(state, 0x2B, buf, 1);
900
901 /* Put the micro into reset for real this time */
902 nxt200x_microcontroller_stop(state);
903
904 /* soft reset everything (agc,frontend,eq,fec)*/
905 buf[0] = 0x0F;
906 nxt200x_writebytes(state, 0x08, buf, 1);
907 buf[0] = 0x00;
908 nxt200x_writebytes(state, 0x08, buf, 1);
909
910 /* write agc sdm configure */
911 buf[0] = 0xF1;
912 nxt200x_writebytes(state, 0x57, buf, 1);
913
914 /* write mod output format */
915 buf[0] = 0x20;
916 nxt200x_writebytes(state, 0x09, buf, 1);
917
918 /* write fec mpeg mode */
919 buf[0] = 0x7E;
920 buf[1] = 0x00;
921 nxt200x_writebytes(state, 0xE9, buf, 2);
922
923 /* write mux selection */
924 buf[0] = 0x00;
925 nxt200x_writebytes(state, 0xCC, buf, 1);
926
927 return 0;
928 }
929
nxt2004_init(struct dvb_frontend * fe)930 static int nxt2004_init(struct dvb_frontend* fe)
931 {
932 struct nxt200x_state* state = fe->demodulator_priv;
933 const struct firmware *fw;
934 int ret;
935 u8 buf[3];
936
937 /* ??? */
938 buf[0]=0x00;
939 nxt200x_writebytes(state, 0x1E, buf, 1);
940
941 /* request the firmware, this will block until someone uploads it */
942 pr_debug("%s: Waiting for firmware upload (%s)...\n",
943 __func__, NXT2004_DEFAULT_FIRMWARE);
944 ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE,
945 state->i2c->dev.parent);
946 pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
947 if (ret) {
948 pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
949 __func__);
950 return ret;
951 }
952
953 ret = nxt2004_load_firmware(fe, fw);
954 release_firmware(fw);
955 if (ret) {
956 pr_err("%s: Writing firmware to device failed\n", __func__);
957 return ret;
958 }
959 pr_info("%s: Firmware upload complete\n", __func__);
960
961 /* ensure transfer is complete */
962 buf[0] = 0x01;
963 nxt200x_writebytes(state, 0x19, buf, 1);
964
965 nxt2004_microcontroller_init(state);
966 nxt200x_microcontroller_stop(state);
967 nxt200x_microcontroller_stop(state);
968 nxt2004_microcontroller_init(state);
969 nxt200x_microcontroller_stop(state);
970
971 /* soft reset everything (agc,frontend,eq,fec)*/
972 buf[0] = 0xFF;
973 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
974 buf[0] = 0x00;
975 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
976
977 /* write agc sdm configure */
978 buf[0] = 0xD7;
979 nxt200x_writebytes(state, 0x57, buf, 1);
980
981 /* ???*/
982 buf[0] = 0x07;
983 buf[1] = 0xfe;
984 nxt200x_writebytes(state, 0x35, buf, 2);
985 buf[0] = 0x12;
986 nxt200x_writebytes(state, 0x34, buf, 1);
987 buf[0] = 0x80;
988 nxt200x_writebytes(state, 0x21, buf, 1);
989
990 /* ???*/
991 buf[0] = 0x21;
992 nxt200x_writebytes(state, 0x0A, buf, 1);
993
994 /* ???*/
995 buf[0] = 0x01;
996 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
997
998 /* write fec mpeg mode */
999 buf[0] = 0x7E;
1000 buf[1] = 0x00;
1001 nxt200x_writebytes(state, 0xE9, buf, 2);
1002
1003 /* write mux selection */
1004 buf[0] = 0x00;
1005 nxt200x_writebytes(state, 0xCC, buf, 1);
1006
1007 /* ???*/
1008 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1009 buf[0] = 0x00;
1010 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1011
1012 /* soft reset? */
1013 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1014 buf[0] = 0x10;
1015 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1016 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1017 buf[0] = 0x00;
1018 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1019
1020 /* ???*/
1021 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1022 buf[0] = 0x01;
1023 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1024 buf[0] = 0x70;
1025 nxt200x_writereg_multibyte(state, 0x81, buf, 1);
1026 buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66;
1027 nxt200x_writereg_multibyte(state, 0x82, buf, 3);
1028
1029 nxt200x_readreg_multibyte(state, 0x88, buf, 1);
1030 buf[0] = 0x11;
1031 nxt200x_writereg_multibyte(state, 0x88, buf, 1);
1032 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1033 buf[0] = 0x40;
1034 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1035
1036 nxt200x_readbytes(state, 0x10, buf, 1);
1037 buf[0] = 0x10;
1038 nxt200x_writebytes(state, 0x10, buf, 1);
1039 nxt200x_readbytes(state, 0x0A, buf, 1);
1040 buf[0] = 0x21;
1041 nxt200x_writebytes(state, 0x0A, buf, 1);
1042
1043 nxt2004_microcontroller_init(state);
1044
1045 buf[0] = 0x21;
1046 nxt200x_writebytes(state, 0x0A, buf, 1);
1047 buf[0] = 0x7E;
1048 nxt200x_writebytes(state, 0xE9, buf, 1);
1049 buf[0] = 0x00;
1050 nxt200x_writebytes(state, 0xEA, buf, 1);
1051
1052 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1053 buf[0] = 0x00;
1054 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1055 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1056 buf[0] = 0x00;
1057 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1058
1059 /* soft reset? */
1060 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1061 buf[0] = 0x10;
1062 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1063 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1064 buf[0] = 0x00;
1065 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1066
1067 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1068 buf[0] = 0x04;
1069 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1070 buf[0] = 0x00;
1071 nxt200x_writereg_multibyte(state, 0x81, buf, 1);
1072 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
1073 nxt200x_writereg_multibyte(state, 0x82, buf, 3);
1074
1075 nxt200x_readreg_multibyte(state, 0x88, buf, 1);
1076 buf[0] = 0x11;
1077 nxt200x_writereg_multibyte(state, 0x88, buf, 1);
1078
1079 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1080 buf[0] = 0x44;
1081 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1082
1083 /* initialize tuner */
1084 nxt200x_readbytes(state, 0x10, buf, 1);
1085 buf[0] = 0x12;
1086 nxt200x_writebytes(state, 0x10, buf, 1);
1087 buf[0] = 0x04;
1088 nxt200x_writebytes(state, 0x13, buf, 1);
1089 buf[0] = 0x00;
1090 nxt200x_writebytes(state, 0x16, buf, 1);
1091 buf[0] = 0x04;
1092 nxt200x_writebytes(state, 0x14, buf, 1);
1093 buf[0] = 0x00;
1094 nxt200x_writebytes(state, 0x14, buf, 1);
1095 nxt200x_writebytes(state, 0x17, buf, 1);
1096 nxt200x_writebytes(state, 0x14, buf, 1);
1097 nxt200x_writebytes(state, 0x17, buf, 1);
1098
1099 return 0;
1100 }
1101
nxt200x_init(struct dvb_frontend * fe)1102 static int nxt200x_init(struct dvb_frontend* fe)
1103 {
1104 struct nxt200x_state* state = fe->demodulator_priv;
1105 int ret = 0;
1106
1107 if (!state->initialised) {
1108 switch (state->demod_chip) {
1109 case NXT2002:
1110 ret = nxt2002_init(fe);
1111 break;
1112 case NXT2004:
1113 ret = nxt2004_init(fe);
1114 break;
1115 default:
1116 return -EINVAL;
1117 break;
1118 }
1119 state->initialised = 1;
1120 }
1121 return ret;
1122 }
1123
nxt200x_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fesettings)1124 static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1125 {
1126 fesettings->min_delay_ms = 500;
1127 fesettings->step_size = 0;
1128 fesettings->max_drift = 0;
1129 return 0;
1130 }
1131
nxt200x_release(struct dvb_frontend * fe)1132 static void nxt200x_release(struct dvb_frontend* fe)
1133 {
1134 struct nxt200x_state* state = fe->demodulator_priv;
1135 kfree(state);
1136 }
1137
1138 static const struct dvb_frontend_ops nxt200x_ops;
1139
nxt200x_attach(const struct nxt200x_config * config,struct i2c_adapter * i2c)1140 struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config,
1141 struct i2c_adapter* i2c)
1142 {
1143 struct nxt200x_state* state = NULL;
1144 u8 buf [] = {0,0,0,0,0};
1145
1146 /* allocate memory for the internal state */
1147 state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL);
1148 if (state == NULL)
1149 goto error;
1150
1151 /* setup the state */
1152 state->config = config;
1153 state->i2c = i2c;
1154 state->initialised = 0;
1155
1156 /* read card id */
1157 nxt200x_readbytes(state, 0x00, buf, 5);
1158 dprintk("NXT info: %*ph\n", 5, buf);
1159
1160 /* set demod chip */
1161 switch (buf[0]) {
1162 case 0x04:
1163 state->demod_chip = NXT2002;
1164 pr_info("NXT2002 Detected\n");
1165 break;
1166 case 0x05:
1167 state->demod_chip = NXT2004;
1168 pr_info("NXT2004 Detected\n");
1169 break;
1170 default:
1171 goto error;
1172 }
1173
1174 /* make sure demod chip is supported */
1175 switch (state->demod_chip) {
1176 case NXT2002:
1177 if (buf[0] != 0x04) goto error; /* device id */
1178 if (buf[1] != 0x02) goto error; /* fab id */
1179 if (buf[2] != 0x11) goto error; /* month */
1180 if (buf[3] != 0x20) goto error; /* year msb */
1181 if (buf[4] != 0x00) goto error; /* year lsb */
1182 break;
1183 case NXT2004:
1184 if (buf[0] != 0x05) goto error; /* device id */
1185 break;
1186 default:
1187 goto error;
1188 }
1189
1190 /* create dvb_frontend */
1191 memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops));
1192 state->frontend.demodulator_priv = state;
1193 return &state->frontend;
1194
1195 error:
1196 kfree(state);
1197 pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf);
1198 return NULL;
1199 }
1200
1201 static const struct dvb_frontend_ops nxt200x_ops = {
1202 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1203 .info = {
1204 .name = "Nextwave NXT200X VSB/QAM frontend",
1205 .frequency_min_hz = 54 * MHz,
1206 .frequency_max_hz = 860 * MHz,
1207 .frequency_stepsize_hz = 166666, /* stepsize is just a guess */
1208 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1209 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1210 FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
1211 },
1212
1213 .release = nxt200x_release,
1214
1215 .init = nxt200x_init,
1216 .sleep = nxt200x_sleep,
1217
1218 .set_frontend = nxt200x_setup_frontend_parameters,
1219 .get_tune_settings = nxt200x_get_tune_settings,
1220
1221 .read_status = nxt200x_read_status,
1222 .read_ber = nxt200x_read_ber,
1223 .read_signal_strength = nxt200x_read_signal_strength,
1224 .read_snr = nxt200x_read_snr,
1225 .read_ucblocks = nxt200x_read_ucblocks,
1226 };
1227
1228 module_param(debug, int, 0644);
1229 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1230
1231 MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
1232 MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob");
1233 MODULE_LICENSE("GPL");
1234
1235 EXPORT_SYMBOL(nxt200x_attach);
1236
1237
