1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADIS16480 and similar IMUs driver
4 *
5 * Copyright 2012 Analog Devices Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/bitfield.h>
10 #include <linux/of_irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/delay.h>
13 #include <linux/mutex.h>
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/spi/spi.h>
17 #include <linux/slab.h>
18 #include <linux/sysfs.h>
19 #include <linux/module.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/imu/adis.h>
25
26 #include <linux/debugfs.h>
27
28 #define ADIS16480_PAGE_SIZE 0x80
29
30 #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
31
32 #define ADIS16480_REG_PAGE_ID 0x00 /* Same address on each page */
33 #define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06)
34 #define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08)
35 #define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A)
36 #define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C)
37 #define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E)
38 #define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10)
39 #define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14)
40 #define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18)
41 #define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C)
42 #define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20)
43 #define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24)
44 #define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28)
45 #define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A)
46 #define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C)
47 #define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E)
48 #define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40)
49 #define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44)
50 #define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48)
51 #define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C)
52 #define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50)
53 #define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54)
54 #define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E)
55
56 #define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04)
57 #define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06)
58 #define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08)
59 #define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A)
60 #define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C)
61 #define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E)
62 #define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10)
63 #define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14)
64 #define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18)
65 #define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C)
66 #define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20)
67 #define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24)
68 #define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28)
69 #define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A)
70 #define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C)
71 #define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40)
72 #define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C)
73
74 #define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02)
75 #define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06)
76 #define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08)
77 #define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A)
78 #define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C)
79 #define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10)
80 #define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16)
81 #define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18)
82 #define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20)
83 #define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22)
84 #define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24)
85 #define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28)
86 #define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A)
87 #define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C)
88 #define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E)
89 #define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30)
90 #define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32)
91 #define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34)
92 #define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36)
93 #define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38)
94 #define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A)
95 #define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78)
96 #define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A)
97 #define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C)
98
99 /*
100 * External clock scaling in PPS mode.
101 * Available only for ADIS1649x devices
102 */
103 #define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10)
104
105 #define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20)
106
107 /* Each filter coefficent bank spans two pages */
108 #define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
109 ADIS16480_REG((page) + 1, (x) - 60 + 8))
110 #define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x))
111 #define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x))
112 #define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x))
113 #define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x))
114
115 /* ADIS16480_REG_FNCTIO_CTRL */
116 #define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0)
117 #define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
118 #define ADIS16480_DRDY_POL_MSK BIT(2)
119 #define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
120 #define ADIS16480_DRDY_EN_MSK BIT(3)
121 #define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
122 #define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4)
123 #define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
124 #define ADIS16480_SYNC_EN_MSK BIT(7)
125 #define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
126 #define ADIS16480_SYNC_MODE_MSK BIT(8)
127 #define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
128
129 struct adis16480_chip_info {
130 unsigned int num_channels;
131 const struct iio_chan_spec *channels;
132 unsigned int gyro_max_val;
133 unsigned int gyro_max_scale;
134 unsigned int accel_max_val;
135 unsigned int accel_max_scale;
136 unsigned int temp_scale;
137 unsigned int int_clk;
138 unsigned int max_dec_rate;
139 const unsigned int *filter_freqs;
140 bool has_pps_clk_mode;
141 };
142
143 enum adis16480_int_pin {
144 ADIS16480_PIN_DIO1,
145 ADIS16480_PIN_DIO2,
146 ADIS16480_PIN_DIO3,
147 ADIS16480_PIN_DIO4
148 };
149
150 enum adis16480_clock_mode {
151 ADIS16480_CLK_SYNC,
152 ADIS16480_CLK_PPS,
153 ADIS16480_CLK_INT
154 };
155
156 struct adis16480 {
157 const struct adis16480_chip_info *chip_info;
158
159 struct adis adis;
160 struct clk *ext_clk;
161 enum adis16480_clock_mode clk_mode;
162 unsigned int clk_freq;
163 };
164
165 static const char * const adis16480_int_pin_names[4] = {
166 [ADIS16480_PIN_DIO1] = "DIO1",
167 [ADIS16480_PIN_DIO2] = "DIO2",
168 [ADIS16480_PIN_DIO3] = "DIO3",
169 [ADIS16480_PIN_DIO4] = "DIO4",
170 };
171
172 #ifdef CONFIG_DEBUG_FS
173
adis16480_show_firmware_revision(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)174 static ssize_t adis16480_show_firmware_revision(struct file *file,
175 char __user *userbuf, size_t count, loff_t *ppos)
176 {
177 struct adis16480 *adis16480 = file->private_data;
178 char buf[7];
179 size_t len;
180 u16 rev;
181 int ret;
182
183 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
184 if (ret < 0)
185 return ret;
186
187 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
188
189 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
190 }
191
192 static const struct file_operations adis16480_firmware_revision_fops = {
193 .open = simple_open,
194 .read = adis16480_show_firmware_revision,
195 .llseek = default_llseek,
196 .owner = THIS_MODULE,
197 };
198
adis16480_show_firmware_date(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)199 static ssize_t adis16480_show_firmware_date(struct file *file,
200 char __user *userbuf, size_t count, loff_t *ppos)
201 {
202 struct adis16480 *adis16480 = file->private_data;
203 u16 md, year;
204 char buf[12];
205 size_t len;
206 int ret;
207
208 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
209 if (ret < 0)
210 return ret;
211
212 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
213 if (ret < 0)
214 return ret;
215
216 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
217 md >> 8, md & 0xff, year);
218
219 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
220 }
221
222 static const struct file_operations adis16480_firmware_date_fops = {
223 .open = simple_open,
224 .read = adis16480_show_firmware_date,
225 .llseek = default_llseek,
226 .owner = THIS_MODULE,
227 };
228
adis16480_show_serial_number(void * arg,u64 * val)229 static int adis16480_show_serial_number(void *arg, u64 *val)
230 {
231 struct adis16480 *adis16480 = arg;
232 u16 serial;
233 int ret;
234
235 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
236 &serial);
237 if (ret < 0)
238 return ret;
239
240 *val = serial;
241
242 return 0;
243 }
244 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
245 adis16480_show_serial_number, NULL, "0x%.4llx\n");
246
adis16480_show_product_id(void * arg,u64 * val)247 static int adis16480_show_product_id(void *arg, u64 *val)
248 {
249 struct adis16480 *adis16480 = arg;
250 u16 prod_id;
251 int ret;
252
253 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
254 &prod_id);
255 if (ret < 0)
256 return ret;
257
258 *val = prod_id;
259
260 return 0;
261 }
262 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
263 adis16480_show_product_id, NULL, "%llu\n");
264
adis16480_show_flash_count(void * arg,u64 * val)265 static int adis16480_show_flash_count(void *arg, u64 *val)
266 {
267 struct adis16480 *adis16480 = arg;
268 u32 flash_count;
269 int ret;
270
271 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
272 &flash_count);
273 if (ret < 0)
274 return ret;
275
276 *val = flash_count;
277
278 return 0;
279 }
280 DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
281 adis16480_show_flash_count, NULL, "%lld\n");
282
adis16480_debugfs_init(struct iio_dev * indio_dev)283 static int adis16480_debugfs_init(struct iio_dev *indio_dev)
284 {
285 struct adis16480 *adis16480 = iio_priv(indio_dev);
286
287 debugfs_create_file_unsafe("firmware_revision", 0400,
288 indio_dev->debugfs_dentry, adis16480,
289 &adis16480_firmware_revision_fops);
290 debugfs_create_file_unsafe("firmware_date", 0400,
291 indio_dev->debugfs_dentry, adis16480,
292 &adis16480_firmware_date_fops);
293 debugfs_create_file_unsafe("serial_number", 0400,
294 indio_dev->debugfs_dentry, adis16480,
295 &adis16480_serial_number_fops);
296 debugfs_create_file_unsafe("product_id", 0400,
297 indio_dev->debugfs_dentry, adis16480,
298 &adis16480_product_id_fops);
299 debugfs_create_file_unsafe("flash_count", 0400,
300 indio_dev->debugfs_dentry, adis16480,
301 &adis16480_flash_count_fops);
302
303 return 0;
304 }
305
306 #else
307
adis16480_debugfs_init(struct iio_dev * indio_dev)308 static int adis16480_debugfs_init(struct iio_dev *indio_dev)
309 {
310 return 0;
311 }
312
313 #endif
314
adis16480_set_freq(struct iio_dev * indio_dev,int val,int val2)315 static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
316 {
317 struct adis16480 *st = iio_priv(indio_dev);
318 unsigned int t, reg;
319
320 if (val < 0 || val2 < 0)
321 return -EINVAL;
322
323 t = val * 1000 + val2 / 1000;
324 if (t == 0)
325 return -EINVAL;
326
327 /*
328 * When using PPS mode, the rate of data collection is equal to the
329 * product of the external clock frequency and the scale factor in the
330 * SYNC_SCALE register.
331 * When using sync mode, or internal clock, the output data rate is
332 * equal with the clock frequency divided by DEC_RATE + 1.
333 */
334 if (st->clk_mode == ADIS16480_CLK_PPS) {
335 t = t / st->clk_freq;
336 reg = ADIS16495_REG_SYNC_SCALE;
337 } else {
338 t = st->clk_freq / t;
339 reg = ADIS16480_REG_DEC_RATE;
340 }
341
342 if (t > st->chip_info->max_dec_rate)
343 t = st->chip_info->max_dec_rate;
344
345 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS))
346 t--;
347
348 return adis_write_reg_16(&st->adis, reg, t);
349 }
350
adis16480_get_freq(struct iio_dev * indio_dev,int * val,int * val2)351 static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
352 {
353 struct adis16480 *st = iio_priv(indio_dev);
354 uint16_t t;
355 int ret;
356 unsigned freq;
357 unsigned int reg;
358
359 if (st->clk_mode == ADIS16480_CLK_PPS)
360 reg = ADIS16495_REG_SYNC_SCALE;
361 else
362 reg = ADIS16480_REG_DEC_RATE;
363
364 ret = adis_read_reg_16(&st->adis, reg, &t);
365 if (ret < 0)
366 return ret;
367
368 /*
369 * When using PPS mode, the rate of data collection is equal to the
370 * product of the external clock frequency and the scale factor in the
371 * SYNC_SCALE register.
372 * When using sync mode, or internal clock, the output data rate is
373 * equal with the clock frequency divided by DEC_RATE + 1.
374 */
375 if (st->clk_mode == ADIS16480_CLK_PPS)
376 freq = st->clk_freq * t;
377 else
378 freq = st->clk_freq / (t + 1);
379
380 *val = freq / 1000;
381 *val2 = (freq % 1000) * 1000;
382
383 return IIO_VAL_INT_PLUS_MICRO;
384 }
385
386 enum {
387 ADIS16480_SCAN_GYRO_X,
388 ADIS16480_SCAN_GYRO_Y,
389 ADIS16480_SCAN_GYRO_Z,
390 ADIS16480_SCAN_ACCEL_X,
391 ADIS16480_SCAN_ACCEL_Y,
392 ADIS16480_SCAN_ACCEL_Z,
393 ADIS16480_SCAN_MAGN_X,
394 ADIS16480_SCAN_MAGN_Y,
395 ADIS16480_SCAN_MAGN_Z,
396 ADIS16480_SCAN_BARO,
397 ADIS16480_SCAN_TEMP,
398 };
399
400 static const unsigned int adis16480_calibbias_regs[] = {
401 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
402 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
403 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
404 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
405 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
406 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
407 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
408 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
409 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
410 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
411 };
412
413 static const unsigned int adis16480_calibscale_regs[] = {
414 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
415 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
416 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
417 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
418 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
419 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
420 };
421
adis16480_set_calibbias(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int bias)422 static int adis16480_set_calibbias(struct iio_dev *indio_dev,
423 const struct iio_chan_spec *chan, int bias)
424 {
425 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
426 struct adis16480 *st = iio_priv(indio_dev);
427
428 switch (chan->type) {
429 case IIO_MAGN:
430 case IIO_PRESSURE:
431 if (bias < -0x8000 || bias >= 0x8000)
432 return -EINVAL;
433 return adis_write_reg_16(&st->adis, reg, bias);
434 case IIO_ANGL_VEL:
435 case IIO_ACCEL:
436 return adis_write_reg_32(&st->adis, reg, bias);
437 default:
438 break;
439 }
440
441 return -EINVAL;
442 }
443
adis16480_get_calibbias(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * bias)444 static int adis16480_get_calibbias(struct iio_dev *indio_dev,
445 const struct iio_chan_spec *chan, int *bias)
446 {
447 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
448 struct adis16480 *st = iio_priv(indio_dev);
449 uint16_t val16;
450 uint32_t val32;
451 int ret;
452
453 switch (chan->type) {
454 case IIO_MAGN:
455 case IIO_PRESSURE:
456 ret = adis_read_reg_16(&st->adis, reg, &val16);
457 *bias = sign_extend32(val16, 15);
458 break;
459 case IIO_ANGL_VEL:
460 case IIO_ACCEL:
461 ret = adis_read_reg_32(&st->adis, reg, &val32);
462 *bias = sign_extend32(val32, 31);
463 break;
464 default:
465 ret = -EINVAL;
466 }
467
468 if (ret < 0)
469 return ret;
470
471 return IIO_VAL_INT;
472 }
473
adis16480_set_calibscale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int scale)474 static int adis16480_set_calibscale(struct iio_dev *indio_dev,
475 const struct iio_chan_spec *chan, int scale)
476 {
477 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
478 struct adis16480 *st = iio_priv(indio_dev);
479
480 if (scale < -0x8000 || scale >= 0x8000)
481 return -EINVAL;
482
483 return adis_write_reg_16(&st->adis, reg, scale);
484 }
485
adis16480_get_calibscale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * scale)486 static int adis16480_get_calibscale(struct iio_dev *indio_dev,
487 const struct iio_chan_spec *chan, int *scale)
488 {
489 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
490 struct adis16480 *st = iio_priv(indio_dev);
491 uint16_t val16;
492 int ret;
493
494 ret = adis_read_reg_16(&st->adis, reg, &val16);
495 if (ret < 0)
496 return ret;
497
498 *scale = sign_extend32(val16, 15);
499 return IIO_VAL_INT;
500 }
501
502 static const unsigned int adis16480_def_filter_freqs[] = {
503 310,
504 55,
505 275,
506 63,
507 };
508
509 static const unsigned int adis16495_def_filter_freqs[] = {
510 300,
511 100,
512 300,
513 100,
514 };
515
516 static const unsigned int ad16480_filter_data[][2] = {
517 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 },
518 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 },
519 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 },
520 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 },
521 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 },
522 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 },
523 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 },
524 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 },
525 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 },
526 };
527
adis16480_get_filter_freq(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * freq)528 static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
529 const struct iio_chan_spec *chan, int *freq)
530 {
531 struct adis16480 *st = iio_priv(indio_dev);
532 unsigned int enable_mask, offset, reg;
533 uint16_t val;
534 int ret;
535
536 reg = ad16480_filter_data[chan->scan_index][0];
537 offset = ad16480_filter_data[chan->scan_index][1];
538 enable_mask = BIT(offset + 2);
539
540 ret = adis_read_reg_16(&st->adis, reg, &val);
541 if (ret < 0)
542 return ret;
543
544 if (!(val & enable_mask))
545 *freq = 0;
546 else
547 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
548
549 return IIO_VAL_INT;
550 }
551
adis16480_set_filter_freq(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int freq)552 static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
553 const struct iio_chan_spec *chan, unsigned int freq)
554 {
555 struct adis16480 *st = iio_priv(indio_dev);
556 unsigned int enable_mask, offset, reg;
557 unsigned int diff, best_diff;
558 unsigned int i, best_freq;
559 uint16_t val;
560 int ret;
561
562 reg = ad16480_filter_data[chan->scan_index][0];
563 offset = ad16480_filter_data[chan->scan_index][1];
564 enable_mask = BIT(offset + 2);
565
566 ret = adis_read_reg_16(&st->adis, reg, &val);
567 if (ret < 0)
568 return ret;
569
570 if (freq == 0) {
571 val &= ~enable_mask;
572 } else {
573 best_freq = 0;
574 best_diff = st->chip_info->filter_freqs[0];
575 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
576 if (st->chip_info->filter_freqs[i] >= freq) {
577 diff = st->chip_info->filter_freqs[i] - freq;
578 if (diff < best_diff) {
579 best_diff = diff;
580 best_freq = i;
581 }
582 }
583 }
584
585 val &= ~(0x3 << offset);
586 val |= best_freq << offset;
587 val |= enable_mask;
588 }
589
590 return adis_write_reg_16(&st->adis, reg, val);
591 }
592
adis16480_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)593 static int adis16480_read_raw(struct iio_dev *indio_dev,
594 const struct iio_chan_spec *chan, int *val, int *val2, long info)
595 {
596 struct adis16480 *st = iio_priv(indio_dev);
597 unsigned int temp;
598
599 switch (info) {
600 case IIO_CHAN_INFO_RAW:
601 return adis_single_conversion(indio_dev, chan, 0, val);
602 case IIO_CHAN_INFO_SCALE:
603 switch (chan->type) {
604 case IIO_ANGL_VEL:
605 *val = st->chip_info->gyro_max_scale;
606 *val2 = st->chip_info->gyro_max_val;
607 return IIO_VAL_FRACTIONAL;
608 case IIO_ACCEL:
609 *val = st->chip_info->accel_max_scale;
610 *val2 = st->chip_info->accel_max_val;
611 return IIO_VAL_FRACTIONAL;
612 case IIO_MAGN:
613 *val = 0;
614 *val2 = 100; /* 0.0001 gauss */
615 return IIO_VAL_INT_PLUS_MICRO;
616 case IIO_TEMP:
617 /*
618 * +85 degrees Celsius = temp_max_scale
619 * +25 degrees Celsius = 0
620 * LSB, 25 degrees Celsius = 60 / temp_max_scale
621 */
622 *val = st->chip_info->temp_scale / 1000;
623 *val2 = (st->chip_info->temp_scale % 1000) * 1000;
624 return IIO_VAL_INT_PLUS_MICRO;
625 case IIO_PRESSURE:
626 *val = 0;
627 *val2 = 4000; /* 40ubar = 0.004 kPa */
628 return IIO_VAL_INT_PLUS_MICRO;
629 default:
630 return -EINVAL;
631 }
632 case IIO_CHAN_INFO_OFFSET:
633 /* Only the temperature channel has a offset */
634 temp = 25 * 1000000LL; /* 25 degree Celsius = 0x0000 */
635 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
636 return IIO_VAL_INT;
637 case IIO_CHAN_INFO_CALIBBIAS:
638 return adis16480_get_calibbias(indio_dev, chan, val);
639 case IIO_CHAN_INFO_CALIBSCALE:
640 return adis16480_get_calibscale(indio_dev, chan, val);
641 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
642 return adis16480_get_filter_freq(indio_dev, chan, val);
643 case IIO_CHAN_INFO_SAMP_FREQ:
644 return adis16480_get_freq(indio_dev, val, val2);
645 default:
646 return -EINVAL;
647 }
648 }
649
adis16480_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long info)650 static int adis16480_write_raw(struct iio_dev *indio_dev,
651 const struct iio_chan_spec *chan, int val, int val2, long info)
652 {
653 switch (info) {
654 case IIO_CHAN_INFO_CALIBBIAS:
655 return adis16480_set_calibbias(indio_dev, chan, val);
656 case IIO_CHAN_INFO_CALIBSCALE:
657 return adis16480_set_calibscale(indio_dev, chan, val);
658 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
659 return adis16480_set_filter_freq(indio_dev, chan, val);
660 case IIO_CHAN_INFO_SAMP_FREQ:
661 return adis16480_set_freq(indio_dev, val, val2);
662
663 default:
664 return -EINVAL;
665 }
666 }
667
668 #define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
669 { \
670 .type = (_type), \
671 .modified = 1, \
672 .channel2 = (_mod), \
673 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
674 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
675 _info_sep, \
676 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
677 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
678 .address = (_address), \
679 .scan_index = (_si), \
680 .scan_type = { \
681 .sign = 's', \
682 .realbits = (_bits), \
683 .storagebits = (_bits), \
684 .endianness = IIO_BE, \
685 }, \
686 }
687
688 #define ADIS16480_GYRO_CHANNEL(_mod) \
689 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
690 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
691 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
692 BIT(IIO_CHAN_INFO_CALIBSCALE), \
693 32)
694
695 #define ADIS16480_ACCEL_CHANNEL(_mod) \
696 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
697 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
698 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
699 BIT(IIO_CHAN_INFO_CALIBSCALE), \
700 32)
701
702 #define ADIS16480_MAGN_CHANNEL(_mod) \
703 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
704 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
705 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
706 16)
707
708 #define ADIS16480_PRESSURE_CHANNEL() \
709 { \
710 .type = IIO_PRESSURE, \
711 .indexed = 1, \
712 .channel = 0, \
713 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
714 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
715 BIT(IIO_CHAN_INFO_SCALE), \
716 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
717 .address = ADIS16480_REG_BAROM_OUT, \
718 .scan_index = ADIS16480_SCAN_BARO, \
719 .scan_type = { \
720 .sign = 's', \
721 .realbits = 32, \
722 .storagebits = 32, \
723 .endianness = IIO_BE, \
724 }, \
725 }
726
727 #define ADIS16480_TEMP_CHANNEL() { \
728 .type = IIO_TEMP, \
729 .indexed = 1, \
730 .channel = 0, \
731 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
732 BIT(IIO_CHAN_INFO_SCALE) | \
733 BIT(IIO_CHAN_INFO_OFFSET), \
734 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
735 .address = ADIS16480_REG_TEMP_OUT, \
736 .scan_index = ADIS16480_SCAN_TEMP, \
737 .scan_type = { \
738 .sign = 's', \
739 .realbits = 16, \
740 .storagebits = 16, \
741 .endianness = IIO_BE, \
742 }, \
743 }
744
745 static const struct iio_chan_spec adis16480_channels[] = {
746 ADIS16480_GYRO_CHANNEL(X),
747 ADIS16480_GYRO_CHANNEL(Y),
748 ADIS16480_GYRO_CHANNEL(Z),
749 ADIS16480_ACCEL_CHANNEL(X),
750 ADIS16480_ACCEL_CHANNEL(Y),
751 ADIS16480_ACCEL_CHANNEL(Z),
752 ADIS16480_MAGN_CHANNEL(X),
753 ADIS16480_MAGN_CHANNEL(Y),
754 ADIS16480_MAGN_CHANNEL(Z),
755 ADIS16480_PRESSURE_CHANNEL(),
756 ADIS16480_TEMP_CHANNEL(),
757 IIO_CHAN_SOFT_TIMESTAMP(11)
758 };
759
760 static const struct iio_chan_spec adis16485_channels[] = {
761 ADIS16480_GYRO_CHANNEL(X),
762 ADIS16480_GYRO_CHANNEL(Y),
763 ADIS16480_GYRO_CHANNEL(Z),
764 ADIS16480_ACCEL_CHANNEL(X),
765 ADIS16480_ACCEL_CHANNEL(Y),
766 ADIS16480_ACCEL_CHANNEL(Z),
767 ADIS16480_TEMP_CHANNEL(),
768 IIO_CHAN_SOFT_TIMESTAMP(7)
769 };
770
771 enum adis16480_variant {
772 ADIS16375,
773 ADIS16480,
774 ADIS16485,
775 ADIS16488,
776 ADIS16495_1,
777 ADIS16495_2,
778 ADIS16495_3,
779 ADIS16497_1,
780 ADIS16497_2,
781 ADIS16497_3,
782 };
783
784 static const struct adis16480_chip_info adis16480_chip_info[] = {
785 [ADIS16375] = {
786 .channels = adis16485_channels,
787 .num_channels = ARRAY_SIZE(adis16485_channels),
788 /*
789 * storing the value in rad/degree and the scale in degree
790 * gives us the result in rad and better precession than
791 * storing the scale directly in rad.
792 */
793 .gyro_max_val = IIO_RAD_TO_DEGREE(22887),
794 .gyro_max_scale = 300,
795 .accel_max_val = IIO_M_S_2_TO_G(21973),
796 .accel_max_scale = 18,
797 .temp_scale = 5650, /* 5.65 milli degree Celsius */
798 .int_clk = 2460000,
799 .max_dec_rate = 2048,
800 .filter_freqs = adis16480_def_filter_freqs,
801 },
802 [ADIS16480] = {
803 .channels = adis16480_channels,
804 .num_channels = ARRAY_SIZE(adis16480_channels),
805 .gyro_max_val = IIO_RAD_TO_DEGREE(22500),
806 .gyro_max_scale = 450,
807 .accel_max_val = IIO_M_S_2_TO_G(12500),
808 .accel_max_scale = 10,
809 .temp_scale = 5650, /* 5.65 milli degree Celsius */
810 .int_clk = 2460000,
811 .max_dec_rate = 2048,
812 .filter_freqs = adis16480_def_filter_freqs,
813 },
814 [ADIS16485] = {
815 .channels = adis16485_channels,
816 .num_channels = ARRAY_SIZE(adis16485_channels),
817 .gyro_max_val = IIO_RAD_TO_DEGREE(22500),
818 .gyro_max_scale = 450,
819 .accel_max_val = IIO_M_S_2_TO_G(20000),
820 .accel_max_scale = 5,
821 .temp_scale = 5650, /* 5.65 milli degree Celsius */
822 .int_clk = 2460000,
823 .max_dec_rate = 2048,
824 .filter_freqs = adis16480_def_filter_freqs,
825 },
826 [ADIS16488] = {
827 .channels = adis16480_channels,
828 .num_channels = ARRAY_SIZE(adis16480_channels),
829 .gyro_max_val = IIO_RAD_TO_DEGREE(22500),
830 .gyro_max_scale = 450,
831 .accel_max_val = IIO_M_S_2_TO_G(22500),
832 .accel_max_scale = 18,
833 .temp_scale = 5650, /* 5.65 milli degree Celsius */
834 .int_clk = 2460000,
835 .max_dec_rate = 2048,
836 .filter_freqs = adis16480_def_filter_freqs,
837 },
838 [ADIS16495_1] = {
839 .channels = adis16485_channels,
840 .num_channels = ARRAY_SIZE(adis16485_channels),
841 .gyro_max_val = IIO_RAD_TO_DEGREE(20000),
842 .gyro_max_scale = 125,
843 .accel_max_val = IIO_M_S_2_TO_G(32000),
844 .accel_max_scale = 8,
845 .temp_scale = 12500, /* 12.5 milli degree Celsius */
846 .int_clk = 4250000,
847 .max_dec_rate = 4250,
848 .filter_freqs = adis16495_def_filter_freqs,
849 .has_pps_clk_mode = true,
850 },
851 [ADIS16495_2] = {
852 .channels = adis16485_channels,
853 .num_channels = ARRAY_SIZE(adis16485_channels),
854 .gyro_max_val = IIO_RAD_TO_DEGREE(18000),
855 .gyro_max_scale = 450,
856 .accel_max_val = IIO_M_S_2_TO_G(32000),
857 .accel_max_scale = 8,
858 .temp_scale = 12500, /* 12.5 milli degree Celsius */
859 .int_clk = 4250000,
860 .max_dec_rate = 4250,
861 .filter_freqs = adis16495_def_filter_freqs,
862 .has_pps_clk_mode = true,
863 },
864 [ADIS16495_3] = {
865 .channels = adis16485_channels,
866 .num_channels = ARRAY_SIZE(adis16485_channels),
867 .gyro_max_val = IIO_RAD_TO_DEGREE(20000),
868 .gyro_max_scale = 2000,
869 .accel_max_val = IIO_M_S_2_TO_G(32000),
870 .accel_max_scale = 8,
871 .temp_scale = 12500, /* 12.5 milli degree Celsius */
872 .int_clk = 4250000,
873 .max_dec_rate = 4250,
874 .filter_freqs = adis16495_def_filter_freqs,
875 .has_pps_clk_mode = true,
876 },
877 [ADIS16497_1] = {
878 .channels = adis16485_channels,
879 .num_channels = ARRAY_SIZE(adis16485_channels),
880 .gyro_max_val = IIO_RAD_TO_DEGREE(20000),
881 .gyro_max_scale = 125,
882 .accel_max_val = IIO_M_S_2_TO_G(32000),
883 .accel_max_scale = 40,
884 .temp_scale = 12500, /* 12.5 milli degree Celsius */
885 .int_clk = 4250000,
886 .max_dec_rate = 4250,
887 .filter_freqs = adis16495_def_filter_freqs,
888 .has_pps_clk_mode = true,
889 },
890 [ADIS16497_2] = {
891 .channels = adis16485_channels,
892 .num_channels = ARRAY_SIZE(adis16485_channels),
893 .gyro_max_val = IIO_RAD_TO_DEGREE(18000),
894 .gyro_max_scale = 450,
895 .accel_max_val = IIO_M_S_2_TO_G(32000),
896 .accel_max_scale = 40,
897 .temp_scale = 12500, /* 12.5 milli degree Celsius */
898 .int_clk = 4250000,
899 .max_dec_rate = 4250,
900 .filter_freqs = adis16495_def_filter_freqs,
901 .has_pps_clk_mode = true,
902 },
903 [ADIS16497_3] = {
904 .channels = adis16485_channels,
905 .num_channels = ARRAY_SIZE(adis16485_channels),
906 .gyro_max_val = IIO_RAD_TO_DEGREE(20000),
907 .gyro_max_scale = 2000,
908 .accel_max_val = IIO_M_S_2_TO_G(32000),
909 .accel_max_scale = 40,
910 .temp_scale = 12500, /* 12.5 milli degree Celsius */
911 .int_clk = 4250000,
912 .max_dec_rate = 4250,
913 .filter_freqs = adis16495_def_filter_freqs,
914 .has_pps_clk_mode = true,
915 },
916 };
917
918 static const struct iio_info adis16480_info = {
919 .read_raw = &adis16480_read_raw,
920 .write_raw = &adis16480_write_raw,
921 .update_scan_mode = adis_update_scan_mode,
922 };
923
adis16480_stop_device(struct iio_dev * indio_dev)924 static int adis16480_stop_device(struct iio_dev *indio_dev)
925 {
926 struct adis16480 *st = iio_priv(indio_dev);
927 int ret;
928
929 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
930 if (ret)
931 dev_err(&indio_dev->dev,
932 "Could not power down device: %d\n", ret);
933
934 return ret;
935 }
936
adis16480_enable_irq(struct adis * adis,bool enable)937 static int adis16480_enable_irq(struct adis *adis, bool enable)
938 {
939 uint16_t val;
940 int ret;
941
942 ret = adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
943 if (ret < 0)
944 return ret;
945
946 val &= ~ADIS16480_DRDY_EN_MSK;
947 val |= ADIS16480_DRDY_EN(enable);
948
949 return adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
950 }
951
adis16480_initial_setup(struct iio_dev * indio_dev)952 static int adis16480_initial_setup(struct iio_dev *indio_dev)
953 {
954 struct adis16480 *st = iio_priv(indio_dev);
955 uint16_t prod_id;
956 unsigned int device_id;
957 int ret;
958
959 adis_reset(&st->adis);
960 msleep(70);
961
962 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1));
963 if (ret)
964 return ret;
965 msleep(30);
966
967 ret = adis_check_status(&st->adis);
968 if (ret)
969 return ret;
970
971 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_PROD_ID, &prod_id);
972 if (ret)
973 return ret;
974
975 ret = sscanf(indio_dev->name, "adis%u\n", &device_id);
976 if (ret != 1)
977 return -EINVAL;
978
979 if (prod_id != device_id)
980 dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.",
981 device_id, prod_id);
982
983 return 0;
984 }
985
986 #define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
987 #define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
988 #define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
989 #define ADIS16480_DIAG_STAT_XACCL_FAIL 3
990 #define ADIS16480_DIAG_STAT_YACCL_FAIL 4
991 #define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
992 #define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
993 #define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
994 #define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
995 #define ADIS16480_DIAG_STAT_BARO_FAIL 11
996
997 static const char * const adis16480_status_error_msgs[] = {
998 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
999 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
1000 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
1001 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
1002 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
1003 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
1004 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
1005 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
1006 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
1007 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
1008 };
1009
1010 static const struct adis_data adis16480_data = {
1011 .diag_stat_reg = ADIS16480_REG_DIAG_STS,
1012 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD,
1013 .has_paging = true,
1014
1015 .read_delay = 5,
1016 .write_delay = 5,
1017
1018 .status_error_msgs = adis16480_status_error_msgs,
1019 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) |
1020 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) |
1021 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) |
1022 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) |
1023 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) |
1024 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) |
1025 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) |
1026 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) |
1027 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) |
1028 BIT(ADIS16480_DIAG_STAT_BARO_FAIL),
1029
1030 .enable_irq = adis16480_enable_irq,
1031 };
1032
adis16480_config_irq_pin(struct device_node * of_node,struct adis16480 * st)1033 static int adis16480_config_irq_pin(struct device_node *of_node,
1034 struct adis16480 *st)
1035 {
1036 struct irq_data *desc;
1037 enum adis16480_int_pin pin;
1038 unsigned int irq_type;
1039 uint16_t val;
1040 int i, irq = 0;
1041
1042 desc = irq_get_irq_data(st->adis.spi->irq);
1043 if (!desc) {
1044 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq);
1045 return -EINVAL;
1046 }
1047
1048 /* Disable data ready since the default after reset is on */
1049 val = ADIS16480_DRDY_EN(0);
1050
1051 /*
1052 * Get the interrupt from the devicetre by reading the interrupt-names
1053 * property. If it is not specified, use DIO1 pin as default.
1054 * According to the datasheet, the factory default assigns DIO2 as data
1055 * ready signal. However, in the previous versions of the driver, DIO1
1056 * pin was used. So, we should leave it as is since some devices might
1057 * be expecting the interrupt on the wrong physical pin.
1058 */
1059 pin = ADIS16480_PIN_DIO1;
1060 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1061 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]);
1062 if (irq > 0) {
1063 pin = i;
1064 break;
1065 }
1066 }
1067
1068 val |= ADIS16480_DRDY_SEL(pin);
1069
1070 /*
1071 * Get the interrupt line behaviour. The data ready polarity can be
1072 * configured as positive or negative, corresponding to
1073 * IRQF_TRIGGER_RISING or IRQF_TRIGGER_FALLING respectively.
1074 */
1075 irq_type = irqd_get_trigger_type(desc);
1076 if (irq_type == IRQF_TRIGGER_RISING) { /* Default */
1077 val |= ADIS16480_DRDY_POL(1);
1078 } else if (irq_type == IRQF_TRIGGER_FALLING) {
1079 val |= ADIS16480_DRDY_POL(0);
1080 } else {
1081 dev_err(&st->adis.spi->dev,
1082 "Invalid interrupt type 0x%x specified\n", irq_type);
1083 return -EINVAL;
1084 }
1085 /* Write the data ready configuration to the FNCTIO_CTRL register */
1086 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1087 }
1088
adis16480_of_get_ext_clk_pin(struct adis16480 * st,struct device_node * of_node)1089 static int adis16480_of_get_ext_clk_pin(struct adis16480 *st,
1090 struct device_node *of_node)
1091 {
1092 const char *ext_clk_pin;
1093 enum adis16480_int_pin pin;
1094 int i;
1095
1096 pin = ADIS16480_PIN_DIO2;
1097 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin))
1098 goto clk_input_not_found;
1099
1100 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1101 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
1102 return i;
1103 }
1104
1105 clk_input_not_found:
1106 dev_info(&st->adis.spi->dev,
1107 "clk input line not specified, using DIO2\n");
1108 return pin;
1109 }
1110
adis16480_ext_clk_config(struct adis16480 * st,struct device_node * of_node,bool enable)1111 static int adis16480_ext_clk_config(struct adis16480 *st,
1112 struct device_node *of_node,
1113 bool enable)
1114 {
1115 unsigned int mode, mask;
1116 enum adis16480_int_pin pin;
1117 uint16_t val;
1118 int ret;
1119
1120 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1121 if (ret < 0)
1122 return ret;
1123
1124 pin = adis16480_of_get_ext_clk_pin(st, of_node);
1125 /*
1126 * Each DIOx pin supports only one function at a time. When a single pin
1127 * has two assignments, the enable bit for a lower priority function
1128 * automatically resets to zero (disabling the lower priority function).
1129 */
1130 if (pin == ADIS16480_DRDY_SEL(val))
1131 dev_warn(&st->adis.spi->dev,
1132 "DIO%x pin supports only one function at a time\n",
1133 pin + 1);
1134
1135 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
1136 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
1137 /* Only ADIS1649x devices support pps ext clock mode */
1138 if (st->chip_info->has_pps_clk_mode) {
1139 mode |= ADIS16480_SYNC_MODE(st->clk_mode);
1140 mask |= ADIS16480_SYNC_MODE_MSK;
1141 }
1142
1143 val &= ~mask;
1144 val |= mode;
1145
1146 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1147 if (ret < 0)
1148 return ret;
1149
1150 return clk_prepare_enable(st->ext_clk);
1151 }
1152
adis16480_get_ext_clocks(struct adis16480 * st)1153 static int adis16480_get_ext_clocks(struct adis16480 *st)
1154 {
1155 st->clk_mode = ADIS16480_CLK_INT;
1156 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync");
1157 if (!IS_ERR_OR_NULL(st->ext_clk)) {
1158 st->clk_mode = ADIS16480_CLK_SYNC;
1159 return 0;
1160 }
1161
1162 if (PTR_ERR(st->ext_clk) != -ENOENT) {
1163 dev_err(&st->adis.spi->dev, "failed to get ext clk\n");
1164 return PTR_ERR(st->ext_clk);
1165 }
1166
1167 if (st->chip_info->has_pps_clk_mode) {
1168 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps");
1169 if (!IS_ERR_OR_NULL(st->ext_clk)) {
1170 st->clk_mode = ADIS16480_CLK_PPS;
1171 return 0;
1172 }
1173
1174 if (PTR_ERR(st->ext_clk) != -ENOENT) {
1175 dev_err(&st->adis.spi->dev, "failed to get ext clk\n");
1176 return PTR_ERR(st->ext_clk);
1177 }
1178 }
1179
1180 return 0;
1181 }
1182
adis16480_probe(struct spi_device * spi)1183 static int adis16480_probe(struct spi_device *spi)
1184 {
1185 const struct spi_device_id *id = spi_get_device_id(spi);
1186 struct iio_dev *indio_dev;
1187 struct adis16480 *st;
1188 int ret;
1189
1190 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1191 if (indio_dev == NULL)
1192 return -ENOMEM;
1193
1194 spi_set_drvdata(spi, indio_dev);
1195
1196 st = iio_priv(indio_dev);
1197
1198 st->chip_info = &adis16480_chip_info[id->driver_data];
1199 indio_dev->dev.parent = &spi->dev;
1200 indio_dev->name = spi_get_device_id(spi)->name;
1201 indio_dev->channels = st->chip_info->channels;
1202 indio_dev->num_channels = st->chip_info->num_channels;
1203 indio_dev->info = &adis16480_info;
1204 indio_dev->modes = INDIO_DIRECT_MODE;
1205
1206 ret = adis_init(&st->adis, indio_dev, spi, &adis16480_data);
1207 if (ret)
1208 return ret;
1209
1210 ret = adis16480_config_irq_pin(spi->dev.of_node, st);
1211 if (ret)
1212 return ret;
1213
1214 ret = adis16480_get_ext_clocks(st);
1215 if (ret)
1216 return ret;
1217
1218 if (!IS_ERR_OR_NULL(st->ext_clk)) {
1219 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true);
1220 if (ret)
1221 return ret;
1222
1223 st->clk_freq = clk_get_rate(st->ext_clk);
1224 st->clk_freq *= 1000; /* micro */
1225 } else {
1226 st->clk_freq = st->chip_info->int_clk;
1227 }
1228
1229 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL);
1230 if (ret)
1231 goto error_clk_disable_unprepare;
1232
1233 ret = adis16480_initial_setup(indio_dev);
1234 if (ret)
1235 goto error_cleanup_buffer;
1236
1237 ret = iio_device_register(indio_dev);
1238 if (ret)
1239 goto error_stop_device;
1240
1241 adis16480_debugfs_init(indio_dev);
1242
1243 return 0;
1244
1245 error_stop_device:
1246 adis16480_stop_device(indio_dev);
1247 error_cleanup_buffer:
1248 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev);
1249 error_clk_disable_unprepare:
1250 clk_disable_unprepare(st->ext_clk);
1251 return ret;
1252 }
1253
adis16480_remove(struct spi_device * spi)1254 static int adis16480_remove(struct spi_device *spi)
1255 {
1256 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1257 struct adis16480 *st = iio_priv(indio_dev);
1258
1259 iio_device_unregister(indio_dev);
1260 adis16480_stop_device(indio_dev);
1261
1262 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev);
1263 clk_disable_unprepare(st->ext_clk);
1264
1265 return 0;
1266 }
1267
1268 static const struct spi_device_id adis16480_ids[] = {
1269 { "adis16375", ADIS16375 },
1270 { "adis16480", ADIS16480 },
1271 { "adis16485", ADIS16485 },
1272 { "adis16488", ADIS16488 },
1273 { "adis16495-1", ADIS16495_1 },
1274 { "adis16495-2", ADIS16495_2 },
1275 { "adis16495-3", ADIS16495_3 },
1276 { "adis16497-1", ADIS16497_1 },
1277 { "adis16497-2", ADIS16497_2 },
1278 { "adis16497-3", ADIS16497_3 },
1279 { }
1280 };
1281 MODULE_DEVICE_TABLE(spi, adis16480_ids);
1282
1283 static const struct of_device_id adis16480_of_match[] = {
1284 { .compatible = "adi,adis16375" },
1285 { .compatible = "adi,adis16480" },
1286 { .compatible = "adi,adis16485" },
1287 { .compatible = "adi,adis16488" },
1288 { .compatible = "adi,adis16495-1" },
1289 { .compatible = "adi,adis16495-2" },
1290 { .compatible = "adi,adis16495-3" },
1291 { .compatible = "adi,adis16497-1" },
1292 { .compatible = "adi,adis16497-2" },
1293 { .compatible = "adi,adis16497-3" },
1294 { },
1295 };
1296 MODULE_DEVICE_TABLE(of, adis16480_of_match);
1297
1298 static struct spi_driver adis16480_driver = {
1299 .driver = {
1300 .name = "adis16480",
1301 .of_match_table = adis16480_of_match,
1302 },
1303 .id_table = adis16480_ids,
1304 .probe = adis16480_probe,
1305 .remove = adis16480_remove,
1306 };
1307 module_spi_driver(adis16480_driver);
1308
1309 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1310 MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
1311 MODULE_LICENSE("GPL v2");
1312
