1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
4 * multi-channel Digital to Analog Converters driver
5 *
6 * Copyright 2011 Analog Devices Inc.
7 */
8
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spi/spi.h>
14 #include <linux/slab.h>
15 #include <linux/sysfs.h>
16 #include <linux/regulator/consumer.h>
17
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20
21 #define AD5360_CMD(x) ((x) << 22)
22 #define AD5360_ADDR(x) ((x) << 16)
23
24 #define AD5360_READBACK_TYPE(x) ((x) << 13)
25 #define AD5360_READBACK_ADDR(x) ((x) << 7)
26
27 #define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
28
29 #define AD5360_CMD_WRITE_DATA 0x3
30 #define AD5360_CMD_WRITE_OFFSET 0x2
31 #define AD5360_CMD_WRITE_GAIN 0x1
32 #define AD5360_CMD_SPECIAL_FUNCTION 0x0
33
34 /* Special function register addresses */
35 #define AD5360_REG_SF_NOP 0x0
36 #define AD5360_REG_SF_CTRL 0x1
37 #define AD5360_REG_SF_OFS(x) (0x2 + (x))
38 #define AD5360_REG_SF_READBACK 0x5
39
40 #define AD5360_SF_CTRL_PWR_DOWN BIT(0)
41
42 #define AD5360_READBACK_X1A 0x0
43 #define AD5360_READBACK_X1B 0x1
44 #define AD5360_READBACK_OFFSET 0x2
45 #define AD5360_READBACK_GAIN 0x3
46 #define AD5360_READBACK_SF 0x4
47
48
49 /**
50 * struct ad5360_chip_info - chip specific information
51 * @channel_template: channel specification template
52 * @num_channels: number of channels
53 * @channels_per_group: number of channels per group
54 * @num_vrefs: number of vref supplies for the chip
55 */
56
57 struct ad5360_chip_info {
58 struct iio_chan_spec channel_template;
59 unsigned int num_channels;
60 unsigned int channels_per_group;
61 unsigned int num_vrefs;
62 };
63
64 /**
65 * struct ad5360_state - driver instance specific data
66 * @spi: spi_device
67 * @chip_info: chip model specific constants, available modes etc
68 * @vref_reg: vref supply regulators
69 * @ctrl: control register cache
70 * @data: spi transfer buffers
71 */
72
73 struct ad5360_state {
74 struct spi_device *spi;
75 const struct ad5360_chip_info *chip_info;
76 struct regulator_bulk_data vref_reg[3];
77 unsigned int ctrl;
78
79 /*
80 * DMA (thus cache coherency maintenance) requires the
81 * transfer buffers to live in their own cache lines.
82 */
83 union {
84 __be32 d32;
85 u8 d8[4];
86 } data[2] ____cacheline_aligned;
87 };
88
89 enum ad5360_type {
90 ID_AD5360,
91 ID_AD5361,
92 ID_AD5362,
93 ID_AD5363,
94 ID_AD5370,
95 ID_AD5371,
96 ID_AD5372,
97 ID_AD5373,
98 };
99
100 #define AD5360_CHANNEL(bits) { \
101 .type = IIO_VOLTAGE, \
102 .indexed = 1, \
103 .output = 1, \
104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
105 BIT(IIO_CHAN_INFO_SCALE) | \
106 BIT(IIO_CHAN_INFO_OFFSET) | \
107 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
108 BIT(IIO_CHAN_INFO_CALIBBIAS), \
109 .scan_type = { \
110 .sign = 'u', \
111 .realbits = (bits), \
112 .storagebits = 16, \
113 .shift = 16 - (bits), \
114 }, \
115 }
116
117 static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
118 [ID_AD5360] = {
119 .channel_template = AD5360_CHANNEL(16),
120 .num_channels = 16,
121 .channels_per_group = 8,
122 .num_vrefs = 2,
123 },
124 [ID_AD5361] = {
125 .channel_template = AD5360_CHANNEL(14),
126 .num_channels = 16,
127 .channels_per_group = 8,
128 .num_vrefs = 2,
129 },
130 [ID_AD5362] = {
131 .channel_template = AD5360_CHANNEL(16),
132 .num_channels = 8,
133 .channels_per_group = 4,
134 .num_vrefs = 2,
135 },
136 [ID_AD5363] = {
137 .channel_template = AD5360_CHANNEL(14),
138 .num_channels = 8,
139 .channels_per_group = 4,
140 .num_vrefs = 2,
141 },
142 [ID_AD5370] = {
143 .channel_template = AD5360_CHANNEL(16),
144 .num_channels = 40,
145 .channels_per_group = 8,
146 .num_vrefs = 2,
147 },
148 [ID_AD5371] = {
149 .channel_template = AD5360_CHANNEL(14),
150 .num_channels = 40,
151 .channels_per_group = 8,
152 .num_vrefs = 3,
153 },
154 [ID_AD5372] = {
155 .channel_template = AD5360_CHANNEL(16),
156 .num_channels = 32,
157 .channels_per_group = 8,
158 .num_vrefs = 2,
159 },
160 [ID_AD5373] = {
161 .channel_template = AD5360_CHANNEL(14),
162 .num_channels = 32,
163 .channels_per_group = 8,
164 .num_vrefs = 2,
165 },
166 };
167
ad5360_get_channel_vref_index(struct ad5360_state * st,unsigned int channel)168 static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
169 unsigned int channel)
170 {
171 unsigned int i;
172
173 /* The first groups have their own vref, while the remaining groups
174 * share the last vref */
175 i = channel / st->chip_info->channels_per_group;
176 if (i >= st->chip_info->num_vrefs)
177 i = st->chip_info->num_vrefs - 1;
178
179 return i;
180 }
181
ad5360_get_channel_vref(struct ad5360_state * st,unsigned int channel)182 static int ad5360_get_channel_vref(struct ad5360_state *st,
183 unsigned int channel)
184 {
185 unsigned int i = ad5360_get_channel_vref_index(st, channel);
186
187 return regulator_get_voltage(st->vref_reg[i].consumer);
188 }
189
190
ad5360_write_unlocked(struct iio_dev * indio_dev,unsigned int cmd,unsigned int addr,unsigned int val,unsigned int shift)191 static int ad5360_write_unlocked(struct iio_dev *indio_dev,
192 unsigned int cmd, unsigned int addr, unsigned int val,
193 unsigned int shift)
194 {
195 struct ad5360_state *st = iio_priv(indio_dev);
196
197 val <<= shift;
198 val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
199 st->data[0].d32 = cpu_to_be32(val);
200
201 return spi_write(st->spi, &st->data[0].d8[1], 3);
202 }
203
ad5360_write(struct iio_dev * indio_dev,unsigned int cmd,unsigned int addr,unsigned int val,unsigned int shift)204 static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
205 unsigned int addr, unsigned int val, unsigned int shift)
206 {
207 int ret;
208
209 mutex_lock(&indio_dev->mlock);
210 ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
211 mutex_unlock(&indio_dev->mlock);
212
213 return ret;
214 }
215
ad5360_read(struct iio_dev * indio_dev,unsigned int type,unsigned int addr)216 static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
217 unsigned int addr)
218 {
219 struct ad5360_state *st = iio_priv(indio_dev);
220 int ret;
221 struct spi_transfer t[] = {
222 {
223 .tx_buf = &st->data[0].d8[1],
224 .len = 3,
225 .cs_change = 1,
226 }, {
227 .rx_buf = &st->data[1].d8[1],
228 .len = 3,
229 },
230 };
231
232 mutex_lock(&indio_dev->mlock);
233
234 st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
235 AD5360_ADDR(AD5360_REG_SF_READBACK) |
236 AD5360_READBACK_TYPE(type) |
237 AD5360_READBACK_ADDR(addr));
238
239 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
240 if (ret >= 0)
241 ret = be32_to_cpu(st->data[1].d32) & 0xffff;
242
243 mutex_unlock(&indio_dev->mlock);
244
245 return ret;
246 }
247
ad5360_read_dac_powerdown(struct device * dev,struct device_attribute * attr,char * buf)248 static ssize_t ad5360_read_dac_powerdown(struct device *dev,
249 struct device_attribute *attr,
250 char *buf)
251 {
252 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
253 struct ad5360_state *st = iio_priv(indio_dev);
254
255 return sprintf(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
256 }
257
ad5360_update_ctrl(struct iio_dev * indio_dev,unsigned int set,unsigned int clr)258 static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
259 unsigned int clr)
260 {
261 struct ad5360_state *st = iio_priv(indio_dev);
262 unsigned int ret;
263
264 mutex_lock(&indio_dev->mlock);
265
266 st->ctrl |= set;
267 st->ctrl &= ~clr;
268
269 ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
270 AD5360_REG_SF_CTRL, st->ctrl, 0);
271
272 mutex_unlock(&indio_dev->mlock);
273
274 return ret;
275 }
276
ad5360_write_dac_powerdown(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)277 static ssize_t ad5360_write_dac_powerdown(struct device *dev,
278 struct device_attribute *attr, const char *buf, size_t len)
279 {
280 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
281 bool pwr_down;
282 int ret;
283
284 ret = strtobool(buf, &pwr_down);
285 if (ret)
286 return ret;
287
288 if (pwr_down)
289 ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
290 else
291 ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
292
293 return ret ? ret : len;
294 }
295
296 static IIO_DEVICE_ATTR(out_voltage_powerdown,
297 S_IRUGO | S_IWUSR,
298 ad5360_read_dac_powerdown,
299 ad5360_write_dac_powerdown, 0);
300
301 static struct attribute *ad5360_attributes[] = {
302 &iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
303 NULL,
304 };
305
306 static const struct attribute_group ad5360_attribute_group = {
307 .attrs = ad5360_attributes,
308 };
309
ad5360_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)310 static int ad5360_write_raw(struct iio_dev *indio_dev,
311 struct iio_chan_spec const *chan,
312 int val,
313 int val2,
314 long mask)
315 {
316 struct ad5360_state *st = iio_priv(indio_dev);
317 int max_val = (1 << chan->scan_type.realbits);
318 unsigned int ofs_index;
319
320 switch (mask) {
321 case IIO_CHAN_INFO_RAW:
322 if (val >= max_val || val < 0)
323 return -EINVAL;
324
325 return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
326 chan->address, val, chan->scan_type.shift);
327
328 case IIO_CHAN_INFO_CALIBBIAS:
329 if (val >= max_val || val < 0)
330 return -EINVAL;
331
332 return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
333 chan->address, val, chan->scan_type.shift);
334
335 case IIO_CHAN_INFO_CALIBSCALE:
336 if (val >= max_val || val < 0)
337 return -EINVAL;
338
339 return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
340 chan->address, val, chan->scan_type.shift);
341
342 case IIO_CHAN_INFO_OFFSET:
343 if (val <= -max_val || val > 0)
344 return -EINVAL;
345
346 val = -val;
347
348 /* offset is supposed to have the same scale as raw, but it
349 * is always 14bits wide, so on a chip where the raw value has
350 * more bits, we need to shift offset. */
351 val >>= (chan->scan_type.realbits - 14);
352
353 /* There is one DAC offset register per vref. Changing one
354 * channels offset will also change the offset for all other
355 * channels which share the same vref supply. */
356 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
357 return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
358 AD5360_REG_SF_OFS(ofs_index), val, 0);
359 default:
360 break;
361 }
362
363 return -EINVAL;
364 }
365
ad5360_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)366 static int ad5360_read_raw(struct iio_dev *indio_dev,
367 struct iio_chan_spec const *chan,
368 int *val,
369 int *val2,
370 long m)
371 {
372 struct ad5360_state *st = iio_priv(indio_dev);
373 unsigned int ofs_index;
374 int scale_uv;
375 int ret;
376
377 switch (m) {
378 case IIO_CHAN_INFO_RAW:
379 ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
380 chan->address);
381 if (ret < 0)
382 return ret;
383 *val = ret >> chan->scan_type.shift;
384 return IIO_VAL_INT;
385 case IIO_CHAN_INFO_SCALE:
386 scale_uv = ad5360_get_channel_vref(st, chan->channel);
387 if (scale_uv < 0)
388 return scale_uv;
389
390 /* vout = 4 * vref * dac_code */
391 *val = scale_uv * 4 / 1000;
392 *val2 = chan->scan_type.realbits;
393 return IIO_VAL_FRACTIONAL_LOG2;
394 case IIO_CHAN_INFO_CALIBBIAS:
395 ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
396 chan->address);
397 if (ret < 0)
398 return ret;
399 *val = ret;
400 return IIO_VAL_INT;
401 case IIO_CHAN_INFO_CALIBSCALE:
402 ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
403 chan->address);
404 if (ret < 0)
405 return ret;
406 *val = ret;
407 return IIO_VAL_INT;
408 case IIO_CHAN_INFO_OFFSET:
409 ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
410 ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
411 AD5360_REG_SF_OFS(ofs_index));
412 if (ret < 0)
413 return ret;
414
415 ret <<= (chan->scan_type.realbits - 14);
416 *val = -ret;
417 return IIO_VAL_INT;
418 }
419
420 return -EINVAL;
421 }
422
423 static const struct iio_info ad5360_info = {
424 .read_raw = ad5360_read_raw,
425 .write_raw = ad5360_write_raw,
426 .attrs = &ad5360_attribute_group,
427 };
428
429 static const char * const ad5360_vref_name[] = {
430 "vref0", "vref1", "vref2"
431 };
432
ad5360_alloc_channels(struct iio_dev * indio_dev)433 static int ad5360_alloc_channels(struct iio_dev *indio_dev)
434 {
435 struct ad5360_state *st = iio_priv(indio_dev);
436 struct iio_chan_spec *channels;
437 unsigned int i;
438
439 channels = kcalloc(st->chip_info->num_channels,
440 sizeof(struct iio_chan_spec), GFP_KERNEL);
441
442 if (!channels)
443 return -ENOMEM;
444
445 for (i = 0; i < st->chip_info->num_channels; ++i) {
446 channels[i] = st->chip_info->channel_template;
447 channels[i].channel = i;
448 channels[i].address = AD5360_CHAN_ADDR(i);
449 }
450
451 indio_dev->channels = channels;
452
453 return 0;
454 }
455
ad5360_probe(struct spi_device * spi)456 static int ad5360_probe(struct spi_device *spi)
457 {
458 enum ad5360_type type = spi_get_device_id(spi)->driver_data;
459 struct iio_dev *indio_dev;
460 struct ad5360_state *st;
461 unsigned int i;
462 int ret;
463
464 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
465 if (indio_dev == NULL) {
466 dev_err(&spi->dev, "Failed to allocate iio device\n");
467 return -ENOMEM;
468 }
469
470 st = iio_priv(indio_dev);
471 spi_set_drvdata(spi, indio_dev);
472
473 st->chip_info = &ad5360_chip_info_tbl[type];
474 st->spi = spi;
475
476 indio_dev->dev.parent = &spi->dev;
477 indio_dev->name = spi_get_device_id(spi)->name;
478 indio_dev->info = &ad5360_info;
479 indio_dev->modes = INDIO_DIRECT_MODE;
480 indio_dev->num_channels = st->chip_info->num_channels;
481
482 ret = ad5360_alloc_channels(indio_dev);
483 if (ret) {
484 dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
485 return ret;
486 }
487
488 for (i = 0; i < st->chip_info->num_vrefs; ++i)
489 st->vref_reg[i].supply = ad5360_vref_name[i];
490
491 ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
492 st->vref_reg);
493 if (ret) {
494 dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
495 goto error_free_channels;
496 }
497
498 ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
499 if (ret) {
500 dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
501 goto error_free_channels;
502 }
503
504 ret = iio_device_register(indio_dev);
505 if (ret) {
506 dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
507 goto error_disable_reg;
508 }
509
510 return 0;
511
512 error_disable_reg:
513 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
514 error_free_channels:
515 kfree(indio_dev->channels);
516
517 return ret;
518 }
519
ad5360_remove(struct spi_device * spi)520 static int ad5360_remove(struct spi_device *spi)
521 {
522 struct iio_dev *indio_dev = spi_get_drvdata(spi);
523 struct ad5360_state *st = iio_priv(indio_dev);
524
525 iio_device_unregister(indio_dev);
526
527 kfree(indio_dev->channels);
528
529 regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
530
531 return 0;
532 }
533
534 static const struct spi_device_id ad5360_ids[] = {
535 { "ad5360", ID_AD5360 },
536 { "ad5361", ID_AD5361 },
537 { "ad5362", ID_AD5362 },
538 { "ad5363", ID_AD5363 },
539 { "ad5370", ID_AD5370 },
540 { "ad5371", ID_AD5371 },
541 { "ad5372", ID_AD5372 },
542 { "ad5373", ID_AD5373 },
543 {}
544 };
545 MODULE_DEVICE_TABLE(spi, ad5360_ids);
546
547 static struct spi_driver ad5360_driver = {
548 .driver = {
549 .name = "ad5360",
550 },
551 .probe = ad5360_probe,
552 .remove = ad5360_remove,
553 .id_table = ad5360_ids,
554 };
555 module_spi_driver(ad5360_driver);
556
557 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
558 MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
559 MODULE_LICENSE("GPL v2");
560
