1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * rcar_du_regs.h -- R-Car Display Unit Registers Definitions 4 * 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 6 * 7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8 */ 9 10 #ifndef __RCAR_DU_REGS_H__ 11 #define __RCAR_DU_REGS_H__ 12 13 #define DU0_REG_OFFSET 0x00000 14 #define DU1_REG_OFFSET 0x30000 15 #define DU2_REG_OFFSET 0x40000 16 #define DU3_REG_OFFSET 0x70000 17 18 /* ----------------------------------------------------------------------------- 19 * Display Control Registers 20 */ 21 22 #define DSYSR 0x00000 /* display 1 */ 23 #define DSYSR_ILTS (1 << 29) 24 #define DSYSR_DSEC (1 << 20) 25 #define DSYSR_IUPD (1 << 16) 26 #define DSYSR_DRES (1 << 9) 27 #define DSYSR_DEN (1 << 8) 28 #define DSYSR_TVM_MASTER (0 << 6) 29 #define DSYSR_TVM_SWITCH (1 << 6) 30 #define DSYSR_TVM_TVSYNC (2 << 6) 31 #define DSYSR_TVM_MASK (3 << 6) 32 #define DSYSR_SCM_INT_NONE (0 << 4) 33 #define DSYSR_SCM_INT_SYNC (2 << 4) 34 #define DSYSR_SCM_INT_VIDEO (3 << 4) 35 #define DSYSR_SCM_MASK (3 << 4) 36 37 #define DSMR 0x00004 38 #define DSMR_VSPM (1 << 28) 39 #define DSMR_ODPM (1 << 27) 40 #define DSMR_DIPM_DISP (0 << 25) 41 #define DSMR_DIPM_CSYNC (1 << 25) 42 #define DSMR_DIPM_DE (3 << 25) 43 #define DSMR_DIPM_MASK (3 << 25) 44 #define DSMR_CSPM (1 << 24) 45 #define DSMR_DIL (1 << 19) 46 #define DSMR_VSL (1 << 18) 47 #define DSMR_HSL (1 << 17) 48 #define DSMR_DDIS (1 << 16) 49 #define DSMR_CDEL (1 << 15) 50 #define DSMR_CDEM_CDE (0 << 13) 51 #define DSMR_CDEM_LOW (2 << 13) 52 #define DSMR_CDEM_HIGH (3 << 13) 53 #define DSMR_CDEM_MASK (3 << 13) 54 #define DSMR_CDED (1 << 12) 55 #define DSMR_ODEV (1 << 8) 56 #define DSMR_CSY_VH_OR (0 << 6) 57 #define DSMR_CSY_333 (2 << 6) 58 #define DSMR_CSY_222 (3 << 6) 59 #define DSMR_CSY_MASK (3 << 6) 60 61 #define DSSR 0x00008 62 #define DSSR_VC1FB_DSA0 (0 << 30) 63 #define DSSR_VC1FB_DSA1 (1 << 30) 64 #define DSSR_VC1FB_DSA2 (2 << 30) 65 #define DSSR_VC1FB_INIT (3 << 30) 66 #define DSSR_VC1FB_MASK (3 << 30) 67 #define DSSR_VC0FB_DSA0 (0 << 28) 68 #define DSSR_VC0FB_DSA1 (1 << 28) 69 #define DSSR_VC0FB_DSA2 (2 << 28) 70 #define DSSR_VC0FB_INIT (3 << 28) 71 #define DSSR_VC0FB_MASK (3 << 28) 72 #define DSSR_DFB(n) (1 << ((n)+15)) 73 #define DSSR_TVR (1 << 15) 74 #define DSSR_FRM (1 << 14) 75 #define DSSR_VBK (1 << 11) 76 #define DSSR_RINT (1 << 9) 77 #define DSSR_HBK (1 << 8) 78 #define DSSR_ADC(n) (1 << ((n)-1)) 79 80 #define DSRCR 0x0000c 81 #define DSRCR_TVCL (1 << 15) 82 #define DSRCR_FRCL (1 << 14) 83 #define DSRCR_VBCL (1 << 11) 84 #define DSRCR_RICL (1 << 9) 85 #define DSRCR_HBCL (1 << 8) 86 #define DSRCR_ADCL(n) (1 << ((n)-1)) 87 #define DSRCR_MASK 0x0000cbff 88 89 #define DIER 0x00010 90 #define DIER_TVE (1 << 15) 91 #define DIER_FRE (1 << 14) 92 #define DIER_VBE (1 << 11) 93 #define DIER_RIE (1 << 9) 94 #define DIER_HBE (1 << 8) 95 #define DIER_ADCE(n) (1 << ((n)-1)) 96 97 #define CPCR 0x00014 98 #define CPCR_CP4CE (1 << 19) 99 #define CPCR_CP3CE (1 << 18) 100 #define CPCR_CP2CE (1 << 17) 101 #define CPCR_CP1CE (1 << 16) 102 103 #define DPPR 0x00018 104 #define DPPR_DPE(n) (1 << ((n)*4-1)) 105 #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) 106 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) 107 #define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */ 108 #define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1)) 109 #define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2)) 110 #define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ 111 112 #define DEFR 0x00020 113 #define DEFR_CODE (0x7773 << 16) 114 #define DEFR_EXSL (1 << 12) 115 #define DEFR_EXVL (1 << 11) 116 #define DEFR_EXUP (1 << 5) 117 #define DEFR_VCUP (1 << 4) 118 #define DEFR_DEFE (1 << 0) 119 120 #define DAPCR 0x00024 121 #define DAPCR_CODE (0x7773 << 16) 122 #define DAPCR_AP2E (1 << 4) 123 #define DAPCR_AP1E (1 << 0) 124 125 #define DCPCR 0x00028 126 #define DCPCR_CODE (0x7773 << 16) 127 #define DCPCR_CA2B (1 << 13) 128 #define DCPCR_CD2F (1 << 12) 129 #define DCPCR_DC2E (1 << 8) 130 #define DCPCR_CAB (1 << 5) 131 #define DCPCR_CDF (1 << 4) 132 #define DCPCR_DCE (1 << 0) 133 134 #define DEFR2 0x00034 135 #define DEFR2_CODE (0x7775 << 16) 136 #define DEFR2_DEFE2G (1 << 0) 137 138 #define DEFR3 0x00038 139 #define DEFR3_CODE (0x7776 << 16) 140 #define DEFR3_EVDA (1 << 14) 141 #define DEFR3_EVDM_1 (1 << 12) 142 #define DEFR3_EVDM_2 (2 << 12) 143 #define DEFR3_EVDM_3 (3 << 12) 144 #define DEFR3_VMSM2_EMA (1 << 6) 145 #define DEFR3_VMSM1_ENA (1 << 4) 146 #define DEFR3_DEFE3 (1 << 0) 147 148 #define DEFR4 0x0003c 149 #define DEFR4_CODE (0x7777 << 16) 150 #define DEFR4_LRUO (1 << 5) 151 #define DEFR4_SPCE (1 << 4) 152 153 #define DVCSR 0x000d0 154 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) 155 #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) 156 #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) 157 #define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16)) 158 #define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16)) 159 #define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2)) 160 #define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2)) 161 #define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2)) 162 #define DVCSR_VCnFB_INIT(n) (3 << ((n)*2)) 163 #define DVCSR_VCnFB_MASK(n) (3 << ((n)*2)) 164 165 #define DEFR5 0x000e0 166 #define DEFR5_CODE (0x66 << 24) 167 #define DEFR5_YCRGB2_DIS (0 << 14) 168 #define DEFR5_YCRGB2_PRI1 (1 << 14) 169 #define DEFR5_YCRGB2_PRI2 (2 << 14) 170 #define DEFR5_YCRGB2_PRI3 (3 << 14) 171 #define DEFR5_YCRGB2_MASK (3 << 14) 172 #define DEFR5_YCRGB1_DIS (0 << 12) 173 #define DEFR5_YCRGB1_PRI1 (1 << 12) 174 #define DEFR5_YCRGB1_PRI2 (2 << 12) 175 #define DEFR5_YCRGB1_PRI3 (3 << 12) 176 #define DEFR5_YCRGB1_MASK (3 << 12) 177 #define DEFR5_DEFE5 (1 << 0) 178 179 #define DDLTR 0x000e4 180 #define DDLTR_CODE (0x7766 << 16) 181 #define DDLTR_DLAR2 (1 << 6) 182 #define DDLTR_DLAY2 (1 << 5) 183 #define DDLTR_DLAY1 (1 << 1) 184 185 #define DEFR6 0x000e8 186 #define DEFR6_CODE (0x7778 << 16) 187 #define DEFR6_ODPM12_DSMR (0 << 10) 188 #define DEFR6_ODPM12_DISP (2 << 10) 189 #define DEFR6_ODPM12_CDE (3 << 10) 190 #define DEFR6_ODPM12_MASK (3 << 10) 191 #define DEFR6_ODPM02_DSMR (0 << 8) 192 #define DEFR6_ODPM02_DISP (2 << 8) 193 #define DEFR6_ODPM02_CDE (3 << 8) 194 #define DEFR6_ODPM02_MASK (3 << 8) 195 #define DEFR6_TCNE1 (1 << 6) 196 #define DEFR6_TCNE0 (1 << 4) 197 #define DEFR6_MLOS1 (1 << 2) 198 #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) 199 200 /* ----------------------------------------------------------------------------- 201 * R8A7790-only Control Registers 202 */ 203 204 #define DD1SSR 0x20008 205 #define DD1SSR_TVR (1 << 15) 206 #define DD1SSR_FRM (1 << 14) 207 #define DD1SSR_BUF (1 << 12) 208 #define DD1SSR_VBK (1 << 11) 209 #define DD1SSR_RINT (1 << 9) 210 #define DD1SSR_HBK (1 << 8) 211 #define DD1SSR_ADC(n) (1 << ((n)-1)) 212 213 #define DD1SRCR 0x2000c 214 #define DD1SRCR_TVR (1 << 15) 215 #define DD1SRCR_FRM (1 << 14) 216 #define DD1SRCR_BUF (1 << 12) 217 #define DD1SRCR_VBK (1 << 11) 218 #define DD1SRCR_RINT (1 << 9) 219 #define DD1SRCR_HBK (1 << 8) 220 #define DD1SRCR_ADC(n) (1 << ((n)-1)) 221 222 #define DD1IER 0x20010 223 #define DD1IER_TVR (1 << 15) 224 #define DD1IER_FRM (1 << 14) 225 #define DD1IER_BUF (1 << 12) 226 #define DD1IER_VBK (1 << 11) 227 #define DD1IER_RINT (1 << 9) 228 #define DD1IER_HBK (1 << 8) 229 #define DD1IER_ADC(n) (1 << ((n)-1)) 230 231 #define DEFR8 0x20020 232 #define DEFR8_CODE (0x7790 << 16) 233 #define DEFR8_VSCS (1 << 6) 234 #define DEFR8_DRGBS_DU(n) ((n) << 4) 235 #define DEFR8_DRGBS_MASK (3 << 4) 236 #define DEFR8_DEFE8 (1 << 0) 237 238 #define DOFLR 0x20024 239 #define DOFLR_CODE (0x7790 << 16) 240 #define DOFLR_HSYCFL1 (1 << 13) 241 #define DOFLR_VSYCFL1 (1 << 12) 242 #define DOFLR_ODDFL1 (1 << 11) 243 #define DOFLR_DISPFL1 (1 << 10) 244 #define DOFLR_CDEFL1 (1 << 9) 245 #define DOFLR_RGBFL1 (1 << 8) 246 #define DOFLR_HSYCFL0 (1 << 5) 247 #define DOFLR_VSYCFL0 (1 << 4) 248 #define DOFLR_ODDFL0 (1 << 3) 249 #define DOFLR_DISPFL0 (1 << 2) 250 #define DOFLR_CDEFL0 (1 << 1) 251 #define DOFLR_RGBFL0 (1 << 0) 252 253 #define DIDSR 0x20028 254 #define DIDSR_CODE (0x7790 << 16) 255 #define DIDSR_LCDS_DCLKIN(n) (0 << (8 + (n) * 2)) 256 #define DIDSR_LCDS_LVDS0(n) (2 << (8 + (n) * 2)) 257 #define DIDSR_LCDS_LVDS1(n) (3 << (8 + (n) * 2)) 258 #define DIDSR_LCDS_MASK(n) (3 << (8 + (n) * 2)) 259 #define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2)) 260 #define DIDSR_PDCS_MASK(n) (3 << ((n) * 2)) 261 262 #define DEFR10 0x20038 263 #define DEFR10_CODE (0x7795 << 16) 264 #define DEFR10_VSPF1_RGB (0 << 14) 265 #define DEFR10_VSPF1_YC (1 << 14) 266 #define DEFR10_DOCF1_RGB (0 << 12) 267 #define DEFR10_DOCF1_YC (1 << 12) 268 #define DEFR10_YCDF0_YCBCR444 (0 << 11) 269 #define DEFR10_YCDF0_YCBCR422 (1 << 11) 270 #define DEFR10_VSPF0_RGB (0 << 10) 271 #define DEFR10_VSPF0_YC (1 << 10) 272 #define DEFR10_DOCF0_RGB (0 << 8) 273 #define DEFR10_DOCF0_YC (1 << 8) 274 #define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */ 275 #define DEFR10_DEFE10 (1 << 0) 276 277 #define DPLLCR 0x20044 278 #define DPLLCR_CODE (0x95 << 24) 279 #define DPLLCR_PLCS1 (1 << 23) 280 /* 281 * PLCS0 is bit 21, but H3 ES1.x requires bit 20 to be set as well. As bit 20 282 * isn't implemented by other SoC in the Gen3 family it can safely be set 283 * unconditionally. 284 */ 285 #define DPLLCR_PLCS0 (3 << 20) 286 #define DPLLCR_CLKE (1 << 18) 287 #define DPLLCR_FDPLL(n) ((n) << 12) 288 #define DPLLCR_N(n) ((n) << 5) 289 #define DPLLCR_M(n) ((n) << 3) 290 #define DPLLCR_STBY (1 << 2) 291 #define DPLLCR_INCS_DOTCLKIN0 (0 << 0) 292 #define DPLLCR_INCS_DOTCLKIN1 (1 << 1) 293 294 #define DPLLC2R 0x20048 295 #define DPLLC2R_CODE (0x95 << 24) 296 #define DPLLC2R_SELC (1 << 12) 297 #define DPLLC2R_M(n) ((n) << 8) 298 #define DPLLC2R_FDPLL(n) ((n) << 0) 299 300 /* ----------------------------------------------------------------------------- 301 * Display Timing Generation Registers 302 */ 303 304 #define HDSR 0x00040 305 #define HDER 0x00044 306 #define VDSR 0x00048 307 #define VDER 0x0004c 308 #define HCR 0x00050 309 #define HSWR 0x00054 310 #define VCR 0x00058 311 #define VSPR 0x0005c 312 #define EQWR 0x00060 313 #define SPWR 0x00064 314 #define CLAMPSR 0x00070 315 #define CLAMPWR 0x00074 316 #define DESR 0x00078 317 #define DEWR 0x0007c 318 319 /* ----------------------------------------------------------------------------- 320 * Display Attribute Registers 321 */ 322 323 #define CP1TR 0x00080 324 #define CP2TR 0x00084 325 #define CP3TR 0x00088 326 #define CP4TR 0x0008c 327 328 #define DOOR 0x00090 329 #define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 330 #define CDER 0x00094 331 #define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 332 #define BPOR 0x00098 333 #define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 334 335 #define RINTOFSR 0x0009c 336 337 #define DSHPR 0x000c8 338 #define DSHPR_CODE (0x7776 << 16) 339 #define DSHPR_PRIH (0xa << 4) 340 #define DSHPR_PRIL_BPP16 (0x8 << 0) 341 #define DSHPR_PRIL_BPP32 (0x9 << 0) 342 343 /* ----------------------------------------------------------------------------- 344 * Display Plane Registers 345 */ 346 347 #define PLANE_OFF 0x00100 348 349 #define PnMR 0x00100 /* plane 1 */ 350 #define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */ 351 #define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */ 352 #define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */ 353 #define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */ 354 #define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */ 355 #define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */ 356 #define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */ 357 #define PnMR_WAE (1 << 16) /* Wrap around Enable */ 358 #define PnMR_SPIM_TP (0 << 12) /* Transparent Color */ 359 #define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */ 360 #define PnMR_SPIM_EOR (2 << 12) /* EOR */ 361 #define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */ 362 #define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */ 363 #define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */ 364 #define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */ 365 #define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */ 366 #define PnMR_DC (1 << 7) /* Display Area Change */ 367 #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 368 #define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */ 369 #define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 370 #define PnMR_BM_VC (3 << 4) /* Video Capture Mode */ 371 #define PnMR_DDDF_8BPP (0 << 0) /* 8bit */ 372 #define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */ 373 #define PnMR_DDDF_ARGB (2 << 0) /* ARGB */ 374 #define PnMR_DDDF_YC (3 << 0) /* YC */ 375 #define PnMR_DDDF_MASK (3 << 0) 376 377 #define PnMWR 0x00104 378 379 #define PnALPHAR 0x00108 380 #define PnALPHAR_ABIT_1 (0 << 12) 381 #define PnALPHAR_ABIT_0 (1 << 12) 382 #define PnALPHAR_ABIT_X (2 << 12) 383 384 #define PnDSXR 0x00110 385 #define PnDSYR 0x00114 386 #define PnDPXR 0x00118 387 #define PnDPYR 0x0011c 388 389 #define PnDSA0R 0x00120 390 #define PnDSA1R 0x00124 391 #define PnDSA2R 0x00128 392 #define PnDSA_MASK 0xfffffff0 393 394 #define PnSPXR 0x00130 395 #define PnSPYR 0x00134 396 #define PnWASPR 0x00138 397 #define PnWAMWR 0x0013c 398 399 #define PnBTR 0x00140 400 401 #define PnTC1R 0x00144 402 #define PnTC2R 0x00148 403 #define PnTC3R 0x0014c 404 #define PnTC3R_CODE (0x66 << 24) 405 406 #define PnMLR 0x00150 407 408 #define PnSWAPR 0x00180 409 #define PnSWAPR_DIGN (1 << 4) 410 #define PnSWAPR_SPQW (1 << 3) 411 #define PnSWAPR_SPLW (1 << 2) 412 #define PnSWAPR_SPWD (1 << 1) 413 #define PnSWAPR_SPBY (1 << 0) 414 415 #define PnDDCR 0x00184 416 #define PnDDCR_CODE (0x7775 << 16) 417 #define PnDDCR_LRGB1 (1 << 11) 418 #define PnDDCR_LRGB0 (1 << 10) 419 420 #define PnDDCR2 0x00188 421 #define PnDDCR2_CODE (0x7776 << 16) 422 #define PnDDCR2_NV21 (1 << 5) 423 #define PnDDCR2_Y420 (1 << 4) 424 #define PnDDCR2_DIVU (1 << 1) 425 #define PnDDCR2_DIVY (1 << 0) 426 427 #define PnDDCR4 0x00190 428 #define PnDDCR4_CODE (0x7766 << 16) 429 #define PnDDCR4_VSPS (1 << 13) 430 #define PnDDCR4_SDFS_RGB (0 << 4) 431 #define PnDDCR4_SDFS_YC (5 << 4) 432 #define PnDDCR4_SDFS_MASK (7 << 4) 433 #define PnDDCR4_EDF_NONE (0 << 0) 434 #define PnDDCR4_EDF_ARGB8888 (1 << 0) 435 #define PnDDCR4_EDF_RGB888 (2 << 0) 436 #define PnDDCR4_EDF_RGB666 (3 << 0) 437 #define PnDDCR4_EDF_MASK (7 << 0) 438 439 #define APnMR 0x0a100 440 #define APnMR_WAE (1 << 16) /* Wrap around Enable */ 441 #define APnMR_DC (1 << 7) /* Display Area Change */ 442 #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 443 #define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 444 445 #define APnMWR 0x0a104 446 447 #define APnDSXR 0x0a110 448 #define APnDSYR 0x0a114 449 #define APnDPXR 0x0a118 450 #define APnDPYR 0x0a11c 451 452 #define APnDSA0R 0x0a120 453 #define APnDSA1R 0x0a124 454 #define APnDSA2R 0x0a128 455 456 #define APnSPXR 0x0a130 457 #define APnSPYR 0x0a134 458 #define APnWASPR 0x0a138 459 #define APnWAMWR 0x0a13c 460 461 #define APnBTR 0x0a140 462 463 #define APnMLR 0x0a150 464 #define APnSWAPR 0x0a180 465 466 /* ----------------------------------------------------------------------------- 467 * Display Capture Registers 468 */ 469 470 #define DCMR 0x0c100 471 #define DCMWR 0x0c104 472 #define DCSAR 0x0c120 473 #define DCMLR 0x0c150 474 475 /* ----------------------------------------------------------------------------- 476 * Color Palette Registers 477 */ 478 479 #define CP1_000R 0x01000 480 #define CP1_255R 0x013fc 481 #define CP2_000R 0x02000 482 #define CP2_255R 0x023fc 483 #define CP3_000R 0x03000 484 #define CP3_255R 0x033fc 485 #define CP4_000R 0x04000 486 #define CP4_255R 0x043fc 487 488 /* ----------------------------------------------------------------------------- 489 * External Synchronization Control Registers 490 */ 491 492 #define ESCR02 0x10000 493 #define ESCR13 0x01000 494 #define ESCR_DCLKOINV (1 << 25) 495 #define ESCR_DCLKSEL_DCLKIN (0 << 20) 496 #define ESCR_DCLKSEL_CLKS (1 << 20) 497 #define ESCR_DCLKSEL_MASK (1 << 20) 498 #define ESCR_DCLKDIS (1 << 16) 499 #define ESCR_SYNCSEL_OFF (0 << 8) 500 #define ESCR_SYNCSEL_EXVSYNC (2 << 8) 501 #define ESCR_SYNCSEL_EXHSYNC (3 << 8) 502 #define ESCR_FRQSEL_MASK (0x3f << 0) 503 504 #define OTAR02 0x10004 505 #define OTAR13 0x01004 506 507 /* ----------------------------------------------------------------------------- 508 * Dual Display Output Control Registers 509 */ 510 511 #define DORCR 0x11000 512 #define DORCR_PG2T (1 << 30) 513 #define DORCR_DK2S (1 << 28) 514 #define DORCR_PG2D_DS1 (0 << 24) 515 #define DORCR_PG2D_DS2 (1 << 24) 516 #define DORCR_PG2D_FIX0 (2 << 24) 517 #define DORCR_PG2D_DOOR (3 << 24) 518 #define DORCR_PG2D_MASK (3 << 24) 519 #define DORCR_DR1D (1 << 21) 520 #define DORCR_PG1D_DS1 (0 << 16) 521 #define DORCR_PG1D_DS2 (1 << 16) 522 #define DORCR_PG1D_FIX0 (2 << 16) 523 #define DORCR_PG1D_DOOR (3 << 16) 524 #define DORCR_PG1D_MASK (3 << 16) 525 #define DORCR_RGPV (1 << 4) 526 #define DORCR_DPRS (1 << 0) 527 528 #define DPTSR 0x11004 529 #define DPTSR_PnDK(n) (1 << ((n) + 16)) 530 #define DPTSR_PnTS(n) (1 << (n)) 531 532 #define DAPTSR 0x11008 533 #define DAPTSR_APnDK(n) (1 << ((n) + 16)) 534 #define DAPTSR_APnTS(n) (1 << (n)) 535 536 #define DS1PR 0x11020 537 #define DS2PR 0x11024 538 539 /* ----------------------------------------------------------------------------- 540 * YC-RGB Conversion Coefficient Registers 541 */ 542 543 #define YNCR 0x11080 544 #define YNOR 0x11084 545 #define CRNOR 0x11088 546 #define CBNOR 0x1108c 547 #define RCRCR 0x11090 548 #define GCRCR 0x11094 549 #define GCBCR 0x11098 550 #define BCBCR 0x1109c 551 552 #endif /* __RCAR_DU_REGS_H__ */ 553
