1 // SPDX-License-Identifier: MIT
2 #include "nv20.h"
3 #include "regs.h"
4
5 #include <core/gpuobj.h>
6 #include <engine/fifo.h>
7 #include <engine/fifo/chan.h>
8
9 /*******************************************************************************
10 * PGRAPH context
11 ******************************************************************************/
12
13 static const struct nvkm_object_func
14 nv34_gr_chan = {
15 .dtor = nv20_gr_chan_dtor,
16 .init = nv20_gr_chan_init,
17 .fini = nv20_gr_chan_fini,
18 };
19
20 static int
nv34_gr_chan_new(struct nvkm_gr * base,struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)21 nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
22 const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
23 {
24 struct nv20_gr *gr = nv20_gr(base);
25 struct nv20_gr_chan *chan;
26 int ret, i;
27
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
29 return -ENOMEM;
30 nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object);
31 chan->gr = gr;
32 chan->chid = fifoch->chid;
33 *pobject = &chan->object;
34
35 ret = nvkm_memory_new(gr->base.engine.subdev.device,
36 NVKM_MEM_TARGET_INST, 0x46dc, 16, true,
37 &chan->inst);
38 if (ret)
39 return ret;
40
41 nvkm_kmap(chan->inst);
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101);
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111);
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060);
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080);
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001);
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000);
50 nvkm_wo32(chan->inst, 0x0480, 0xffff0000);
51 for (i = 0x04d4; i < 0x04dc; i += 4)
52 nvkm_wo32(chan->inst, i, 0x0fff0000);
53 nvkm_wo32(chan->inst, 0x04e0, 0x00011100);
54 for (i = 0x04fc; i < 0x053c; i += 4)
55 nvkm_wo32(chan->inst, i, 0x07ff0000);
56 nvkm_wo32(chan->inst, 0x0544, 0x4b7fffff);
57 nvkm_wo32(chan->inst, 0x057c, 0x00000080);
58 nvkm_wo32(chan->inst, 0x0580, 0x30201000);
59 nvkm_wo32(chan->inst, 0x0584, 0x70605040);
60 nvkm_wo32(chan->inst, 0x0588, 0xb8a89888);
61 nvkm_wo32(chan->inst, 0x058c, 0xf8e8d8c8);
62 nvkm_wo32(chan->inst, 0x05a0, 0xb0000000);
63 for (i = 0x05f0; i < 0x0630; i += 4)
64 nvkm_wo32(chan->inst, i, 0x00010588);
65 for (i = 0x0630; i < 0x0670; i += 4)
66 nvkm_wo32(chan->inst, i, 0x00030303);
67 for (i = 0x06b0; i < 0x06f0; i += 4)
68 nvkm_wo32(chan->inst, i, 0x0008aae4);
69 for (i = 0x06f0; i < 0x0730; i += 4)
70 nvkm_wo32(chan->inst, i, 0x01012000);
71 for (i = 0x0730; i < 0x0770; i += 4)
72 nvkm_wo32(chan->inst, i, 0x00080008);
73 nvkm_wo32(chan->inst, 0x0850, 0x00040000);
74 nvkm_wo32(chan->inst, 0x0854, 0x00010000);
75 for (i = 0x0858; i < 0x0868; i += 4)
76 nvkm_wo32(chan->inst, i, 0x00040004);
77 for (i = 0x15ac; i <= 0x271c ; i += 16) {
78 nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
79 nvkm_wo32(chan->inst, i + 4, 0x0436086c);
80 nvkm_wo32(chan->inst, i + 8, 0x000c001b);
81 }
82 for (i = 0x274c; i < 0x275c; i += 4)
83 nvkm_wo32(chan->inst, i, 0x0000ffff);
84 nvkm_wo32(chan->inst, 0x2ae0, 0x3f800000);
85 nvkm_wo32(chan->inst, 0x2e9c, 0x3f800000);
86 nvkm_wo32(chan->inst, 0x2eb0, 0x3f800000);
87 nvkm_wo32(chan->inst, 0x2edc, 0x40000000);
88 nvkm_wo32(chan->inst, 0x2ee0, 0x3f800000);
89 nvkm_wo32(chan->inst, 0x2ee4, 0x3f000000);
90 nvkm_wo32(chan->inst, 0x2eec, 0x40000000);
91 nvkm_wo32(chan->inst, 0x2ef0, 0x3f800000);
92 nvkm_wo32(chan->inst, 0x2ef8, 0xbf800000);
93 nvkm_wo32(chan->inst, 0x2f00, 0xbf800000);
94 nvkm_done(chan->inst);
95 return 0;
96 }
97
98 /*******************************************************************************
99 * PGRAPH engine/subdev functions
100 ******************************************************************************/
101
102 static const struct nvkm_gr_func
103 nv34_gr = {
104 .dtor = nv20_gr_dtor,
105 .oneinit = nv20_gr_oneinit,
106 .init = nv30_gr_init,
107 .intr = nv20_gr_intr,
108 .tile = nv20_gr_tile,
109 .chan_new = nv34_gr_chan_new,
110 .sclass = {
111 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
112 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
113 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
114 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
115 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
116 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */
117 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
118 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
119 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
120 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
121 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
122 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
123 { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
124 { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
125 { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
126 { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
127 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
128 { -1, -1, 0x0697, &nv04_gr_object }, /* rankine */
129 {}
130 }
131 };
132
133 int
nv34_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)134 nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
135 {
136 return nv20_gr_new_(&nv34_gr, device, index, pgr);
137 }
138
