1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU12_DRIVER_IF_H 25 #define SMU12_DRIVER_IF_H 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 #define SMU12_DRIVER_IF_VERSION 10 31 32 typedef struct { 33 int32_t value; 34 uint32_t numFractionalBits; 35 } FloatInIntFormat_t; 36 37 typedef enum { 38 DSPCLK_DCFCLK = 0, 39 DSPCLK_DISPCLK, 40 DSPCLK_PIXCLK, 41 DSPCLK_PHYCLK, 42 DSPCLK_COUNT, 43 } DSPCLK_e; 44 45 typedef struct { 46 uint16_t Freq; // in MHz 47 uint16_t Vid; // min voltage in SVI2 VID 48 } DisplayClockTable_t; 49 50 typedef struct { 51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 53 uint16_t MinMclk; 54 uint16_t MaxMclk; 55 56 uint8_t WmSetting; 57 uint8_t WmType; // Used for normal pstate change or memory retraining 58 uint8_t Padding[2]; 59 } WatermarkRowGeneric_t; 60 61 #define NUM_WM_RANGES 4 62 #define WM_PSTATE_CHG 0 63 #define WM_RETRAINING 1 64 65 typedef enum { 66 WM_SOCCLK = 0, 67 WM_DCFCLK, 68 WM_COUNT, 69 } WM_CLOCK_e; 70 71 typedef struct { 72 // Watermarks 73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 74 75 uint32_t MmHubPadding[7]; // SMU internal use 76 } Watermarks_t; 77 78 typedef enum { 79 CUSTOM_DPM_SETTING_GFXCLK, 80 CUSTOM_DPM_SETTING_CCLK, 81 CUSTOM_DPM_SETTING_FCLK_CCX, 82 CUSTOM_DPM_SETTING_FCLK_GFX, 83 CUSTOM_DPM_SETTING_FCLK_STALLS, 84 CUSTOM_DPM_SETTING_LCLK, 85 CUSTOM_DPM_SETTING_COUNT, 86 } CUSTOM_DPM_SETTING_e; 87 88 typedef struct { 89 uint8_t ActiveHystLimit; 90 uint8_t IdleHystLimit; 91 uint8_t FPS; 92 uint8_t MinActiveFreqType; 93 FloatInIntFormat_t MinActiveFreq; 94 FloatInIntFormat_t PD_Data_limit; 95 FloatInIntFormat_t PD_Data_time_constant; 96 FloatInIntFormat_t PD_Data_error_coeff; 97 FloatInIntFormat_t PD_Data_error_rate_coeff; 98 } DpmActivityMonitorCoeffExt_t; 99 100 typedef struct { 101 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; 102 } CustomDpmSettings_t; 103 104 105 #define NUM_DCFCLK_DPM_LEVELS 8 106 #define NUM_SOCCLK_DPM_LEVELS 8 107 #define NUM_FCLK_DPM_LEVELS 4 108 #define NUM_MEMCLK_DPM_LEVELS 4 109 #define NUM_VCN_DPM_LEVELS 8 110 111 typedef struct { 112 uint32_t Freq; // In MHz 113 uint32_t Vol; // Millivolts with 2 fractional bits 114 } DpmClock_t; 115 116 typedef struct { 117 DpmClock_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 118 DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 119 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS]; 120 DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS]; 121 DpmClock_t VClocks[NUM_VCN_DPM_LEVELS]; 122 DpmClock_t DClocks[NUM_VCN_DPM_LEVELS]; 123 124 uint8_t NumDcfClkDpmEnabled; 125 uint8_t NumSocClkDpmEnabled; 126 uint8_t NumFClkDpmEnabled; 127 uint8_t NumMemClkDpmEnabled; 128 uint8_t NumVClkDpmEnabled; 129 uint8_t NumDClkDpmEnabled; 130 uint8_t spare[2]; 131 } DpmClocks_t; 132 133 134 typedef enum { 135 CLOCK_SMNCLK = 0, 136 CLOCK_SOCCLK, 137 CLOCK_MP0CLK, 138 CLOCK_MP1CLK, 139 CLOCK_MP2CLK, 140 CLOCK_VCLK, 141 CLOCK_LCLK, 142 CLOCK_DCLK, 143 CLOCK_ACLK, 144 CLOCK_ISPCLK, 145 CLOCK_SHUBCLK, 146 CLOCK_DISPCLK, 147 CLOCK_DPPCLK, 148 CLOCK_DPREFCLK, 149 CLOCK_DCFCLK, 150 CLOCK_FCLK, 151 CLOCK_UMCCLK, 152 CLOCK_GFXCLK, 153 CLOCK_COUNT, 154 } CLOCK_IDs_e; 155 156 // Throttler Status Bitmask 157 #define THROTTLER_STATUS_BIT_SPL 0 158 #define THROTTLER_STATUS_BIT_FPPT 1 159 #define THROTTLER_STATUS_BIT_SPPT 2 160 #define THROTTLER_STATUS_BIT_SPPT_APU 3 161 #define THROTTLER_STATUS_BIT_THM_CORE 4 162 #define THROTTLER_STATUS_BIT_THM_GFX 5 163 #define THROTTLER_STATUS_BIT_THM_SOC 6 164 #define THROTTLER_STATUS_BIT_TDC_VDD 7 165 #define THROTTLER_STATUS_BIT_TDC_SOC 8 166 167 typedef struct { 168 uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz] 169 170 uint16_t AverageGfxclkFrequency; //[MHz] 171 uint16_t AverageSocclkFrequency; //[MHz] 172 uint16_t AverageVclkFrequency; //[MHz] 173 uint16_t AverageFclkFrequency; //[MHz] 174 175 uint16_t AverageGfxActivity; //[centi] 176 uint16_t AverageUvdActivity; //[centi] 177 178 uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC 179 uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC 180 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC 181 182 uint16_t FanPwm; //[milli] 183 uint16_t CurrentSocketPower; //[mW] 184 185 uint16_t CoreFrequency[8]; //[MHz] 186 uint16_t CorePower[8]; //[mW] 187 uint16_t CoreTemperature[8]; //[centi-Celsius] 188 uint16_t L3Frequency[2]; //[MHz] 189 uint16_t L3Temperature[2]; //[centi-Celsius] 190 191 uint16_t GfxTemperature; //[centi-Celsius] 192 uint16_t SocTemperature; //[centi-Celsius] 193 uint16_t ThrottlerStatus; 194 uint16_t spare; 195 } SmuMetrics_t; 196 197 198 // Workload bits 199 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 200 #define WORKLOAD_PPLIB_VIDEO_BIT 2 201 #define WORKLOAD_PPLIB_VR_BIT 3 202 #define WORKLOAD_PPLIB_COMPUTE_BIT 4 203 #define WORKLOAD_PPLIB_CUSTOM_BIT 5 204 #define WORKLOAD_PPLIB_COUNT 6 205 206 #define TABLE_BIOS_IF 0 // Called by BIOS 207 #define TABLE_WATERMARKS 1 // Called by Driver 208 #define TABLE_CUSTOM_DPM 2 // Called by Driver 209 #define TABLE_SPARE1 3 210 #define TABLE_DPMCLOCKS 4 // Called by Driver 211 #define TABLE_MOMENTARY_PM 5 // Called by Tools 212 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log 213 #define TABLE_SMU_METRICS 7 // Called by Driver 214 #define TABLE_COUNT 8 215 216 217 #endif 218
