1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU11_DRIVER_IF_ARCTURUS_H 25 #define SMU11_DRIVER_IF_ARCTURUS_H 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 //#define SMU11_DRIVER_IF_VERSION 0x09 31 32 #define PPTABLE_ARCTURUS_SMU_VERSION 4 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_VCLK_DPM_LEVELS 8 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_MP0CLK_DPM_LEVELS 2 38 #define NUM_SOCCLK_DPM_LEVELS 8 39 #define NUM_UCLK_DPM_LEVELS 4 40 #define NUM_FCLK_DPM_LEVELS 8 41 #define NUM_XGMI_LEVELS 2 42 #define NUM_XGMI_PSTATE_LEVELS 4 43 44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1) 52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1) 53 54 // Feature Control Defines 55 // DPM 56 #define FEATURE_DPM_PREFETCHER_BIT 0 57 #define FEATURE_DPM_GFXCLK_BIT 1 58 #define FEATURE_DPM_UCLK_BIT 2 59 #define FEATURE_DPM_SOCCLK_BIT 3 60 #define FEATURE_DPM_FCLK_BIT 4 61 #define FEATURE_DPM_MP0CLK_BIT 5 62 #define FEATURE_DPM_XGMI_BIT 6 63 // Idle 64 #define FEATURE_DS_GFXCLK_BIT 7 65 #define FEATURE_DS_SOCCLK_BIT 8 66 #define FEATURE_DS_LCLK_BIT 9 67 #define FEATURE_DS_FCLK_BIT 10 68 #define FEATURE_DS_UCLK_BIT 11 69 #define FEATURE_GFX_ULV_BIT 12 70 #define FEATURE_DPM_VCN_BIT 13 71 #define FEATURE_RSMU_SMN_CG_BIT 14 72 #define FEATURE_WAFL_CG_BIT 15 73 // Throttler/Response 74 #define FEATURE_PPT_BIT 16 75 #define FEATURE_TDC_BIT 17 76 #define FEATURE_APCC_PLUS_BIT 18 77 #define FEATURE_VR0HOT_BIT 19 78 #define FEATURE_VR1HOT_BIT 20 79 #define FEATURE_FW_CTF_BIT 21 80 #define FEATURE_FAN_CONTROL_BIT 22 81 #define FEATURE_THERMAL_BIT 23 82 // Other 83 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 24 84 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25 85 86 #define FEATURE_SPARE_26_BIT 26 87 #define FEATURE_SPARE_27_BIT 27 88 #define FEATURE_SPARE_28_BIT 28 89 #define FEATURE_SPARE_29_BIT 29 90 #define FEATURE_SPARE_30_BIT 30 91 #define FEATURE_SPARE_31_BIT 31 92 #define FEATURE_SPARE_32_BIT 32 93 #define FEATURE_SPARE_33_BIT 33 94 #define FEATURE_SPARE_34_BIT 34 95 #define FEATURE_SPARE_35_BIT 35 96 #define FEATURE_SPARE_36_BIT 36 97 #define FEATURE_SPARE_37_BIT 37 98 #define FEATURE_SPARE_38_BIT 38 99 #define FEATURE_SPARE_39_BIT 39 100 #define FEATURE_SPARE_40_BIT 40 101 #define FEATURE_SPARE_41_BIT 41 102 #define FEATURE_SPARE_42_BIT 42 103 #define FEATURE_SPARE_43_BIT 43 104 #define FEATURE_SPARE_44_BIT 44 105 #define FEATURE_SPARE_45_BIT 45 106 #define FEATURE_SPARE_46_BIT 46 107 #define FEATURE_SPARE_47_BIT 47 108 #define FEATURE_SPARE_48_BIT 48 109 #define FEATURE_SPARE_49_BIT 49 110 #define FEATURE_SPARE_50_BIT 50 111 #define FEATURE_SPARE_51_BIT 51 112 #define FEATURE_SPARE_52_BIT 52 113 #define FEATURE_SPARE_53_BIT 53 114 #define FEATURE_SPARE_54_BIT 54 115 #define FEATURE_SPARE_55_BIT 55 116 #define FEATURE_SPARE_56_BIT 56 117 #define FEATURE_SPARE_57_BIT 57 118 #define FEATURE_SPARE_58_BIT 58 119 #define FEATURE_SPARE_59_BIT 59 120 #define FEATURE_SPARE_60_BIT 60 121 #define FEATURE_SPARE_61_BIT 61 122 #define FEATURE_SPARE_62_BIT 62 123 #define FEATURE_SPARE_63_BIT 63 124 125 #define NUM_FEATURES 64 126 127 128 #define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 129 #define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 130 #define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 131 #define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 132 #define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT ) 133 #define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 134 #define FEATURE_DPM_XGMI_MASK (1 << FEATURE_DPM_XGMI_BIT ) 135 136 #define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 137 #define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 138 #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 139 #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 140 #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 141 #define FEATURE_GFX_ULV_MASK (1 << FEATURE_GFX_ULV_BIT ) 142 #define FEATURE_VCN_PG_MASK (1 << FEATURE_VCN_PG_BIT ) 143 #define FEATURE_RSMU_SMN_CG_MASK (1 << FEATURE_RSMU_SMN_CG_BIT ) 144 #define FEATURE_WAFL_CG_MASK (1 << FEATURE_WAFL_CG_BIT ) 145 146 #define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 147 #define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 148 #define FEATURE_APCC_MASK (1 << FEATURE_APCC_BIT ) 149 #define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 150 #define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 151 #define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 152 #define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 153 #define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 154 155 #define FEATURE_OUT_OF_BAND_MONITOR_MASK (1 << EATURE_OUT_OF_BAND_MONITOR_BIT ) 156 #define FEATURE_TEMP_DEPENDENT_VMIN_MASK (1 << FEATURE_TEMP_DEPENDENT_VMIN_MASK ) 157 158 159 //FIXME need updating 160 // Debug Overrides Bitmask 161 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000001 162 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK 0x00000002 163 164 // I2C Config Bit Defines 165 #define I2C_CONTROLLER_ENABLED 1 166 #define I2C_CONTROLLER_DISABLED 0 167 168 // VR Mapping Bit Defines 169 #define VR_MAPPING_VR_SELECT_MASK 0x01 170 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 171 172 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 173 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 174 175 // PSI Bit Defines 176 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 177 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 178 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 179 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 180 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 181 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 182 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 183 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 184 185 // Throttler Control/Status Bits 186 #define THROTTLER_PADDING_BIT 0 187 #define THROTTLER_TEMP_EDGE_BIT 1 188 #define THROTTLER_TEMP_HOTSPOT_BIT 2 189 #define THROTTLER_TEMP_MEM_BIT 3 190 #define THROTTLER_TEMP_VR_GFX_BIT 4 191 #define THROTTLER_TEMP_VR_MEM_BIT 5 192 #define THROTTLER_TEMP_VR_SOC_BIT 6 193 #define THROTTLER_TDC_GFX_BIT 7 194 #define THROTTLER_TDC_SOC_BIT 8 195 #define THROTTLER_PPT0_BIT 9 196 #define THROTTLER_PPT1_BIT 10 197 #define THROTTLER_PPT2_BIT 11 198 #define THROTTLER_PPT3_BIT 12 199 #define THROTTLER_PPM_BIT 13 200 #define THROTTLER_FIT_BIT 14 201 #define THROTTLER_APCC_BIT 15 202 203 // Table transfer status 204 #define TABLE_TRANSFER_OK 0x0 205 #define TABLE_TRANSFER_FAILED 0xFF 206 #define TABLE_TRANSFER_PENDING 0xAB 207 208 // Workload bits 209 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 210 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 1 211 #define WORKLOAD_PPLIB_VIDEO_BIT 2 212 #define WORKLOAD_PPLIB_COMPUTE_BIT 3 213 #define WORKLOAD_PPLIB_CUSTOM_BIT 4 214 #define WORKLOAD_PPLIB_COUNT 5 215 216 //XGMI performance states 217 #define XGMI_STATE_D0 1 218 #define XGMI_STATE_D3 0 219 220 #define NUM_I2C_CONTROLLERS 8 221 222 #define I2C_CONTROLLER_ENABLED 1 223 #define I2C_CONTROLLER_DISABLED 0 224 225 #define MAX_SW_I2C_COMMANDS 8 226 227 typedef enum { 228 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 229 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 230 I2C_CONTROLLER_PORT_COUNT, 231 } I2cControllerPort_e; 232 233 typedef enum { 234 I2C_CONTROLLER_NAME_VR_GFX = 0, 235 I2C_CONTROLLER_NAME_VR_SOC, 236 I2C_CONTROLLER_NAME_VR_MEM, 237 I2C_CONTROLLER_NAME_SPARE, 238 I2C_CONTROLLER_NAME_COUNT, 239 } I2cControllerName_e; 240 241 typedef enum { 242 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 243 I2C_CONTROLLER_THROTTLER_VR_GFX, 244 I2C_CONTROLLER_THROTTLER_VR_SOC, 245 I2C_CONTROLLER_THROTTLER_VR_MEM, 246 I2C_CONTROLLER_THROTTLER_COUNT, 247 } I2cControllerThrottler_e; 248 249 typedef enum { 250 I2C_CONTROLLER_PROTOCOL_VR_0, 251 I2C_CONTROLLER_PROTOCOL_VR_1, 252 I2C_CONTROLLER_PROTOCOL_TMP_0, 253 I2C_CONTROLLER_PROTOCOL_TMP_1, 254 I2C_CONTROLLER_PROTOCOL_SPARE_0, 255 I2C_CONTROLLER_PROTOCOL_SPARE_1, 256 I2C_CONTROLLER_PROTOCOL_COUNT, 257 } I2cControllerProtocol_e; 258 259 typedef struct { 260 uint8_t Enabled; 261 uint8_t Speed; 262 uint8_t Padding[2]; 263 uint32_t SlaveAddress; 264 uint8_t ControllerPort; 265 uint8_t ControllerName; 266 uint8_t ThermalThrotter; 267 uint8_t I2cProtocol; 268 } I2cControllerConfig_t; 269 270 typedef enum { 271 I2C_PORT_SVD_SCL = 0, 272 I2C_PORT_GPIO, 273 } I2cPort_e; 274 275 typedef enum { 276 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 277 I2C_SPEED_FAST_100K, //100 Kbits/s 278 I2C_SPEED_FAST_400K, //400 Kbits/s 279 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 280 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 281 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 282 I2C_SPEED_COUNT, 283 } I2cSpeed_e; 284 285 typedef enum { 286 I2C_CMD_READ = 0, 287 I2C_CMD_WRITE, 288 I2C_CMD_COUNT, 289 } I2cCmdType_e; 290 291 #define CMDCONFIG_STOP_BIT 0 292 #define CMDCONFIG_RESTART_BIT 1 293 294 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 295 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 296 297 typedef struct { 298 uint8_t RegisterAddr; ////only valid for write, ignored for read 299 uint8_t Cmd; //Read(0) or Write(1) 300 uint8_t Data; //Return data for read. Data to send for write 301 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command 302 } SwI2cCmd_t; //SW I2C Command Table 303 304 typedef struct { 305 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 306 uint8_t I2CSpeed; //Slow(0) or Fast(1) 307 uint16_t SlaveAddress; 308 uint8_t NumCmds; //Number of commands 309 uint8_t Padding[3]; 310 311 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 312 313 uint32_t MmHubPadding[8]; // SMU internal use 314 315 } SwI2cRequest_t; // SW I2C Request Table 316 317 //D3HOT sequences 318 typedef enum { 319 BACO_SEQUENCE, 320 MSR_SEQUENCE, 321 BAMACO_SEQUENCE, 322 ULPS_SEQUENCE, 323 D3HOT_SEQUENCE_COUNT, 324 }D3HOTSequence_e; 325 326 //THis is aligned with RSMU PGFSM Register Mapping 327 typedef enum { 328 PG_DYNAMIC_MODE = 0, 329 PG_STATIC_MODE, 330 } PowerGatingMode_e; 331 332 //This is aligned with RSMU PGFSM Register Mapping 333 typedef enum { 334 PG_POWER_DOWN = 0, 335 PG_POWER_UP, 336 } PowerGatingSettings_e; 337 338 typedef struct { 339 uint32_t a; // store in IEEE float format in this variable 340 uint32_t b; // store in IEEE float format in this variable 341 uint32_t c; // store in IEEE float format in this variable 342 } QuadraticInt_t; 343 344 typedef struct { 345 uint32_t m; // store in IEEE float format in this variable 346 uint32_t b; // store in IEEE float format in this variable 347 } LinearInt_t; 348 349 typedef struct { 350 uint32_t a; // store in IEEE float format in this variable 351 uint32_t b; // store in IEEE float format in this variable 352 uint32_t c; // store in IEEE float format in this variable 353 } DroopInt_t; 354 355 typedef enum { 356 GFXCLK_SOURCE_PLL = 0, 357 GFXCLK_SOURCE_AFLL, 358 GFXCLK_SOURCE_COUNT, 359 } GfxclkSrc_e; 360 361 typedef enum { 362 PPCLK_GFXCLK, 363 PPCLK_VCLK, 364 PPCLK_DCLK, 365 PPCLK_SOCCLK, 366 PPCLK_UCLK, 367 PPCLK_FCLK, 368 PPCLK_COUNT, 369 } PPCLK_e; 370 371 typedef enum { 372 POWER_SOURCE_AC, 373 POWER_SOURCE_DC, 374 POWER_SOURCE_COUNT, 375 } POWER_SOURCE_e; 376 377 typedef enum { 378 TEMP_EDGE, 379 TEMP_HOTSPOT, 380 TEMP_MEM, 381 TEMP_VR_GFX, 382 TEMP_VR_SOC, 383 TEMP_VR_MEM, 384 TEMP_COUNT 385 } TEMP_TYPE_e; 386 387 typedef enum { 388 PPT_THROTTLER_PPT0, 389 PPT_THROTTLER_PPT1, 390 PPT_THROTTLER_PPT2, 391 PPT_THROTTLER_PPT3, 392 PPT_THROTTLER_COUNT 393 } PPT_THROTTLER_e; 394 395 typedef enum { 396 VOLTAGE_MODE_AVFS = 0, 397 VOLTAGE_MODE_AVFS_SS, 398 VOLTAGE_MODE_SS, 399 VOLTAGE_MODE_COUNT, 400 } VOLTAGE_MODE_e; 401 402 typedef enum { 403 AVFS_VOLTAGE_GFX = 0, 404 AVFS_VOLTAGE_SOC, 405 AVFS_VOLTAGE_COUNT, 406 } AVFS_VOLTAGE_TYPE_e; 407 408 typedef enum { 409 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 410 GPIO_INT_POLARITY_ACTIVE_HIGH, 411 } GpioIntPolarity_e; 412 413 typedef enum { 414 MEMORY_TYPE_GDDR6 = 0, 415 MEMORY_TYPE_HBM, 416 } MemoryType_e; 417 418 typedef enum { 419 PWR_CONFIG_TDP = 0, 420 PWR_CONFIG_TGP, 421 PWR_CONFIG_TCP_ESTIMATED, 422 PWR_CONFIG_TCP_MEASURED, 423 } PwrConfig_e; 424 425 typedef enum { 426 XGMI_LINK_RATE_12 = 0, // 12Gbps 427 XGMI_LINK_RATE_16, // 16Gbps 428 XGMI_LINK_RATE_22, // 22Gbps 429 XGMI_LINK_RATE_25, // 25Gbps 430 XGMI_LINK_RATE_COUNT 431 } XGMI_LINK_RATE_e; 432 433 typedef enum { 434 XGMI_LINK_WIDTH_2 = 0, // x2 435 XGMI_LINK_WIDTH_4, // x4 436 XGMI_LINK_WIDTH_8, // x8 437 XGMI_LINK_WIDTH_16, // x16 438 XGMI_LINK_WIDTH_COUNT 439 } XGMI_LINK_WIDTH_e; 440 441 typedef struct { 442 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 443 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 444 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 445 uint8_t padding; 446 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 447 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 448 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 449 uint16_t Padding16; 450 } DpmDescriptor_t; 451 452 typedef struct { 453 uint32_t Version; 454 455 // SECTION: Feature Enablement 456 uint32_t FeaturesToRun[2]; 457 458 // SECTION: Infrastructure Limits 459 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; 460 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; 461 uint16_t TdcLimitSoc; // Amps 462 uint16_t TdcLimitSocTau; // Time constant of LPF in ms 463 uint16_t TdcLimitGfx; // Amps 464 uint16_t TdcLimitGfxTau; // Time constant of LPF in ms 465 466 uint16_t TedgeLimit; // Celcius 467 uint16_t ThotspotLimit; // Celcius 468 uint16_t TmemLimit; // Celcius 469 uint16_t Tvr_gfxLimit; // Celcius 470 uint16_t Tvr_memLimit; // Celcius 471 uint16_t Tvr_socLimit; // Celcius 472 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 473 474 uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold 475 uint16_t PpmTemperatureThreshold; 476 477 // SECTION: Throttler settings 478 uint32_t ThrottlerControlMask; // See Throtter masks defines 479 480 // SECTION: ULV Settings 481 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 482 uint16_t UlvPadding; // Padding 483 484 uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV 485 uint8_t Padding234[3]; 486 487 // SECTION: Voltage Control Parameters 488 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 489 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 490 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 491 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 492 493 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 494 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 495 496 //SECTION: DPM Config 1 497 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 498 499 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 500 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 501 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 502 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 503 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 504 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 505 506 uint32_t Paddingclks[16]; 507 508 // SECTION: DPM Config 2 509 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 510 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 511 512 // GFXCLK DPM 513 uint16_t GfxclkFidle; // In MHz 514 uint16_t GfxclkSlewRate; // for PLL babystepping??? 515 uint8_t Padding567[4]; 516 uint16_t GfxclkDsMaxFreq; // In MHz 517 uint8_t GfxclkSource; // 0 = PLL, 1 = AFLL 518 uint8_t Padding456; 519 520 // GFXCLK Thermal DPM (formerly 'Boost' Settings) 521 uint16_t EnableTdpm; 522 uint16_t TdpmHighHystTemperature; 523 uint16_t TdpmLowHystTemperature; 524 uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. 525 526 // SECTION: Fan Control 527 uint16_t FanStopTemp; //Celcius 528 uint16_t FanStartTemp; //Celcius 529 530 uint16_t FanGainEdge; 531 uint16_t FanGainHotspot; 532 uint16_t FanGainVrGfx; 533 uint16_t FanGainVrSoc; 534 uint16_t FanGainVrMem; 535 uint16_t FanGainHbm; 536 uint16_t FanPwmMin; 537 uint16_t FanAcousticLimitRpm; 538 uint16_t FanThrottlingRpm; 539 uint16_t FanMaximumRpm; 540 uint16_t FanTargetTemperature; 541 uint16_t FanTargetGfxclk; 542 uint8_t FanZeroRpmEnable; 543 uint8_t FanTachEdgePerRev; 544 uint8_t FanTempInputSelect; 545 uint8_t padding8_Fan; 546 547 // The following are AFC override parameters. Leave at 0 to use FW defaults. 548 int16_t FuzzyFan_ErrorSetDelta; 549 int16_t FuzzyFan_ErrorRateSetDelta; 550 int16_t FuzzyFan_PwmSetDelta; 551 uint16_t FuzzyFan_Reserved; 552 553 554 // SECTION: AVFS 555 // Overrides 556 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 557 uint8_t Padding8_Avfs[2]; 558 559 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 560 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 561 DroopInt_t dBtcGbGfxAfll; // GHz->V BtcGb 562 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 563 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 564 565 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 566 567 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 568 569 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 570 uint8_t Padding8_GfxBtc[2]; 571 572 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 573 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 574 575 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 576 577 // SECTION: XGMI 578 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 579 uint8_t XgmiDpmSpare[2]; 580 581 // Temperature Dependent Vmin 582 uint16_t VDDGFX_TVmin; //Celcius 583 uint16_t VDDSOC_TVmin; //Celcius 584 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 585 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 586 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 587 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 588 589 uint16_t VDDGFX_TVminHystersis; // Celcius 590 uint16_t VDDSOC_TVminHystersis; // Celcius 591 592 593 // SECTION: Advanced Options 594 uint32_t DebugOverrides; 595 QuadraticInt_t ReservedEquation0; 596 QuadraticInt_t ReservedEquation1; 597 QuadraticInt_t ReservedEquation2; 598 QuadraticInt_t ReservedEquation3; 599 600 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 601 uint16_t PaddingUlv; // Padding 602 603 // Total Power configuration, use defines from PwrConfig_e 604 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured 605 uint8_t TotalPowerSpare1; 606 uint16_t TotalPowerSpare2; 607 608 // APCC Settings 609 uint16_t PccThresholdLow; 610 uint16_t PccThresholdHigh; 611 uint32_t PaddingAPCC[6]; //FIXME pending SPEC 612 613 // SECTION: Reserved 614 uint32_t Reserved[11]; 615 616 // SECTION: BOARD PARAMETERS 617 618 // SVI2 Board Parameters 619 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 620 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 621 622 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 623 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 624 uint8_t VddMemVrMapping; // Use VR_MAPPING* bitfields 625 uint8_t BoardVrMapping; // Use VR_MAPPING* bitfields 626 627 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 628 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 629 uint8_t Padding8_V[2]; 630 631 // Telemetry Settings 632 uint16_t GfxMaxCurrent; // in Amps 633 int8_t GfxOffset; // in Amps 634 uint8_t Padding_TelemetryGfx; 635 636 uint16_t SocMaxCurrent; // in Amps 637 int8_t SocOffset; // in Amps 638 uint8_t Padding_TelemetrySoc; 639 640 uint16_t MemMaxCurrent; // in Amps 641 int8_t MemOffset; // in Amps 642 uint8_t Padding_TelemetryMem; 643 644 uint16_t BoardMaxCurrent; // in Amps 645 int8_t BoardOffset; // in Amps 646 uint8_t Padding_TelemetryBoardInput; 647 648 // GPIO Settings 649 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 650 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 651 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 652 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 653 654 // GFXCLK PLL Spread Spectrum 655 uint8_t PllGfxclkSpreadEnabled; // on or off 656 uint8_t PllGfxclkSpreadPercent; // Q4.4 657 uint16_t PllGfxclkSpreadFreq; // kHz 658 659 // UCLK Spread Spectrum 660 uint8_t UclkSpreadEnabled; // on or off 661 uint8_t UclkSpreadPercent; // Q4.4 662 uint16_t UclkSpreadFreq; // kHz 663 664 // FCLK Spread Spectrum 665 uint8_t FclkSpreadEnabled; // on or off 666 uint8_t FclkSpreadPercent; // Q4.4 667 uint16_t FclkSpreadFreq; // kHz 668 669 // GFXCLK Fll Spread Spectrum 670 uint8_t FllGfxclkSpreadEnabled; // on or off 671 uint8_t FllGfxclkSpreadPercent; // Q4.4 672 uint16_t FllGfxclkSpreadFreq; // kHz 673 674 // I2C Controller Structure 675 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 676 677 // Memory section 678 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 679 680 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 681 uint8_t PaddingMem[3]; 682 683 // Total board power 684 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 685 uint16_t BoardPadding; 686 687 // SECTION: XGMI Training 688 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 689 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 690 691 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 692 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 693 694 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 695 uint8_t GpioI2cScl; // Serial Clock 696 uint8_t GpioI2cSda; // Serial Data 697 uint16_t GpioPadding; 698 699 uint32_t BoardReserved[9]; 700 701 // Padding for MMHUB - do not modify this 702 uint32_t MmHubPadding[8]; // SMU internal use 703 704 } PPTable_t; 705 706 typedef struct { 707 // Time constant parameters for clock averages in ms 708 uint16_t GfxclkAverageLpfTau; 709 uint16_t SocclkAverageLpfTau; 710 uint16_t UclkAverageLpfTau; 711 uint16_t GfxActivityLpfTau; 712 uint16_t UclkActivityLpfTau; 713 714 uint16_t SocketPowerLpfTau; 715 716 // Padding - ignore 717 uint32_t MmHubPadding[8]; // SMU internal use 718 } DriverSmuConfig_t; 719 720 typedef struct { 721 uint16_t CurrClock[PPCLK_COUNT]; 722 uint16_t AverageGfxclkFrequency; 723 uint16_t AverageSocclkFrequency; 724 uint16_t AverageUclkFrequency ; 725 uint16_t AverageGfxActivity ; 726 uint16_t AverageUclkActivity ; 727 uint8_t CurrSocVoltageOffset ; 728 uint8_t CurrGfxVoltageOffset ; 729 uint8_t CurrMemVidOffset ; 730 uint8_t Padding8 ; 731 uint16_t AverageSocketPower ; 732 uint16_t TemperatureEdge ; 733 uint16_t TemperatureHotspot ; 734 uint16_t TemperatureHBM ; 735 uint16_t TemperatureVrGfx ; 736 uint16_t TemperatureVrSoc ; 737 uint16_t TemperatureVrMem ; 738 uint32_t ThrottlerStatus ; 739 740 uint16_t CurrFanSpeed ; 741 uint16_t Padding16; 742 743 uint32_t Padding[4]; 744 745 // Padding - ignore 746 uint32_t MmHubPadding[8]; // SMU internal use 747 } SmuMetrics_t; 748 749 750 typedef struct { 751 uint16_t avgPsmCount[75]; 752 uint16_t minPsmCount[75]; 753 float avgPsmVoltage[75]; 754 float minPsmVoltage[75]; 755 756 uint32_t MmHubPadding[8]; // SMU internal use 757 } AvfsDebugTable_t; 758 759 typedef struct { 760 uint8_t AvfsVersion; 761 uint8_t Padding; 762 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 763 764 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 765 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 766 767 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 768 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 769 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 770 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 771 772 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 773 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 774 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 775 776 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 777 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 778 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 779 780 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 781 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 782 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 783 784 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 785 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 786 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 787 788 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 789 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 790 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 791 792 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 793 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 794 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 795 796 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 797 798 799 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 800 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 801 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 802 803 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 804 805 uint32_t EnabledAvfsModules[2]; 806 807 uint32_t MmHubPadding[8]; // SMU internal use 808 } AvfsFuseOverride_t; 809 810 /* NOT CURRENTLY USED 811 typedef struct { 812 uint8_t Gfx_ActiveHystLimit; 813 uint8_t Gfx_IdleHystLimit; 814 uint8_t Gfx_FPS; 815 uint8_t Gfx_MinActiveFreqType; 816 uint8_t Gfx_BoosterFreqType; 817 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 818 uint8_t Gfx_UseRlcBusy; 819 uint8_t PaddingGfx[3]; 820 uint16_t Gfx_MinActiveFreq; // MHz 821 uint16_t Gfx_BoosterFreq; // MHz 822 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 823 uint32_t Gfx_PD_Data_limit_a; // Q16 824 uint32_t Gfx_PD_Data_limit_b; // Q16 825 uint32_t Gfx_PD_Data_limit_c; // Q16 826 uint32_t Gfx_PD_Data_error_coeff; // Q16 827 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 828 829 uint8_t Mem_ActiveHystLimit; 830 uint8_t Mem_IdleHystLimit; 831 uint8_t Mem_FPS; 832 uint8_t Mem_MinActiveFreqType; 833 uint8_t Mem_BoosterFreqType; 834 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 835 uint8_t Mem_UseRlcBusy; 836 uint8_t PaddingMem[3]; 837 uint16_t Mem_MinActiveFreq; // MHz 838 uint16_t Mem_BoosterFreq; // MHz 839 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 840 uint32_t Mem_PD_Data_limit_a; // Q16 841 uint32_t Mem_PD_Data_limit_b; // Q16 842 uint32_t Mem_PD_Data_limit_c; // Q16 843 uint32_t Mem_PD_Data_error_coeff; // Q16 844 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 845 846 uint32_t Mem_UpThreshold_Limit; // Q16 847 uint8_t Mem_UpHystLimit; 848 uint8_t Mem_DownHystLimit; 849 uint16_t Mem_Fps; 850 851 uint32_t MmHubPadding[8]; // SMU internal use 852 } DpmActivityMonitorCoeffInt_t; 853 */ 854 855 // These defines are used with the following messages: 856 // SMC_MSG_TransferTableDram2Smu 857 // SMC_MSG_TransferTableSmu2Dram 858 #define TABLE_PPTABLE 0 859 #define TABLE_AVFS 1 860 #define TABLE_AVFS_PSM_DEBUG 2 861 #define TABLE_AVFS_FUSE_OVERRIDE 3 862 #define TABLE_PMSTATUSLOG 4 863 #define TABLE_SMU_METRICS 5 864 #define TABLE_DRIVER_SMU_CONFIG 6 865 //#define TABLE_ACTIVITY_MONITOR_COEFF 7 866 #define TABLE_OVERDRIVE 7 867 #define TABLE_WAFL_XGMI_TOPOLOGY 8 868 #define TABLE_COUNT 9 869 870 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 871 typedef enum { 872 DF_SWITCH_TYPE_FAST = 0, 873 DF_SWITCH_TYPE_SLOW, 874 DF_SWITCH_TYPE_COUNT, 875 } DF_SWITCH_TYPE_e; 876 877 typedef enum { 878 DRAM_BIT_WIDTH_DISABLED = 0, 879 DRAM_BIT_WIDTH_X_8, 880 DRAM_BIT_WIDTH_X_16, 881 DRAM_BIT_WIDTH_X_32, 882 DRAM_BIT_WIDTH_X_64, // NOT USED. 883 DRAM_BIT_WIDTH_X_128, 884 DRAM_BIT_WIDTH_COUNT, 885 } DRAM_BIT_WIDTH_TYPE_e; 886 887 #define REMOVE_FMAX_MARGIN_BIT 0x0 888 #define REMOVE_DCTOL_MARGIN_BIT 0x1 889 #define REMOVE_PLATFORM_MARGIN_BIT 0x2 890 891 #endif 892
