1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_ENCODER__DCN20_H__ 27 #define __DC_LINK_ENCODER__DCN20_H__ 28 29 #include "dcn10/dcn10_link_encoder.h" 30 31 #define DCN2_AUX_REG_LIST(id)\ 32 AUX_REG_LIST(id), \ 33 SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id) 34 35 #define UNIPHY_MASK_SH_LIST(mask_sh)\ 36 LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh) 37 38 #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\ 39 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\ 40 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ 41 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ 42 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ 43 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\ 44 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\ 45 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\ 46 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\ 47 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\ 48 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ 49 UNIPHY_MASK_SH_LIST(mask_sh),\ 50 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ 51 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ 52 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ 53 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ 54 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ 55 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ 56 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ 57 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ 58 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ 59 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ 60 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh) 61 62 #define UNIPHY_DCN2_REG_LIST(id) \ 63 SRI(CLOCK_ENABLE, SYMCLK, id), \ 64 SRI(CHANNEL_XBAR_CNTL, UNIPHY, id) 65 66 struct mpll_cfg { 67 uint32_t mpllb_ana_v2i; 68 uint32_t mpllb_ana_freq_vco; 69 uint32_t mpllb_ana_cp_int; 70 uint32_t mpllb_ana_cp_prop; 71 uint32_t mpllb_multiplier; 72 uint32_t ref_clk_mpllb_div; 73 bool mpllb_word_div2_en; 74 bool mpllb_ssc_en; 75 bool mpllb_div5_clk_en; 76 bool mpllb_div_clk_en; 77 bool mpllb_fracn_en; 78 bool mpllb_pmix_en; 79 uint32_t mpllb_div_multiplier; 80 uint32_t mpllb_tx_clk_div; 81 uint32_t mpllb_fracn_quot; 82 uint32_t mpllb_fracn_den; 83 uint32_t mpllb_ssc_peak; 84 uint32_t mpllb_ssc_stepsize; 85 uint32_t mpllb_ssc_up_spread; 86 uint32_t mpllb_fracn_rem; 87 uint32_t mpllb_hdmi_div; 88 // TODO: May not mpll params, need to figure out. 89 uint32_t tx_vboost_lvl; 90 uint32_t hdmi_pixel_clk_div; 91 uint32_t ref_range; 92 uint32_t ref_clk; 93 bool hdmimode_enable; 94 }; 95 96 struct dpcssys_phy_seq_cfg { 97 bool program_fuse; 98 bool bypass_sram; 99 bool lane_en[4]; 100 bool use_calibration_setting; 101 struct mpll_cfg mpll_cfg; 102 bool load_sram_fw; 103 #if 0 104 105 bool hdmimode_enable; 106 bool silver2; 107 bool ext_refclk_en; 108 uint32_t dp_tx0_term_ctrl; 109 uint32_t dp_tx1_term_ctrl; 110 uint32_t dp_tx2_term_ctrl; 111 uint32_t dp_tx3_term_ctrl; 112 uint32_t fw_data[0x1000]; 113 uint32_t dp_tx0_width; 114 uint32_t dp_tx1_width; 115 uint32_t dp_tx2_width; 116 uint32_t dp_tx3_width; 117 uint32_t dp_tx0_rate; 118 uint32_t dp_tx1_rate; 119 uint32_t dp_tx2_rate; 120 uint32_t dp_tx3_rate; 121 uint32_t dp_tx0_eq_main; 122 uint32_t dp_tx0_eq_pre; 123 uint32_t dp_tx0_eq_post; 124 uint32_t dp_tx1_eq_main; 125 uint32_t dp_tx1_eq_pre; 126 uint32_t dp_tx1_eq_post; 127 uint32_t dp_tx2_eq_main; 128 uint32_t dp_tx2_eq_pre; 129 uint32_t dp_tx2_eq_post; 130 uint32_t dp_tx3_eq_main; 131 uint32_t dp_tx3_eq_pre; 132 uint32_t dp_tx3_eq_post; 133 bool data_swap_en; 134 bool data_order_invert_en; 135 uint32_t ldpcs_fifo_start_delay; 136 uint32_t rdpcs_fifo_start_delay; 137 bool rdpcs_reg_fifo_error_mask; 138 bool rdpcs_tx_fifo_error_mask; 139 bool rdpcs_dpalt_disable_mask; 140 bool rdpcs_dpalt_4lane_mask; 141 #endif 142 }; 143 144 struct dcn20_link_encoder { 145 struct dcn10_link_encoder enc10; 146 struct dpcssys_phy_seq_cfg phy_seq_cfg; 147 }; 148 149 void enc2_fec_set_enable(struct link_encoder *enc, bool enable); 150 void enc2_fec_set_ready(struct link_encoder *enc, bool ready); 151 bool enc2_fec_is_active(struct link_encoder *enc); 152 void enc2_hw_init(struct link_encoder *enc); 153 154 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 155 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); 156 #endif 157 158 void dcn20_link_encoder_enable_dp_output( 159 struct link_encoder *enc, 160 const struct dc_link_settings *link_settings, 161 enum clock_source_id clock_source); 162 163 void dcn20_link_encoder_construct( 164 struct dcn20_link_encoder *enc20, 165 const struct encoder_init_data *init_data, 166 const struct encoder_feature_support *enc_features, 167 const struct dcn10_link_enc_registers *link_regs, 168 const struct dcn10_link_enc_aux_registers *aux_regs, 169 const struct dcn10_link_enc_hpd_registers *hpd_regs, 170 const struct dcn10_link_enc_shift *link_shift, 171 const struct dcn10_link_enc_mask *link_mask); 172 173 #endif /* __DC_LINK_ENCODER__DCN20_H__ */ 174
