1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "core_types.h"
29
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33
34 #define NUM_PHASES 64
35 #define HORZ_MAX_TAPS 8
36 #define VERT_MAX_TAPS 8
37
38 #define BLACK_OFFSET_RGB_Y 0x0
39 #define BLACK_OFFSET_CBCR 0x8000
40
41 #define REG(reg)\
42 dpp->tf_regs->reg
43
44 #define CTX \
45 dpp->base.ctx
46
47 #undef FN
48 #define FN(reg_name, field_name) \
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
50
51 enum pixel_format_description {
52 PIXEL_FORMAT_FIXED = 0,
53 PIXEL_FORMAT_FIXED16,
54 PIXEL_FORMAT_FLOAT
55
56 };
57
58 enum dcn10_coef_filter_type_sel {
59 SCL_COEF_LUMA_VERT_FILTER = 0,
60 SCL_COEF_LUMA_HORZ_FILTER = 1,
61 SCL_COEF_CHROMA_VERT_FILTER = 2,
62 SCL_COEF_CHROMA_HORZ_FILTER = 3,
63 SCL_COEF_ALPHA_VERT_FILTER = 4,
64 SCL_COEF_ALPHA_HORZ_FILTER = 5
65 };
66
67 enum dscl_autocal_mode {
68 AUTOCAL_MODE_OFF = 0,
69
70 /* Autocal calculate the scaling ratio and initial phase and the
71 * DSCL_MODE_SEL must be set to 1
72 */
73 AUTOCAL_MODE_AUTOSCALE = 1,
74 /* Autocal perform auto centering without replication and the
75 * DSCL_MODE_SEL must be set to 0
76 */
77 AUTOCAL_MODE_AUTOCENTER = 2,
78 /* Autocal perform auto centering and auto replication and the
79 * DSCL_MODE_SEL must be set to 0
80 */
81 AUTOCAL_MODE_AUTOREPLICATE = 3
82 };
83
84 enum dscl_mode_sel {
85 DSCL_MODE_SCALING_444_BYPASS = 0,
86 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
87 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
88 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
89 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
90 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
91 DSCL_MODE_DSCL_BYPASS = 6
92 };
93
dpp_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)94 void dpp_read_state(struct dpp *dpp_base,
95 struct dcn_dpp_state *s)
96 {
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
98
99 REG_GET(DPP_CONTROL,
100 DPP_CLOCK_ENABLE, &s->is_enabled);
101 REG_GET(CM_IGAM_CONTROL,
102 CM_IGAM_LUT_MODE, &s->igam_lut_mode);
103 REG_GET(CM_IGAM_CONTROL,
104 CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
105 REG_GET(CM_DGAM_CONTROL,
106 CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
107 REG_GET(CM_RGAM_CONTROL,
108 CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
109 REG_GET(CM_GAMUT_REMAP_CONTROL,
110 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
111
112 if (s->gamut_remap_mode) {
113 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
114 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
115 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
116 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
117 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
118 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
119 }
120 }
121
122 /* Program gamut remap in bypass mode */
dpp_set_gamut_remap_bypass(struct dcn10_dpp * dpp)123 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
124 {
125 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
126 CM_GAMUT_REMAP_MODE, 0);
127 /* Gamut remap in bypass */
128 }
129
130 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
131
dpp_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)132 static bool dpp_get_optimal_number_of_taps(
133 struct dpp *dpp,
134 struct scaler_data *scl_data,
135 const struct scaling_taps *in_taps)
136 {
137 uint32_t pixel_width;
138
139 if (scl_data->viewport.width > scl_data->recout.width)
140 pixel_width = scl_data->recout.width;
141 else
142 pixel_width = scl_data->viewport.width;
143
144 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/
145 if (scl_data->format == PIXEL_FORMAT_FP16 &&
146 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
147 scl_data->ratios.horz.value != dc_fixpt_one.value &&
148 scl_data->ratios.vert.value != dc_fixpt_one.value)
149 return false;
150
151 if (scl_data->viewport.width > scl_data->h_active &&
152 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
153 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
154 return false;
155
156 /* TODO: add lb check */
157
158 /* No support for programming ratio of 4, drop to 3.99999.. */
159 if (scl_data->ratios.horz.value == (4ll << 32))
160 scl_data->ratios.horz.value--;
161 if (scl_data->ratios.vert.value == (4ll << 32))
162 scl_data->ratios.vert.value--;
163 if (scl_data->ratios.horz_c.value == (4ll << 32))
164 scl_data->ratios.horz_c.value--;
165 if (scl_data->ratios.vert_c.value == (4ll << 32))
166 scl_data->ratios.vert_c.value--;
167
168 /* Set default taps if none are provided */
169 if (in_taps->h_taps == 0)
170 scl_data->taps.h_taps = 4;
171 else
172 scl_data->taps.h_taps = in_taps->h_taps;
173 if (in_taps->v_taps == 0)
174 scl_data->taps.v_taps = 4;
175 else
176 scl_data->taps.v_taps = in_taps->v_taps;
177 if (in_taps->v_taps_c == 0)
178 scl_data->taps.v_taps_c = 2;
179 else
180 scl_data->taps.v_taps_c = in_taps->v_taps_c;
181 if (in_taps->h_taps_c == 0)
182 scl_data->taps.h_taps_c = 2;
183 /* Only 1 and even h_taps_c are supported by hw */
184 else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
185 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
186 else
187 scl_data->taps.h_taps_c = in_taps->h_taps_c;
188
189 if (!dpp->ctx->dc->debug.always_scale) {
190 if (IDENTITY_RATIO(scl_data->ratios.horz))
191 scl_data->taps.h_taps = 1;
192 if (IDENTITY_RATIO(scl_data->ratios.vert))
193 scl_data->taps.v_taps = 1;
194 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
195 scl_data->taps.h_taps_c = 1;
196 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
197 scl_data->taps.v_taps_c = 1;
198 }
199
200 return true;
201 }
202
dpp_reset(struct dpp * dpp_base)203 void dpp_reset(struct dpp *dpp_base)
204 {
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
206
207 dpp->filter_h_c = NULL;
208 dpp->filter_v_c = NULL;
209 dpp->filter_h = NULL;
210 dpp->filter_v = NULL;
211
212 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
213 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
214 }
215
216
217
dpp1_cm_set_regamma_pwl(struct dpp * dpp_base,const struct pwl_params * params,enum opp_regamma mode)218 static void dpp1_cm_set_regamma_pwl(
219 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
220 {
221 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
222 uint32_t re_mode = 0;
223
224 switch (mode) {
225 case OPP_REGAMMA_BYPASS:
226 re_mode = 0;
227 break;
228 case OPP_REGAMMA_SRGB:
229 re_mode = 1;
230 break;
231 case OPP_REGAMMA_XVYCC:
232 re_mode = 2;
233 break;
234 case OPP_REGAMMA_USER:
235 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
236 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
237 break;
238
239 dpp1_cm_power_on_regamma_lut(dpp_base, true);
240 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
241
242 if (dpp->is_write_to_ram_a_safe)
243 dpp1_cm_program_regamma_luta_settings(dpp_base, params);
244 else
245 dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
246
247 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
248 params->hw_points_num);
249 dpp->pwl_data = *params;
250
251 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
252 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
253 break;
254 default:
255 break;
256 }
257 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
258 }
259
dpp1_setup_format_flags(enum surface_pixel_format input_format,enum pixel_format_description * fmt)260 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
261 enum pixel_format_description *fmt)
262 {
263
264 if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
265 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
266 *fmt = PIXEL_FORMAT_FLOAT;
267 else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
268 *fmt = PIXEL_FORMAT_FIXED16;
269 else
270 *fmt = PIXEL_FORMAT_FIXED;
271 }
272
dpp1_set_degamma_format_float(struct dpp * dpp_base,bool is_float)273 static void dpp1_set_degamma_format_float(
274 struct dpp *dpp_base,
275 bool is_float)
276 {
277 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
278
279 if (is_float) {
280 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
281 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
282 } else {
283 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
284 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
285 }
286 }
287
dpp1_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)288 void dpp1_cnv_setup (
289 struct dpp *dpp_base,
290 enum surface_pixel_format format,
291 enum expansion_mode mode,
292 struct dc_csc_transform input_csc_color_matrix,
293 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
294 enum dc_color_space input_color_space,
295 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
296 #else
297 enum dc_color_space input_color_space)
298 #endif
299 {
300 uint32_t pixel_format;
301 uint32_t alpha_en;
302 enum pixel_format_description fmt ;
303 enum dc_color_space color_space;
304 enum dcn10_input_csc_select select;
305 bool is_float;
306 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
307 bool force_disable_cursor = false;
308 struct out_csc_color_matrix tbl_entry;
309 int i = 0;
310
311 dpp1_setup_format_flags(format, &fmt);
312 alpha_en = 1;
313 pixel_format = 0;
314 color_space = COLOR_SPACE_SRGB;
315 select = INPUT_CSC_SELECT_BYPASS;
316 is_float = false;
317
318 switch (fmt) {
319 case PIXEL_FORMAT_FIXED:
320 case PIXEL_FORMAT_FIXED16:
321 /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
322 REG_SET_3(FORMAT_CONTROL, 0,
323 CNVC_BYPASS, 0,
324 FORMAT_EXPANSION_MODE, mode,
325 OUTPUT_FP, 0);
326 break;
327 case PIXEL_FORMAT_FLOAT:
328 REG_SET_3(FORMAT_CONTROL, 0,
329 CNVC_BYPASS, 0,
330 FORMAT_EXPANSION_MODE, mode,
331 OUTPUT_FP, 1);
332 is_float = true;
333 break;
334 default:
335
336 break;
337 }
338
339 dpp1_set_degamma_format_float(dpp_base, is_float);
340
341 switch (format) {
342 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
343 pixel_format = 1;
344 break;
345 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
346 pixel_format = 3;
347 alpha_en = 0;
348 break;
349 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
350 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
351 pixel_format = 8;
352 break;
353 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
354 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
355 pixel_format = 10;
356 break;
357 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
358 force_disable_cursor = false;
359 pixel_format = 65;
360 color_space = COLOR_SPACE_YCBCR709;
361 select = INPUT_CSC_SELECT_ICSC;
362 break;
363 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
364 force_disable_cursor = true;
365 pixel_format = 64;
366 color_space = COLOR_SPACE_YCBCR709;
367 select = INPUT_CSC_SELECT_ICSC;
368 break;
369 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
370 force_disable_cursor = true;
371 pixel_format = 67;
372 color_space = COLOR_SPACE_YCBCR709;
373 select = INPUT_CSC_SELECT_ICSC;
374 break;
375 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
376 force_disable_cursor = true;
377 pixel_format = 66;
378 color_space = COLOR_SPACE_YCBCR709;
379 select = INPUT_CSC_SELECT_ICSC;
380 break;
381 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
382 pixel_format = 22;
383 break;
384 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
385 pixel_format = 24;
386 break;
387 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
388 pixel_format = 25;
389 break;
390 default:
391 break;
392 }
393
394 /* Set default color space based on format if none is given. */
395 color_space = input_color_space ? input_color_space : color_space;
396
397 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
398 CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
399 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
400
401 // if input adjustments exist, program icsc with those values
402
403 if (input_csc_color_matrix.enable_adjustment
404 == true) {
405 for (i = 0; i < 12; i++)
406 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
407
408 tbl_entry.color_space = color_space;
409
410 if (color_space >= COLOR_SPACE_YCBCR601)
411 select = INPUT_CSC_SELECT_ICSC;
412 else
413 select = INPUT_CSC_SELECT_BYPASS;
414
415 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
416 } else
417 dpp1_program_input_csc(dpp_base, color_space, select, NULL);
418
419 if (force_disable_cursor) {
420 REG_UPDATE(CURSOR_CONTROL,
421 CURSOR_ENABLE, 0);
422 REG_UPDATE(CURSOR0_CONTROL,
423 CUR0_ENABLE, 0);
424 }
425 }
426
dpp1_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)427 void dpp1_set_cursor_attributes(
428 struct dpp *dpp_base,
429 struct dc_cursor_attributes *cursor_attributes)
430 {
431 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
432 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
433
434 REG_UPDATE_2(CURSOR0_CONTROL,
435 CUR0_MODE, color_format,
436 CUR0_EXPANSION_MODE, 0);
437
438 if (color_format == CURSOR_MODE_MONO) {
439 /* todo: clarify what to program these to */
440 REG_UPDATE(CURSOR0_COLOR0,
441 CUR0_COLOR0, 0x00000000);
442 REG_UPDATE(CURSOR0_COLOR1,
443 CUR0_COLOR1, 0xFFFFFFFF);
444 }
445 }
446
447
dpp1_set_cursor_position(struct dpp * dpp_base,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param,uint32_t width,uint32_t height)448 void dpp1_set_cursor_position(
449 struct dpp *dpp_base,
450 const struct dc_cursor_position *pos,
451 const struct dc_cursor_mi_param *param,
452 uint32_t width,
453 uint32_t height)
454 {
455 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
456 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
457 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
458 uint32_t cur_en = pos->enable ? 1 : 0;
459
460 // Cursor width/height and hotspots need to be rotated for offset calculation
461 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
462 swap(width, height);
463 if (param->rotation == ROTATION_ANGLE_90) {
464 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
465 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
466 }
467 } else if (param->rotation == ROTATION_ANGLE_180) {
468 src_x_offset = pos->x - param->viewport.x;
469 src_y_offset = pos->y - param->viewport.y;
470 }
471
472
473 if (src_x_offset >= (int)param->viewport.width)
474 cur_en = 0; /* not visible beyond right edge*/
475
476 if (src_x_offset + (int)width <= 0)
477 cur_en = 0; /* not visible beyond left edge*/
478
479 if (src_y_offset >= (int)param->viewport.height)
480 cur_en = 0; /* not visible beyond bottom edge*/
481
482 if (src_y_offset + (int)height <= 0)
483 cur_en = 0; /* not visible beyond top edge*/
484
485 REG_UPDATE(CURSOR0_CONTROL,
486 CUR0_ENABLE, cur_en);
487
488 }
489
dpp1_cnv_set_optional_cursor_attributes(struct dpp * dpp_base,struct dpp_cursor_attributes * attr)490 void dpp1_cnv_set_optional_cursor_attributes(
491 struct dpp *dpp_base,
492 struct dpp_cursor_attributes *attr)
493 {
494 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
495
496 if (attr) {
497 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias);
498 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale);
499 }
500 }
501
dpp1_dppclk_control(struct dpp * dpp_base,bool dppclk_div,bool enable)502 void dpp1_dppclk_control(
503 struct dpp *dpp_base,
504 bool dppclk_div,
505 bool enable)
506 {
507 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
508
509 if (enable) {
510 if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
511 REG_UPDATE_2(DPP_CONTROL,
512 DPPCLK_RATE_CONTROL, dppclk_div,
513 DPP_CLOCK_ENABLE, 1);
514 else
515 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
516 } else
517 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
518 }
519
520 static const struct dpp_funcs dcn10_dpp_funcs = {
521 .dpp_read_state = dpp_read_state,
522 .dpp_reset = dpp_reset,
523 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
524 .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
525 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
526 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
527 .dpp_set_csc_default = dpp1_cm_set_output_csc_default,
528 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
529 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
530 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
531 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
532 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
533 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
534 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
535 .dpp_set_degamma = dpp1_set_degamma,
536 .dpp_program_input_lut = dpp1_program_input_lut,
537 .dpp_program_degamma_pwl = dpp1_set_degamma_pwl,
538 .dpp_setup = dpp1_cnv_setup,
539 .dpp_full_bypass = dpp1_full_bypass,
540 .set_cursor_attributes = dpp1_set_cursor_attributes,
541 .set_cursor_position = dpp1_set_cursor_position,
542 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
543 .dpp_dppclk_control = dpp1_dppclk_control,
544 .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
545 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
546 .dpp_program_blnd_lut = NULL,
547 .dpp_program_shaper_lut = NULL,
548 .dpp_program_3dlut = NULL
549 #endif
550 };
551
552 static struct dpp_caps dcn10_dpp_cap = {
553 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
554 .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
555 };
556
557 /*****************************************/
558 /* Constructor, Destructor */
559 /*****************************************/
560
dpp1_construct(struct dcn10_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn_dpp_registers * tf_regs,const struct dcn_dpp_shift * tf_shift,const struct dcn_dpp_mask * tf_mask)561 void dpp1_construct(
562 struct dcn10_dpp *dpp,
563 struct dc_context *ctx,
564 uint32_t inst,
565 const struct dcn_dpp_registers *tf_regs,
566 const struct dcn_dpp_shift *tf_shift,
567 const struct dcn_dpp_mask *tf_mask)
568 {
569 dpp->base.ctx = ctx;
570
571 dpp->base.inst = inst;
572 dpp->base.funcs = &dcn10_dpp_funcs;
573 dpp->base.caps = &dcn10_dpp_cap;
574
575 dpp->tf_regs = tf_regs;
576 dpp->tf_shift = tf_shift;
577 dpp->tf_mask = tf_mask;
578
579 dpp->lb_pixel_depth_supported =
580 LB_PIXEL_DEPTH_18BPP |
581 LB_PIXEL_DEPTH_24BPP |
582 LB_PIXEL_DEPTH_30BPP;
583
584 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
585 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
586 }
587
