1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/of_address.h>
9
10 #include "ccu_common.h"
11 #include "ccu_reset.h"
12
13 #include "ccu_div.h"
14 #include "ccu_gate.h"
15 #include "ccu_mp.h"
16 #include "ccu_mult.h"
17 #include "ccu_nk.h"
18 #include "ccu_nkm.h"
19 #include "ccu_nkmp.h"
20 #include "ccu_nm.h"
21 #include "ccu_phase.h"
22 #include "ccu_sdm.h"
23
24 #include "ccu-sun8i-a23-a33.h"
25
26
27 static struct ccu_nkmp pll_cpux_clk = {
28 .enable = BIT(31),
29 .lock = BIT(28),
30
31 .n = _SUNXI_CCU_MULT(8, 5),
32 .k = _SUNXI_CCU_MULT(4, 2),
33 .m = _SUNXI_CCU_DIV(0, 2),
34 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35
36 .common = {
37 .reg = 0x000,
38 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
39 &ccu_nkmp_ops,
40 0),
41 },
42 };
43
44 /*
45 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * the base (2x, 4x and 8x), and one variable divider (the one true
47 * pll audio).
48 *
49 * With sigma-delta modulation for fractional-N on the audio PLL,
50 * we have to use specific dividers. This means the variable divider
51 * can no longer be used, as the audio codec requests the exact clock
52 * rates we support through this mechanism. So we now hard code the
53 * variable divider to 1. This means the clock rates will no longer
54 * match the clock names.
55 */
56 #define SUN8I_A23_PLL_AUDIO_REG 0x008
57
58 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
61 };
62
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
64 "osc24M", 0x008,
65 8, 7, /* N */
66 0, 5, /* M */
67 pll_audio_sdm_table, BIT(24),
68 0x284, BIT(31),
69 BIT(31), /* gate */
70 BIT(28), /* lock */
71 CLK_SET_RATE_UNGATE);
72
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
74 "osc24M", 0x010,
75 8, 7, /* N */
76 0, 4, /* M */
77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
79 270000000, /* frac rate 0 */
80 297000000, /* frac rate 1 */
81 BIT(31), /* gate */
82 BIT(28), /* lock */
83 CLK_SET_RATE_UNGATE);
84
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 "osc24M", 0x018,
87 8, 7, /* N */
88 0, 4, /* M */
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
91 270000000, /* frac rate 0 */
92 297000000, /* frac rate 1 */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
95 CLK_SET_RATE_UNGATE);
96
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
98 "osc24M", 0x020,
99 8, 5, /* N */
100 4, 2, /* K */
101 0, 2, /* M */
102 BIT(31), /* gate */
103 BIT(28), /* lock */
104 0);
105
106 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
107 "osc24M", 0x028,
108 8, 5, /* N */
109 4, 2, /* K */
110 BIT(31), /* gate */
111 BIT(28), /* lock */
112 2, /* post-div */
113 CLK_SET_RATE_UNGATE);
114
115 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
116 "osc24M", 0x038,
117 8, 7, /* N */
118 0, 4, /* M */
119 BIT(24), /* frac enable */
120 BIT(25), /* frac select */
121 270000000, /* frac rate 0 */
122 297000000, /* frac rate 1 */
123 BIT(31), /* gate */
124 BIT(28), /* lock */
125 CLK_SET_RATE_UNGATE);
126
127 /*
128 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
129 *
130 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
131 * integer / fractional clock with switchable multipliers and dividers.
132 * This is not supported here. We hardcode the PLL to MIPI mode.
133 */
134 #define SUN8I_A23_PLL_MIPI_REG 0x040
135 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
136 "pll-video", 0x040,
137 8, 4, /* N */
138 4, 2, /* K */
139 0, 4, /* M */
140 BIT(31) | BIT(23) | BIT(22), /* gate */
141 BIT(28), /* lock */
142 CLK_SET_RATE_UNGATE);
143
144 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
145 "osc24M", 0x044,
146 8, 7, /* N */
147 0, 4, /* M */
148 BIT(24), /* frac enable */
149 BIT(25), /* frac select */
150 270000000, /* frac rate 0 */
151 297000000, /* frac rate 1 */
152 BIT(31), /* gate */
153 BIT(28), /* lock */
154 CLK_SET_RATE_UNGATE);
155
156 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
157 "osc24M", 0x048,
158 8, 7, /* N */
159 0, 4, /* M */
160 BIT(24), /* frac enable */
161 BIT(25), /* frac select */
162 270000000, /* frac rate 0 */
163 297000000, /* frac rate 1 */
164 BIT(31), /* gate */
165 BIT(28), /* lock */
166 CLK_SET_RATE_UNGATE);
167
168 static const char * const cpux_parents[] = { "osc32k", "osc24M",
169 "pll-cpux" , "pll-cpux" };
170 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
171 0x050, 16, 2, CLK_IS_CRITICAL);
172
173 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
174
175 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
176 "axi" , "pll-periph" };
177 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
178 { .index = 3, .shift = 6, .width = 2 },
179 };
180 static struct ccu_div ahb1_clk = {
181 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
182
183 .mux = {
184 .shift = 12,
185 .width = 2,
186
187 .var_predivs = ahb1_predivs,
188 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
189 },
190
191 .common = {
192 .reg = 0x054,
193 .features = CCU_FEATURE_VARIABLE_PREDIV,
194 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
195 ahb1_parents,
196 &ccu_div_ops,
197 0),
198 },
199 };
200
201 static struct clk_div_table apb1_div_table[] = {
202 { .val = 0, .div = 2 },
203 { .val = 1, .div = 2 },
204 { .val = 2, .div = 4 },
205 { .val = 3, .div = 8 },
206 { /* Sentinel */ },
207 };
208 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
209 0x054, 8, 2, apb1_div_table, 0);
210
211 static const char * const apb2_parents[] = { "osc32k", "osc24M",
212 "pll-periph" , "pll-periph" };
213 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
214 0, 5, /* M */
215 16, 2, /* P */
216 24, 2, /* mux */
217 0);
218
219 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
220 0x060, BIT(1), 0);
221 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
222 0x060, BIT(6), 0);
223 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
224 0x060, BIT(8), 0);
225 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
226 0x060, BIT(9), 0);
227 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
228 0x060, BIT(10), 0);
229 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
230 0x060, BIT(13), 0);
231 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
232 0x060, BIT(14), 0);
233 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
234 0x060, BIT(19), 0);
235 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
236 0x060, BIT(20), 0);
237 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
238 0x060, BIT(21), 0);
239 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
240 0x060, BIT(24), 0);
241 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
242 0x060, BIT(26), 0);
243 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
244 0x060, BIT(29), 0);
245
246 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
247 0x064, BIT(0), 0);
248 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
249 0x064, BIT(4), 0);
250 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
251 0x064, BIT(8), 0);
252 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
253 0x064, BIT(12), 0);
254 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
255 0x064, BIT(14), 0);
256 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
257 0x064, BIT(20), 0);
258 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
259 0x064, BIT(21), 0);
260 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
261 0x064, BIT(22), 0);
262 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
263 0x064, BIT(25), 0);
264
265 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
266 0x068, BIT(0), 0);
267 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
268 0x068, BIT(5), 0);
269 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
270 0x068, BIT(12), 0);
271 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
272 0x068, BIT(13), 0);
273
274 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
275 0x06c, BIT(0), 0);
276 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
277 0x06c, BIT(1), 0);
278 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
279 0x06c, BIT(2), 0);
280 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
281 0x06c, BIT(16), 0);
282 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
283 0x06c, BIT(17), 0);
284 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
285 0x06c, BIT(18), 0);
286 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
287 0x06c, BIT(19), 0);
288 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
289 0x06c, BIT(20), 0);
290
291 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
292 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
293 0, 4, /* M */
294 16, 2, /* P */
295 24, 2, /* mux */
296 BIT(31), /* gate */
297 0);
298
299 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
300 0, 4, /* M */
301 16, 2, /* P */
302 24, 2, /* mux */
303 BIT(31), /* gate */
304 0);
305
306 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
307 0x088, 20, 3, 0);
308 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
309 0x088, 8, 3, 0);
310
311 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
312 0, 4, /* M */
313 16, 2, /* P */
314 24, 2, /* mux */
315 BIT(31), /* gate */
316 0);
317
318 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
319 0x08c, 20, 3, 0);
320 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
321 0x08c, 8, 3, 0);
322
323 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
324 0, 4, /* M */
325 16, 2, /* P */
326 24, 2, /* mux */
327 BIT(31), /* gate */
328 0);
329
330 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
331 0x090, 20, 3, 0);
332 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
333 0x090, 8, 3, 0);
334
335 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
336 0, 4, /* M */
337 16, 2, /* P */
338 24, 2, /* mux */
339 BIT(31), /* gate */
340 0);
341
342 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
343 0, 4, /* M */
344 16, 2, /* P */
345 24, 2, /* mux */
346 BIT(31), /* gate */
347 0);
348
349 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
350 "pll-audio-2x", "pll-audio" };
351 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
352 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
353
354 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
355 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
356
357 /* TODO: the parent for most of the USB clocks is not known */
358 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
359 0x0cc, BIT(8), 0);
360 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
361 0x0cc, BIT(9), 0);
362 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
363 0x0cc, BIT(10), 0);
364 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
365 0x0cc, BIT(11), 0);
366 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
367 0x0cc, BIT(16), 0);
368
369 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
370 0x100, BIT(0), 0);
371 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
372 0x100, BIT(1), 0);
373 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
374 0x100, BIT(16), 0);
375 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
376 0x100, BIT(24), 0);
377 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
378 0x100, BIT(26), 0);
379
380 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
381 "pll-gpu", "pll-de" };
382 static const u8 de_table[] = { 0, 2, 3, 5 };
383 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
384 de_parents, de_table,
385 0x104, 0, 4, 24, 3, BIT(31), 0);
386
387 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
388 de_parents, de_table,
389 0x10c, 0, 4, 24, 3, BIT(31), 0);
390
391 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
392 "pll-mipi" };
393 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
394 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
395 lcd_ch0_parents, lcd_ch0_table,
396 0x118, 24, 3, BIT(31),
397 CLK_SET_RATE_PARENT);
398
399 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
400 static const u8 lcd_ch1_table[] = { 0, 2 };
401 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
402 lcd_ch1_parents, lcd_ch1_table,
403 0x12c, 0, 4, 24, 2, BIT(31), 0);
404
405 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
406 "pll-mipi", "pll-ve" };
407 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
408 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
409 csi_sclk_parents, csi_sclk_table,
410 0x134, 16, 4, 24, 3, BIT(31), 0);
411
412 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
413 "osc24M" };
414 static const u8 csi_mclk_table[] = { 0, 3, 5 };
415 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
416 csi_mclk_parents, csi_mclk_table,
417 0x134, 0, 5, 8, 3, BIT(15), 0);
418
419 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
420 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
421
422 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
423 0x140, BIT(31), CLK_SET_RATE_PARENT);
424 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
425 0x144, BIT(31), 0);
426
427 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
428 "pll-ddr" };
429 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
430 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
431
432 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
433 static const u8 dsi_sclk_table[] = { 0, 2 };
434 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
435 dsi_sclk_parents, dsi_sclk_table,
436 0x168, 16, 4, 24, 2, BIT(31), 0);
437
438 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
439 static const u8 dsi_dphy_table[] = { 0, 2 };
440 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
441 dsi_dphy_parents, dsi_dphy_table,
442 0x168, 0, 4, 8, 2, BIT(15), 0);
443
444 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
445 de_parents, de_table,
446 0x180, 0, 4, 24, 3, BIT(31), 0);
447
448 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
449 0x1a0, 0, 3, BIT(31), 0);
450
451 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
452 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
453 0x1b0, 0, 3, 24, 2, BIT(31), 0);
454
455 static struct ccu_common *sun8i_a23_ccu_clks[] = {
456 &pll_cpux_clk.common,
457 &pll_audio_base_clk.common,
458 &pll_video_clk.common,
459 &pll_ve_clk.common,
460 &pll_ddr_clk.common,
461 &pll_periph_clk.common,
462 &pll_gpu_clk.common,
463 &pll_mipi_clk.common,
464 &pll_hsic_clk.common,
465 &pll_de_clk.common,
466 &cpux_clk.common,
467 &axi_clk.common,
468 &ahb1_clk.common,
469 &apb1_clk.common,
470 &apb2_clk.common,
471 &bus_mipi_dsi_clk.common,
472 &bus_dma_clk.common,
473 &bus_mmc0_clk.common,
474 &bus_mmc1_clk.common,
475 &bus_mmc2_clk.common,
476 &bus_nand_clk.common,
477 &bus_dram_clk.common,
478 &bus_hstimer_clk.common,
479 &bus_spi0_clk.common,
480 &bus_spi1_clk.common,
481 &bus_otg_clk.common,
482 &bus_ehci_clk.common,
483 &bus_ohci_clk.common,
484 &bus_ve_clk.common,
485 &bus_lcd_clk.common,
486 &bus_csi_clk.common,
487 &bus_de_fe_clk.common,
488 &bus_de_be_clk.common,
489 &bus_gpu_clk.common,
490 &bus_msgbox_clk.common,
491 &bus_spinlock_clk.common,
492 &bus_drc_clk.common,
493 &bus_codec_clk.common,
494 &bus_pio_clk.common,
495 &bus_i2s0_clk.common,
496 &bus_i2s1_clk.common,
497 &bus_i2c0_clk.common,
498 &bus_i2c1_clk.common,
499 &bus_i2c2_clk.common,
500 &bus_uart0_clk.common,
501 &bus_uart1_clk.common,
502 &bus_uart2_clk.common,
503 &bus_uart3_clk.common,
504 &bus_uart4_clk.common,
505 &nand_clk.common,
506 &mmc0_clk.common,
507 &mmc0_sample_clk.common,
508 &mmc0_output_clk.common,
509 &mmc1_clk.common,
510 &mmc1_sample_clk.common,
511 &mmc1_output_clk.common,
512 &mmc2_clk.common,
513 &mmc2_sample_clk.common,
514 &mmc2_output_clk.common,
515 &spi0_clk.common,
516 &spi1_clk.common,
517 &i2s0_clk.common,
518 &i2s1_clk.common,
519 &usb_phy0_clk.common,
520 &usb_phy1_clk.common,
521 &usb_hsic_clk.common,
522 &usb_hsic_12M_clk.common,
523 &usb_ohci_clk.common,
524 &dram_ve_clk.common,
525 &dram_csi_clk.common,
526 &dram_drc_clk.common,
527 &dram_de_fe_clk.common,
528 &dram_de_be_clk.common,
529 &de_be_clk.common,
530 &de_fe_clk.common,
531 &lcd_ch0_clk.common,
532 &lcd_ch1_clk.common,
533 &csi_sclk_clk.common,
534 &csi_mclk_clk.common,
535 &ve_clk.common,
536 &ac_dig_clk.common,
537 &avs_clk.common,
538 &mbus_clk.common,
539 &dsi_sclk_clk.common,
540 &dsi_dphy_clk.common,
541 &drc_clk.common,
542 &gpu_clk.common,
543 &ats_clk.common,
544 };
545
546 static const struct clk_hw *clk_parent_pll_audio[] = {
547 &pll_audio_base_clk.common.hw
548 };
549
550 /* We hardcode the divider to 1 for now */
551 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
552 clk_parent_pll_audio,
553 1, 1, CLK_SET_RATE_PARENT);
554 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
555 clk_parent_pll_audio,
556 2, 1, CLK_SET_RATE_PARENT);
557 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
558 clk_parent_pll_audio,
559 1, 1, CLK_SET_RATE_PARENT);
560 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
561 clk_parent_pll_audio,
562 1, 2, CLK_SET_RATE_PARENT);
563 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
564 &pll_periph_clk.common.hw,
565 1, 2, 0);
566 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
567 &pll_video_clk.common.hw,
568 1, 2, 0);
569
570 static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
571 .hws = {
572 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
573 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
574 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
575 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
576 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
577 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
578 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
579 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
580 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
581 [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
582 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
583 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
584 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
585 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
586 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
587 [CLK_PLL_DE] = &pll_de_clk.common.hw,
588 [CLK_CPUX] = &cpux_clk.common.hw,
589 [CLK_AXI] = &axi_clk.common.hw,
590 [CLK_AHB1] = &ahb1_clk.common.hw,
591 [CLK_APB1] = &apb1_clk.common.hw,
592 [CLK_APB2] = &apb2_clk.common.hw,
593 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
594 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
595 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
596 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
597 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
598 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
599 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
600 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
601 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
602 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
603 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
604 [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
605 [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
606 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
607 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
608 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
609 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
610 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
611 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
612 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
613 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
614 [CLK_BUS_DRC] = &bus_drc_clk.common.hw,
615 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
616 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
617 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
618 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
619 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
620 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
621 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
622 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
623 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
624 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
625 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
626 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
627 [CLK_NAND] = &nand_clk.common.hw,
628 [CLK_MMC0] = &mmc0_clk.common.hw,
629 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
630 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
631 [CLK_MMC1] = &mmc1_clk.common.hw,
632 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
633 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
634 [CLK_MMC2] = &mmc2_clk.common.hw,
635 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
636 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
637 [CLK_SPI0] = &spi0_clk.common.hw,
638 [CLK_SPI1] = &spi1_clk.common.hw,
639 [CLK_I2S0] = &i2s0_clk.common.hw,
640 [CLK_I2S1] = &i2s1_clk.common.hw,
641 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
642 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
643 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
644 [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
645 [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
646 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
647 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
648 [CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
649 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
650 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
651 [CLK_DE_BE] = &de_be_clk.common.hw,
652 [CLK_DE_FE] = &de_fe_clk.common.hw,
653 [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
654 [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
655 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
656 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
657 [CLK_VE] = &ve_clk.common.hw,
658 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
659 [CLK_AVS] = &avs_clk.common.hw,
660 [CLK_MBUS] = &mbus_clk.common.hw,
661 [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
662 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
663 [CLK_DRC] = &drc_clk.common.hw,
664 [CLK_GPU] = &gpu_clk.common.hw,
665 [CLK_ATS] = &ats_clk.common.hw,
666 },
667 .num = CLK_NUMBER,
668 };
669
670 static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
671 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
672 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
673 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
674
675 [RST_MBUS] = { 0x0fc, BIT(31) },
676
677 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
678 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
679 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
680 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
681 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
682 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
683 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
684 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
685 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
686 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
687 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
688 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
689 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
690
691 [RST_BUS_VE] = { 0x2c4, BIT(0) },
692 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
693 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
694 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
695 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
696 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
697 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
698 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
699 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
700
701 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
702
703 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
704 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
705 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
706
707 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
708 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
709 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
710 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
711 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
712 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
713 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
714 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
715 };
716
717 static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
718 .ccu_clks = sun8i_a23_ccu_clks,
719 .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks),
720
721 .hw_clks = &sun8i_a23_hw_clks,
722
723 .resets = sun8i_a23_ccu_resets,
724 .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
725 };
726
sun8i_a23_ccu_setup(struct device_node * node)727 static void __init sun8i_a23_ccu_setup(struct device_node *node)
728 {
729 void __iomem *reg;
730 u32 val;
731
732 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
733 if (IS_ERR(reg)) {
734 pr_err("%pOF: Could not map the clock registers\n", node);
735 return;
736 }
737
738 /* Force the PLL-Audio-1x divider to 1 */
739 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
740 val &= ~GENMASK(19, 16);
741 writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
742
743 /* Force PLL-MIPI to MIPI mode */
744 val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
745 val &= ~BIT(16);
746 writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
747
748 sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc);
749 }
750 CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",
751 sun8i_a23_ccu_setup);
752
