1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017, Intel Corporation
4 */
5 #include <linux/clk-provider.h>
6 #include <linux/io.h>
7 #include <linux/slab.h>
8 #include "stratix10-clk.h"
9 #include "clk.h"
10
11 #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
12 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
13
socfpga_gate_clk_recalc_rate(struct clk_hw * hwclk,unsigned long parent_rate)14 static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
15 unsigned long parent_rate)
16 {
17 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
18 u32 div = 1, val;
19
20 if (socfpgaclk->fixed_div) {
21 div = socfpgaclk->fixed_div;
22 } else if (socfpgaclk->div_reg) {
23 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
24 val &= GENMASK(socfpgaclk->width - 1, 0);
25 div = (1 << val);
26 }
27 return parent_rate / div;
28 }
29
socfpga_dbg_clk_recalc_rate(struct clk_hw * hwclk,unsigned long parent_rate)30 static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
31 unsigned long parent_rate)
32 {
33 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
34 u32 div = 1, val;
35
36 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
37 val &= GENMASK(socfpgaclk->width - 1, 0);
38 div = (1 << val);
39 div = div ? 4 : 1;
40
41 return parent_rate / div;
42 }
43
socfpga_gate_get_parent(struct clk_hw * hwclk)44 static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
45 {
46 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
47 u32 mask;
48 u8 parent = 0;
49
50 if (socfpgaclk->bypass_reg) {
51 mask = (0x1 << socfpgaclk->bypass_shift);
52 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
53 socfpgaclk->bypass_shift);
54 }
55 return parent;
56 }
57
58 static struct clk_ops gateclk_ops = {
59 .recalc_rate = socfpga_gate_clk_recalc_rate,
60 .get_parent = socfpga_gate_get_parent,
61 };
62
63 static const struct clk_ops dbgclk_ops = {
64 .recalc_rate = socfpga_dbg_clk_recalc_rate,
65 .get_parent = socfpga_gate_get_parent,
66 };
67
s10_register_gate(const char * name,const char * parent_name,const char * const * parent_names,u8 num_parents,unsigned long flags,void __iomem * regbase,unsigned long gate_reg,unsigned long gate_idx,unsigned long div_reg,unsigned long div_offset,u8 div_width,unsigned long bypass_reg,u8 bypass_shift,u8 fixed_div)68 struct clk *s10_register_gate(const char *name, const char *parent_name,
69 const char * const *parent_names,
70 u8 num_parents, unsigned long flags,
71 void __iomem *regbase, unsigned long gate_reg,
72 unsigned long gate_idx, unsigned long div_reg,
73 unsigned long div_offset, u8 div_width,
74 unsigned long bypass_reg, u8 bypass_shift,
75 u8 fixed_div)
76 {
77 struct clk *clk;
78 struct socfpga_gate_clk *socfpga_clk;
79 struct clk_init_data init;
80
81 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
82 if (!socfpga_clk)
83 return NULL;
84
85 socfpga_clk->hw.reg = regbase + gate_reg;
86 socfpga_clk->hw.bit_idx = gate_idx;
87
88 gateclk_ops.enable = clk_gate_ops.enable;
89 gateclk_ops.disable = clk_gate_ops.disable;
90
91 socfpga_clk->fixed_div = fixed_div;
92
93 if (div_reg)
94 socfpga_clk->div_reg = regbase + div_reg;
95 else
96 socfpga_clk->div_reg = NULL;
97
98 socfpga_clk->width = div_width;
99 socfpga_clk->shift = div_offset;
100
101 if (bypass_reg)
102 socfpga_clk->bypass_reg = regbase + bypass_reg;
103 else
104 socfpga_clk->bypass_reg = NULL;
105 socfpga_clk->bypass_shift = bypass_shift;
106
107 if (streq(name, "cs_pdbg_clk"))
108 init.ops = &dbgclk_ops;
109 else
110 init.ops = &gateclk_ops;
111
112 init.name = name;
113 init.flags = flags;
114
115 init.num_parents = num_parents;
116 init.parent_names = parent_names ? parent_names : &parent_name;
117 socfpga_clk->hw.hw.init = &init;
118
119 clk = clk_register(NULL, &socfpga_clk->hw.hw);
120 if (WARN_ON(IS_ERR(clk))) {
121 kfree(socfpga_clk);
122 return NULL;
123 }
124
125 return clk;
126 }
127
