1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8660.h>
19
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26
27 static struct clk_pll pll8 = {
28 .l_reg = 0x3144,
29 .m_reg = 0x3148,
30 .n_reg = 0x314c,
31 .config_reg = 0x3154,
32 .mode_reg = 0x3140,
33 .status_reg = 0x3158,
34 .status_bit = 16,
35 .clkr.hw.init = &(struct clk_init_data){
36 .name = "pll8",
37 .parent_names = (const char *[]){ "pxo" },
38 .num_parents = 1,
39 .ops = &clk_pll_ops,
40 },
41 };
42
43 static struct clk_regmap pll8_vote = {
44 .enable_reg = 0x34c0,
45 .enable_mask = BIT(8),
46 .hw.init = &(struct clk_init_data){
47 .name = "pll8_vote",
48 .parent_names = (const char *[]){ "pll8" },
49 .num_parents = 1,
50 .ops = &clk_pll_vote_ops,
51 },
52 };
53
54 enum {
55 P_PXO,
56 P_PLL8,
57 P_CXO,
58 };
59
60 static const struct parent_map gcc_pxo_pll8_map[] = {
61 { P_PXO, 0 },
62 { P_PLL8, 3 }
63 };
64
65 static const char * const gcc_pxo_pll8[] = {
66 "pxo",
67 "pll8_vote",
68 };
69
70 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
71 { P_PXO, 0 },
72 { P_PLL8, 3 },
73 { P_CXO, 5 }
74 };
75
76 static const char * const gcc_pxo_pll8_cxo[] = {
77 "pxo",
78 "pll8_vote",
79 "cxo",
80 };
81
82 static struct freq_tbl clk_tbl_gsbi_uart[] = {
83 { 1843200, P_PLL8, 2, 6, 625 },
84 { 3686400, P_PLL8, 2, 12, 625 },
85 { 7372800, P_PLL8, 2, 24, 625 },
86 { 14745600, P_PLL8, 2, 48, 625 },
87 { 16000000, P_PLL8, 4, 1, 6 },
88 { 24000000, P_PLL8, 4, 1, 4 },
89 { 32000000, P_PLL8, 4, 1, 3 },
90 { 40000000, P_PLL8, 1, 5, 48 },
91 { 46400000, P_PLL8, 1, 29, 240 },
92 { 48000000, P_PLL8, 4, 1, 2 },
93 { 51200000, P_PLL8, 1, 2, 15 },
94 { 56000000, P_PLL8, 1, 7, 48 },
95 { 58982400, P_PLL8, 1, 96, 625 },
96 { 64000000, P_PLL8, 2, 1, 3 },
97 { }
98 };
99
100 static struct clk_rcg gsbi1_uart_src = {
101 .ns_reg = 0x29d4,
102 .md_reg = 0x29d0,
103 .mn = {
104 .mnctr_en_bit = 8,
105 .mnctr_reset_bit = 7,
106 .mnctr_mode_shift = 5,
107 .n_val_shift = 16,
108 .m_val_shift = 16,
109 .width = 16,
110 },
111 .p = {
112 .pre_div_shift = 3,
113 .pre_div_width = 2,
114 },
115 .s = {
116 .src_sel_shift = 0,
117 .parent_map = gcc_pxo_pll8_map,
118 },
119 .freq_tbl = clk_tbl_gsbi_uart,
120 .clkr = {
121 .enable_reg = 0x29d4,
122 .enable_mask = BIT(11),
123 .hw.init = &(struct clk_init_data){
124 .name = "gsbi1_uart_src",
125 .parent_names = gcc_pxo_pll8,
126 .num_parents = 2,
127 .ops = &clk_rcg_ops,
128 .flags = CLK_SET_PARENT_GATE,
129 },
130 },
131 };
132
133 static struct clk_branch gsbi1_uart_clk = {
134 .halt_reg = 0x2fcc,
135 .halt_bit = 10,
136 .clkr = {
137 .enable_reg = 0x29d4,
138 .enable_mask = BIT(9),
139 .hw.init = &(struct clk_init_data){
140 .name = "gsbi1_uart_clk",
141 .parent_names = (const char *[]){
142 "gsbi1_uart_src",
143 },
144 .num_parents = 1,
145 .ops = &clk_branch_ops,
146 .flags = CLK_SET_RATE_PARENT,
147 },
148 },
149 };
150
151 static struct clk_rcg gsbi2_uart_src = {
152 .ns_reg = 0x29f4,
153 .md_reg = 0x29f0,
154 .mn = {
155 .mnctr_en_bit = 8,
156 .mnctr_reset_bit = 7,
157 .mnctr_mode_shift = 5,
158 .n_val_shift = 16,
159 .m_val_shift = 16,
160 .width = 16,
161 },
162 .p = {
163 .pre_div_shift = 3,
164 .pre_div_width = 2,
165 },
166 .s = {
167 .src_sel_shift = 0,
168 .parent_map = gcc_pxo_pll8_map,
169 },
170 .freq_tbl = clk_tbl_gsbi_uart,
171 .clkr = {
172 .enable_reg = 0x29f4,
173 .enable_mask = BIT(11),
174 .hw.init = &(struct clk_init_data){
175 .name = "gsbi2_uart_src",
176 .parent_names = gcc_pxo_pll8,
177 .num_parents = 2,
178 .ops = &clk_rcg_ops,
179 .flags = CLK_SET_PARENT_GATE,
180 },
181 },
182 };
183
184 static struct clk_branch gsbi2_uart_clk = {
185 .halt_reg = 0x2fcc,
186 .halt_bit = 6,
187 .clkr = {
188 .enable_reg = 0x29f4,
189 .enable_mask = BIT(9),
190 .hw.init = &(struct clk_init_data){
191 .name = "gsbi2_uart_clk",
192 .parent_names = (const char *[]){
193 "gsbi2_uart_src",
194 },
195 .num_parents = 1,
196 .ops = &clk_branch_ops,
197 .flags = CLK_SET_RATE_PARENT,
198 },
199 },
200 };
201
202 static struct clk_rcg gsbi3_uart_src = {
203 .ns_reg = 0x2a14,
204 .md_reg = 0x2a10,
205 .mn = {
206 .mnctr_en_bit = 8,
207 .mnctr_reset_bit = 7,
208 .mnctr_mode_shift = 5,
209 .n_val_shift = 16,
210 .m_val_shift = 16,
211 .width = 16,
212 },
213 .p = {
214 .pre_div_shift = 3,
215 .pre_div_width = 2,
216 },
217 .s = {
218 .src_sel_shift = 0,
219 .parent_map = gcc_pxo_pll8_map,
220 },
221 .freq_tbl = clk_tbl_gsbi_uart,
222 .clkr = {
223 .enable_reg = 0x2a14,
224 .enable_mask = BIT(11),
225 .hw.init = &(struct clk_init_data){
226 .name = "gsbi3_uart_src",
227 .parent_names = gcc_pxo_pll8,
228 .num_parents = 2,
229 .ops = &clk_rcg_ops,
230 .flags = CLK_SET_PARENT_GATE,
231 },
232 },
233 };
234
235 static struct clk_branch gsbi3_uart_clk = {
236 .halt_reg = 0x2fcc,
237 .halt_bit = 2,
238 .clkr = {
239 .enable_reg = 0x2a14,
240 .enable_mask = BIT(9),
241 .hw.init = &(struct clk_init_data){
242 .name = "gsbi3_uart_clk",
243 .parent_names = (const char *[]){
244 "gsbi3_uart_src",
245 },
246 .num_parents = 1,
247 .ops = &clk_branch_ops,
248 .flags = CLK_SET_RATE_PARENT,
249 },
250 },
251 };
252
253 static struct clk_rcg gsbi4_uart_src = {
254 .ns_reg = 0x2a34,
255 .md_reg = 0x2a30,
256 .mn = {
257 .mnctr_en_bit = 8,
258 .mnctr_reset_bit = 7,
259 .mnctr_mode_shift = 5,
260 .n_val_shift = 16,
261 .m_val_shift = 16,
262 .width = 16,
263 },
264 .p = {
265 .pre_div_shift = 3,
266 .pre_div_width = 2,
267 },
268 .s = {
269 .src_sel_shift = 0,
270 .parent_map = gcc_pxo_pll8_map,
271 },
272 .freq_tbl = clk_tbl_gsbi_uart,
273 .clkr = {
274 .enable_reg = 0x2a34,
275 .enable_mask = BIT(11),
276 .hw.init = &(struct clk_init_data){
277 .name = "gsbi4_uart_src",
278 .parent_names = gcc_pxo_pll8,
279 .num_parents = 2,
280 .ops = &clk_rcg_ops,
281 .flags = CLK_SET_PARENT_GATE,
282 },
283 },
284 };
285
286 static struct clk_branch gsbi4_uart_clk = {
287 .halt_reg = 0x2fd0,
288 .halt_bit = 26,
289 .clkr = {
290 .enable_reg = 0x2a34,
291 .enable_mask = BIT(9),
292 .hw.init = &(struct clk_init_data){
293 .name = "gsbi4_uart_clk",
294 .parent_names = (const char *[]){
295 "gsbi4_uart_src",
296 },
297 .num_parents = 1,
298 .ops = &clk_branch_ops,
299 .flags = CLK_SET_RATE_PARENT,
300 },
301 },
302 };
303
304 static struct clk_rcg gsbi5_uart_src = {
305 .ns_reg = 0x2a54,
306 .md_reg = 0x2a50,
307 .mn = {
308 .mnctr_en_bit = 8,
309 .mnctr_reset_bit = 7,
310 .mnctr_mode_shift = 5,
311 .n_val_shift = 16,
312 .m_val_shift = 16,
313 .width = 16,
314 },
315 .p = {
316 .pre_div_shift = 3,
317 .pre_div_width = 2,
318 },
319 .s = {
320 .src_sel_shift = 0,
321 .parent_map = gcc_pxo_pll8_map,
322 },
323 .freq_tbl = clk_tbl_gsbi_uart,
324 .clkr = {
325 .enable_reg = 0x2a54,
326 .enable_mask = BIT(11),
327 .hw.init = &(struct clk_init_data){
328 .name = "gsbi5_uart_src",
329 .parent_names = gcc_pxo_pll8,
330 .num_parents = 2,
331 .ops = &clk_rcg_ops,
332 .flags = CLK_SET_PARENT_GATE,
333 },
334 },
335 };
336
337 static struct clk_branch gsbi5_uart_clk = {
338 .halt_reg = 0x2fd0,
339 .halt_bit = 22,
340 .clkr = {
341 .enable_reg = 0x2a54,
342 .enable_mask = BIT(9),
343 .hw.init = &(struct clk_init_data){
344 .name = "gsbi5_uart_clk",
345 .parent_names = (const char *[]){
346 "gsbi5_uart_src",
347 },
348 .num_parents = 1,
349 .ops = &clk_branch_ops,
350 .flags = CLK_SET_RATE_PARENT,
351 },
352 },
353 };
354
355 static struct clk_rcg gsbi6_uart_src = {
356 .ns_reg = 0x2a74,
357 .md_reg = 0x2a70,
358 .mn = {
359 .mnctr_en_bit = 8,
360 .mnctr_reset_bit = 7,
361 .mnctr_mode_shift = 5,
362 .n_val_shift = 16,
363 .m_val_shift = 16,
364 .width = 16,
365 },
366 .p = {
367 .pre_div_shift = 3,
368 .pre_div_width = 2,
369 },
370 .s = {
371 .src_sel_shift = 0,
372 .parent_map = gcc_pxo_pll8_map,
373 },
374 .freq_tbl = clk_tbl_gsbi_uart,
375 .clkr = {
376 .enable_reg = 0x2a74,
377 .enable_mask = BIT(11),
378 .hw.init = &(struct clk_init_data){
379 .name = "gsbi6_uart_src",
380 .parent_names = gcc_pxo_pll8,
381 .num_parents = 2,
382 .ops = &clk_rcg_ops,
383 .flags = CLK_SET_PARENT_GATE,
384 },
385 },
386 };
387
388 static struct clk_branch gsbi6_uart_clk = {
389 .halt_reg = 0x2fd0,
390 .halt_bit = 18,
391 .clkr = {
392 .enable_reg = 0x2a74,
393 .enable_mask = BIT(9),
394 .hw.init = &(struct clk_init_data){
395 .name = "gsbi6_uart_clk",
396 .parent_names = (const char *[]){
397 "gsbi6_uart_src",
398 },
399 .num_parents = 1,
400 .ops = &clk_branch_ops,
401 .flags = CLK_SET_RATE_PARENT,
402 },
403 },
404 };
405
406 static struct clk_rcg gsbi7_uart_src = {
407 .ns_reg = 0x2a94,
408 .md_reg = 0x2a90,
409 .mn = {
410 .mnctr_en_bit = 8,
411 .mnctr_reset_bit = 7,
412 .mnctr_mode_shift = 5,
413 .n_val_shift = 16,
414 .m_val_shift = 16,
415 .width = 16,
416 },
417 .p = {
418 .pre_div_shift = 3,
419 .pre_div_width = 2,
420 },
421 .s = {
422 .src_sel_shift = 0,
423 .parent_map = gcc_pxo_pll8_map,
424 },
425 .freq_tbl = clk_tbl_gsbi_uart,
426 .clkr = {
427 .enable_reg = 0x2a94,
428 .enable_mask = BIT(11),
429 .hw.init = &(struct clk_init_data){
430 .name = "gsbi7_uart_src",
431 .parent_names = gcc_pxo_pll8,
432 .num_parents = 2,
433 .ops = &clk_rcg_ops,
434 .flags = CLK_SET_PARENT_GATE,
435 },
436 },
437 };
438
439 static struct clk_branch gsbi7_uart_clk = {
440 .halt_reg = 0x2fd0,
441 .halt_bit = 14,
442 .clkr = {
443 .enable_reg = 0x2a94,
444 .enable_mask = BIT(9),
445 .hw.init = &(struct clk_init_data){
446 .name = "gsbi7_uart_clk",
447 .parent_names = (const char *[]){
448 "gsbi7_uart_src",
449 },
450 .num_parents = 1,
451 .ops = &clk_branch_ops,
452 .flags = CLK_SET_RATE_PARENT,
453 },
454 },
455 };
456
457 static struct clk_rcg gsbi8_uart_src = {
458 .ns_reg = 0x2ab4,
459 .md_reg = 0x2ab0,
460 .mn = {
461 .mnctr_en_bit = 8,
462 .mnctr_reset_bit = 7,
463 .mnctr_mode_shift = 5,
464 .n_val_shift = 16,
465 .m_val_shift = 16,
466 .width = 16,
467 },
468 .p = {
469 .pre_div_shift = 3,
470 .pre_div_width = 2,
471 },
472 .s = {
473 .src_sel_shift = 0,
474 .parent_map = gcc_pxo_pll8_map,
475 },
476 .freq_tbl = clk_tbl_gsbi_uart,
477 .clkr = {
478 .enable_reg = 0x2ab4,
479 .enable_mask = BIT(11),
480 .hw.init = &(struct clk_init_data){
481 .name = "gsbi8_uart_src",
482 .parent_names = gcc_pxo_pll8,
483 .num_parents = 2,
484 .ops = &clk_rcg_ops,
485 .flags = CLK_SET_PARENT_GATE,
486 },
487 },
488 };
489
490 static struct clk_branch gsbi8_uart_clk = {
491 .halt_reg = 0x2fd0,
492 .halt_bit = 10,
493 .clkr = {
494 .enable_reg = 0x2ab4,
495 .enable_mask = BIT(9),
496 .hw.init = &(struct clk_init_data){
497 .name = "gsbi8_uart_clk",
498 .parent_names = (const char *[]){ "gsbi8_uart_src" },
499 .num_parents = 1,
500 .ops = &clk_branch_ops,
501 .flags = CLK_SET_RATE_PARENT,
502 },
503 },
504 };
505
506 static struct clk_rcg gsbi9_uart_src = {
507 .ns_reg = 0x2ad4,
508 .md_reg = 0x2ad0,
509 .mn = {
510 .mnctr_en_bit = 8,
511 .mnctr_reset_bit = 7,
512 .mnctr_mode_shift = 5,
513 .n_val_shift = 16,
514 .m_val_shift = 16,
515 .width = 16,
516 },
517 .p = {
518 .pre_div_shift = 3,
519 .pre_div_width = 2,
520 },
521 .s = {
522 .src_sel_shift = 0,
523 .parent_map = gcc_pxo_pll8_map,
524 },
525 .freq_tbl = clk_tbl_gsbi_uart,
526 .clkr = {
527 .enable_reg = 0x2ad4,
528 .enable_mask = BIT(11),
529 .hw.init = &(struct clk_init_data){
530 .name = "gsbi9_uart_src",
531 .parent_names = gcc_pxo_pll8,
532 .num_parents = 2,
533 .ops = &clk_rcg_ops,
534 .flags = CLK_SET_PARENT_GATE,
535 },
536 },
537 };
538
539 static struct clk_branch gsbi9_uart_clk = {
540 .halt_reg = 0x2fd0,
541 .halt_bit = 6,
542 .clkr = {
543 .enable_reg = 0x2ad4,
544 .enable_mask = BIT(9),
545 .hw.init = &(struct clk_init_data){
546 .name = "gsbi9_uart_clk",
547 .parent_names = (const char *[]){ "gsbi9_uart_src" },
548 .num_parents = 1,
549 .ops = &clk_branch_ops,
550 .flags = CLK_SET_RATE_PARENT,
551 },
552 },
553 };
554
555 static struct clk_rcg gsbi10_uart_src = {
556 .ns_reg = 0x2af4,
557 .md_reg = 0x2af0,
558 .mn = {
559 .mnctr_en_bit = 8,
560 .mnctr_reset_bit = 7,
561 .mnctr_mode_shift = 5,
562 .n_val_shift = 16,
563 .m_val_shift = 16,
564 .width = 16,
565 },
566 .p = {
567 .pre_div_shift = 3,
568 .pre_div_width = 2,
569 },
570 .s = {
571 .src_sel_shift = 0,
572 .parent_map = gcc_pxo_pll8_map,
573 },
574 .freq_tbl = clk_tbl_gsbi_uart,
575 .clkr = {
576 .enable_reg = 0x2af4,
577 .enable_mask = BIT(11),
578 .hw.init = &(struct clk_init_data){
579 .name = "gsbi10_uart_src",
580 .parent_names = gcc_pxo_pll8,
581 .num_parents = 2,
582 .ops = &clk_rcg_ops,
583 .flags = CLK_SET_PARENT_GATE,
584 },
585 },
586 };
587
588 static struct clk_branch gsbi10_uart_clk = {
589 .halt_reg = 0x2fd0,
590 .halt_bit = 2,
591 .clkr = {
592 .enable_reg = 0x2af4,
593 .enable_mask = BIT(9),
594 .hw.init = &(struct clk_init_data){
595 .name = "gsbi10_uart_clk",
596 .parent_names = (const char *[]){ "gsbi10_uart_src" },
597 .num_parents = 1,
598 .ops = &clk_branch_ops,
599 .flags = CLK_SET_RATE_PARENT,
600 },
601 },
602 };
603
604 static struct clk_rcg gsbi11_uart_src = {
605 .ns_reg = 0x2b14,
606 .md_reg = 0x2b10,
607 .mn = {
608 .mnctr_en_bit = 8,
609 .mnctr_reset_bit = 7,
610 .mnctr_mode_shift = 5,
611 .n_val_shift = 16,
612 .m_val_shift = 16,
613 .width = 16,
614 },
615 .p = {
616 .pre_div_shift = 3,
617 .pre_div_width = 2,
618 },
619 .s = {
620 .src_sel_shift = 0,
621 .parent_map = gcc_pxo_pll8_map,
622 },
623 .freq_tbl = clk_tbl_gsbi_uart,
624 .clkr = {
625 .enable_reg = 0x2b14,
626 .enable_mask = BIT(11),
627 .hw.init = &(struct clk_init_data){
628 .name = "gsbi11_uart_src",
629 .parent_names = gcc_pxo_pll8,
630 .num_parents = 2,
631 .ops = &clk_rcg_ops,
632 .flags = CLK_SET_PARENT_GATE,
633 },
634 },
635 };
636
637 static struct clk_branch gsbi11_uart_clk = {
638 .halt_reg = 0x2fd4,
639 .halt_bit = 17,
640 .clkr = {
641 .enable_reg = 0x2b14,
642 .enable_mask = BIT(9),
643 .hw.init = &(struct clk_init_data){
644 .name = "gsbi11_uart_clk",
645 .parent_names = (const char *[]){ "gsbi11_uart_src" },
646 .num_parents = 1,
647 .ops = &clk_branch_ops,
648 .flags = CLK_SET_RATE_PARENT,
649 },
650 },
651 };
652
653 static struct clk_rcg gsbi12_uart_src = {
654 .ns_reg = 0x2b34,
655 .md_reg = 0x2b30,
656 .mn = {
657 .mnctr_en_bit = 8,
658 .mnctr_reset_bit = 7,
659 .mnctr_mode_shift = 5,
660 .n_val_shift = 16,
661 .m_val_shift = 16,
662 .width = 16,
663 },
664 .p = {
665 .pre_div_shift = 3,
666 .pre_div_width = 2,
667 },
668 .s = {
669 .src_sel_shift = 0,
670 .parent_map = gcc_pxo_pll8_map,
671 },
672 .freq_tbl = clk_tbl_gsbi_uart,
673 .clkr = {
674 .enable_reg = 0x2b34,
675 .enable_mask = BIT(11),
676 .hw.init = &(struct clk_init_data){
677 .name = "gsbi12_uart_src",
678 .parent_names = gcc_pxo_pll8,
679 .num_parents = 2,
680 .ops = &clk_rcg_ops,
681 .flags = CLK_SET_PARENT_GATE,
682 },
683 },
684 };
685
686 static struct clk_branch gsbi12_uart_clk = {
687 .halt_reg = 0x2fd4,
688 .halt_bit = 13,
689 .clkr = {
690 .enable_reg = 0x2b34,
691 .enable_mask = BIT(9),
692 .hw.init = &(struct clk_init_data){
693 .name = "gsbi12_uart_clk",
694 .parent_names = (const char *[]){ "gsbi12_uart_src" },
695 .num_parents = 1,
696 .ops = &clk_branch_ops,
697 .flags = CLK_SET_RATE_PARENT,
698 },
699 },
700 };
701
702 static struct freq_tbl clk_tbl_gsbi_qup[] = {
703 { 1100000, P_PXO, 1, 2, 49 },
704 { 5400000, P_PXO, 1, 1, 5 },
705 { 10800000, P_PXO, 1, 2, 5 },
706 { 15060000, P_PLL8, 1, 2, 51 },
707 { 24000000, P_PLL8, 4, 1, 4 },
708 { 25600000, P_PLL8, 1, 1, 15 },
709 { 27000000, P_PXO, 1, 0, 0 },
710 { 48000000, P_PLL8, 4, 1, 2 },
711 { 51200000, P_PLL8, 1, 2, 15 },
712 { }
713 };
714
715 static struct clk_rcg gsbi1_qup_src = {
716 .ns_reg = 0x29cc,
717 .md_reg = 0x29c8,
718 .mn = {
719 .mnctr_en_bit = 8,
720 .mnctr_reset_bit = 7,
721 .mnctr_mode_shift = 5,
722 .n_val_shift = 16,
723 .m_val_shift = 16,
724 .width = 8,
725 },
726 .p = {
727 .pre_div_shift = 3,
728 .pre_div_width = 2,
729 },
730 .s = {
731 .src_sel_shift = 0,
732 .parent_map = gcc_pxo_pll8_map,
733 },
734 .freq_tbl = clk_tbl_gsbi_qup,
735 .clkr = {
736 .enable_reg = 0x29cc,
737 .enable_mask = BIT(11),
738 .hw.init = &(struct clk_init_data){
739 .name = "gsbi1_qup_src",
740 .parent_names = gcc_pxo_pll8,
741 .num_parents = 2,
742 .ops = &clk_rcg_ops,
743 .flags = CLK_SET_PARENT_GATE,
744 },
745 },
746 };
747
748 static struct clk_branch gsbi1_qup_clk = {
749 .halt_reg = 0x2fcc,
750 .halt_bit = 9,
751 .clkr = {
752 .enable_reg = 0x29cc,
753 .enable_mask = BIT(9),
754 .hw.init = &(struct clk_init_data){
755 .name = "gsbi1_qup_clk",
756 .parent_names = (const char *[]){ "gsbi1_qup_src" },
757 .num_parents = 1,
758 .ops = &clk_branch_ops,
759 .flags = CLK_SET_RATE_PARENT,
760 },
761 },
762 };
763
764 static struct clk_rcg gsbi2_qup_src = {
765 .ns_reg = 0x29ec,
766 .md_reg = 0x29e8,
767 .mn = {
768 .mnctr_en_bit = 8,
769 .mnctr_reset_bit = 7,
770 .mnctr_mode_shift = 5,
771 .n_val_shift = 16,
772 .m_val_shift = 16,
773 .width = 8,
774 },
775 .p = {
776 .pre_div_shift = 3,
777 .pre_div_width = 2,
778 },
779 .s = {
780 .src_sel_shift = 0,
781 .parent_map = gcc_pxo_pll8_map,
782 },
783 .freq_tbl = clk_tbl_gsbi_qup,
784 .clkr = {
785 .enable_reg = 0x29ec,
786 .enable_mask = BIT(11),
787 .hw.init = &(struct clk_init_data){
788 .name = "gsbi2_qup_src",
789 .parent_names = gcc_pxo_pll8,
790 .num_parents = 2,
791 .ops = &clk_rcg_ops,
792 .flags = CLK_SET_PARENT_GATE,
793 },
794 },
795 };
796
797 static struct clk_branch gsbi2_qup_clk = {
798 .halt_reg = 0x2fcc,
799 .halt_bit = 4,
800 .clkr = {
801 .enable_reg = 0x29ec,
802 .enable_mask = BIT(9),
803 .hw.init = &(struct clk_init_data){
804 .name = "gsbi2_qup_clk",
805 .parent_names = (const char *[]){ "gsbi2_qup_src" },
806 .num_parents = 1,
807 .ops = &clk_branch_ops,
808 .flags = CLK_SET_RATE_PARENT,
809 },
810 },
811 };
812
813 static struct clk_rcg gsbi3_qup_src = {
814 .ns_reg = 0x2a0c,
815 .md_reg = 0x2a08,
816 .mn = {
817 .mnctr_en_bit = 8,
818 .mnctr_reset_bit = 7,
819 .mnctr_mode_shift = 5,
820 .n_val_shift = 16,
821 .m_val_shift = 16,
822 .width = 8,
823 },
824 .p = {
825 .pre_div_shift = 3,
826 .pre_div_width = 2,
827 },
828 .s = {
829 .src_sel_shift = 0,
830 .parent_map = gcc_pxo_pll8_map,
831 },
832 .freq_tbl = clk_tbl_gsbi_qup,
833 .clkr = {
834 .enable_reg = 0x2a0c,
835 .enable_mask = BIT(11),
836 .hw.init = &(struct clk_init_data){
837 .name = "gsbi3_qup_src",
838 .parent_names = gcc_pxo_pll8,
839 .num_parents = 2,
840 .ops = &clk_rcg_ops,
841 .flags = CLK_SET_PARENT_GATE,
842 },
843 },
844 };
845
846 static struct clk_branch gsbi3_qup_clk = {
847 .halt_reg = 0x2fcc,
848 .halt_bit = 0,
849 .clkr = {
850 .enable_reg = 0x2a0c,
851 .enable_mask = BIT(9),
852 .hw.init = &(struct clk_init_data){
853 .name = "gsbi3_qup_clk",
854 .parent_names = (const char *[]){ "gsbi3_qup_src" },
855 .num_parents = 1,
856 .ops = &clk_branch_ops,
857 .flags = CLK_SET_RATE_PARENT,
858 },
859 },
860 };
861
862 static struct clk_rcg gsbi4_qup_src = {
863 .ns_reg = 0x2a2c,
864 .md_reg = 0x2a28,
865 .mn = {
866 .mnctr_en_bit = 8,
867 .mnctr_reset_bit = 7,
868 .mnctr_mode_shift = 5,
869 .n_val_shift = 16,
870 .m_val_shift = 16,
871 .width = 8,
872 },
873 .p = {
874 .pre_div_shift = 3,
875 .pre_div_width = 2,
876 },
877 .s = {
878 .src_sel_shift = 0,
879 .parent_map = gcc_pxo_pll8_map,
880 },
881 .freq_tbl = clk_tbl_gsbi_qup,
882 .clkr = {
883 .enable_reg = 0x2a2c,
884 .enable_mask = BIT(11),
885 .hw.init = &(struct clk_init_data){
886 .name = "gsbi4_qup_src",
887 .parent_names = gcc_pxo_pll8,
888 .num_parents = 2,
889 .ops = &clk_rcg_ops,
890 .flags = CLK_SET_PARENT_GATE,
891 },
892 },
893 };
894
895 static struct clk_branch gsbi4_qup_clk = {
896 .halt_reg = 0x2fd0,
897 .halt_bit = 24,
898 .clkr = {
899 .enable_reg = 0x2a2c,
900 .enable_mask = BIT(9),
901 .hw.init = &(struct clk_init_data){
902 .name = "gsbi4_qup_clk",
903 .parent_names = (const char *[]){ "gsbi4_qup_src" },
904 .num_parents = 1,
905 .ops = &clk_branch_ops,
906 .flags = CLK_SET_RATE_PARENT,
907 },
908 },
909 };
910
911 static struct clk_rcg gsbi5_qup_src = {
912 .ns_reg = 0x2a4c,
913 .md_reg = 0x2a48,
914 .mn = {
915 .mnctr_en_bit = 8,
916 .mnctr_reset_bit = 7,
917 .mnctr_mode_shift = 5,
918 .n_val_shift = 16,
919 .m_val_shift = 16,
920 .width = 8,
921 },
922 .p = {
923 .pre_div_shift = 3,
924 .pre_div_width = 2,
925 },
926 .s = {
927 .src_sel_shift = 0,
928 .parent_map = gcc_pxo_pll8_map,
929 },
930 .freq_tbl = clk_tbl_gsbi_qup,
931 .clkr = {
932 .enable_reg = 0x2a4c,
933 .enable_mask = BIT(11),
934 .hw.init = &(struct clk_init_data){
935 .name = "gsbi5_qup_src",
936 .parent_names = gcc_pxo_pll8,
937 .num_parents = 2,
938 .ops = &clk_rcg_ops,
939 .flags = CLK_SET_PARENT_GATE,
940 },
941 },
942 };
943
944 static struct clk_branch gsbi5_qup_clk = {
945 .halt_reg = 0x2fd0,
946 .halt_bit = 20,
947 .clkr = {
948 .enable_reg = 0x2a4c,
949 .enable_mask = BIT(9),
950 .hw.init = &(struct clk_init_data){
951 .name = "gsbi5_qup_clk",
952 .parent_names = (const char *[]){ "gsbi5_qup_src" },
953 .num_parents = 1,
954 .ops = &clk_branch_ops,
955 .flags = CLK_SET_RATE_PARENT,
956 },
957 },
958 };
959
960 static struct clk_rcg gsbi6_qup_src = {
961 .ns_reg = 0x2a6c,
962 .md_reg = 0x2a68,
963 .mn = {
964 .mnctr_en_bit = 8,
965 .mnctr_reset_bit = 7,
966 .mnctr_mode_shift = 5,
967 .n_val_shift = 16,
968 .m_val_shift = 16,
969 .width = 8,
970 },
971 .p = {
972 .pre_div_shift = 3,
973 .pre_div_width = 2,
974 },
975 .s = {
976 .src_sel_shift = 0,
977 .parent_map = gcc_pxo_pll8_map,
978 },
979 .freq_tbl = clk_tbl_gsbi_qup,
980 .clkr = {
981 .enable_reg = 0x2a6c,
982 .enable_mask = BIT(11),
983 .hw.init = &(struct clk_init_data){
984 .name = "gsbi6_qup_src",
985 .parent_names = gcc_pxo_pll8,
986 .num_parents = 2,
987 .ops = &clk_rcg_ops,
988 .flags = CLK_SET_PARENT_GATE,
989 },
990 },
991 };
992
993 static struct clk_branch gsbi6_qup_clk = {
994 .halt_reg = 0x2fd0,
995 .halt_bit = 16,
996 .clkr = {
997 .enable_reg = 0x2a6c,
998 .enable_mask = BIT(9),
999 .hw.init = &(struct clk_init_data){
1000 .name = "gsbi6_qup_clk",
1001 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1002 .num_parents = 1,
1003 .ops = &clk_branch_ops,
1004 .flags = CLK_SET_RATE_PARENT,
1005 },
1006 },
1007 };
1008
1009 static struct clk_rcg gsbi7_qup_src = {
1010 .ns_reg = 0x2a8c,
1011 .md_reg = 0x2a88,
1012 .mn = {
1013 .mnctr_en_bit = 8,
1014 .mnctr_reset_bit = 7,
1015 .mnctr_mode_shift = 5,
1016 .n_val_shift = 16,
1017 .m_val_shift = 16,
1018 .width = 8,
1019 },
1020 .p = {
1021 .pre_div_shift = 3,
1022 .pre_div_width = 2,
1023 },
1024 .s = {
1025 .src_sel_shift = 0,
1026 .parent_map = gcc_pxo_pll8_map,
1027 },
1028 .freq_tbl = clk_tbl_gsbi_qup,
1029 .clkr = {
1030 .enable_reg = 0x2a8c,
1031 .enable_mask = BIT(11),
1032 .hw.init = &(struct clk_init_data){
1033 .name = "gsbi7_qup_src",
1034 .parent_names = gcc_pxo_pll8,
1035 .num_parents = 2,
1036 .ops = &clk_rcg_ops,
1037 .flags = CLK_SET_PARENT_GATE,
1038 },
1039 },
1040 };
1041
1042 static struct clk_branch gsbi7_qup_clk = {
1043 .halt_reg = 0x2fd0,
1044 .halt_bit = 12,
1045 .clkr = {
1046 .enable_reg = 0x2a8c,
1047 .enable_mask = BIT(9),
1048 .hw.init = &(struct clk_init_data){
1049 .name = "gsbi7_qup_clk",
1050 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1051 .num_parents = 1,
1052 .ops = &clk_branch_ops,
1053 .flags = CLK_SET_RATE_PARENT,
1054 },
1055 },
1056 };
1057
1058 static struct clk_rcg gsbi8_qup_src = {
1059 .ns_reg = 0x2aac,
1060 .md_reg = 0x2aa8,
1061 .mn = {
1062 .mnctr_en_bit = 8,
1063 .mnctr_reset_bit = 7,
1064 .mnctr_mode_shift = 5,
1065 .n_val_shift = 16,
1066 .m_val_shift = 16,
1067 .width = 8,
1068 },
1069 .p = {
1070 .pre_div_shift = 3,
1071 .pre_div_width = 2,
1072 },
1073 .s = {
1074 .src_sel_shift = 0,
1075 .parent_map = gcc_pxo_pll8_map,
1076 },
1077 .freq_tbl = clk_tbl_gsbi_qup,
1078 .clkr = {
1079 .enable_reg = 0x2aac,
1080 .enable_mask = BIT(11),
1081 .hw.init = &(struct clk_init_data){
1082 .name = "gsbi8_qup_src",
1083 .parent_names = gcc_pxo_pll8,
1084 .num_parents = 2,
1085 .ops = &clk_rcg_ops,
1086 .flags = CLK_SET_PARENT_GATE,
1087 },
1088 },
1089 };
1090
1091 static struct clk_branch gsbi8_qup_clk = {
1092 .halt_reg = 0x2fd0,
1093 .halt_bit = 8,
1094 .clkr = {
1095 .enable_reg = 0x2aac,
1096 .enable_mask = BIT(9),
1097 .hw.init = &(struct clk_init_data){
1098 .name = "gsbi8_qup_clk",
1099 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1100 .num_parents = 1,
1101 .ops = &clk_branch_ops,
1102 .flags = CLK_SET_RATE_PARENT,
1103 },
1104 },
1105 };
1106
1107 static struct clk_rcg gsbi9_qup_src = {
1108 .ns_reg = 0x2acc,
1109 .md_reg = 0x2ac8,
1110 .mn = {
1111 .mnctr_en_bit = 8,
1112 .mnctr_reset_bit = 7,
1113 .mnctr_mode_shift = 5,
1114 .n_val_shift = 16,
1115 .m_val_shift = 16,
1116 .width = 8,
1117 },
1118 .p = {
1119 .pre_div_shift = 3,
1120 .pre_div_width = 2,
1121 },
1122 .s = {
1123 .src_sel_shift = 0,
1124 .parent_map = gcc_pxo_pll8_map,
1125 },
1126 .freq_tbl = clk_tbl_gsbi_qup,
1127 .clkr = {
1128 .enable_reg = 0x2acc,
1129 .enable_mask = BIT(11),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "gsbi9_qup_src",
1132 .parent_names = gcc_pxo_pll8,
1133 .num_parents = 2,
1134 .ops = &clk_rcg_ops,
1135 .flags = CLK_SET_PARENT_GATE,
1136 },
1137 },
1138 };
1139
1140 static struct clk_branch gsbi9_qup_clk = {
1141 .halt_reg = 0x2fd0,
1142 .halt_bit = 4,
1143 .clkr = {
1144 .enable_reg = 0x2acc,
1145 .enable_mask = BIT(9),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gsbi9_qup_clk",
1148 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1149 .num_parents = 1,
1150 .ops = &clk_branch_ops,
1151 .flags = CLK_SET_RATE_PARENT,
1152 },
1153 },
1154 };
1155
1156 static struct clk_rcg gsbi10_qup_src = {
1157 .ns_reg = 0x2aec,
1158 .md_reg = 0x2ae8,
1159 .mn = {
1160 .mnctr_en_bit = 8,
1161 .mnctr_reset_bit = 7,
1162 .mnctr_mode_shift = 5,
1163 .n_val_shift = 16,
1164 .m_val_shift = 16,
1165 .width = 8,
1166 },
1167 .p = {
1168 .pre_div_shift = 3,
1169 .pre_div_width = 2,
1170 },
1171 .s = {
1172 .src_sel_shift = 0,
1173 .parent_map = gcc_pxo_pll8_map,
1174 },
1175 .freq_tbl = clk_tbl_gsbi_qup,
1176 .clkr = {
1177 .enable_reg = 0x2aec,
1178 .enable_mask = BIT(11),
1179 .hw.init = &(struct clk_init_data){
1180 .name = "gsbi10_qup_src",
1181 .parent_names = gcc_pxo_pll8,
1182 .num_parents = 2,
1183 .ops = &clk_rcg_ops,
1184 .flags = CLK_SET_PARENT_GATE,
1185 },
1186 },
1187 };
1188
1189 static struct clk_branch gsbi10_qup_clk = {
1190 .halt_reg = 0x2fd0,
1191 .halt_bit = 0,
1192 .clkr = {
1193 .enable_reg = 0x2aec,
1194 .enable_mask = BIT(9),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "gsbi10_qup_clk",
1197 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1198 .num_parents = 1,
1199 .ops = &clk_branch_ops,
1200 .flags = CLK_SET_RATE_PARENT,
1201 },
1202 },
1203 };
1204
1205 static struct clk_rcg gsbi11_qup_src = {
1206 .ns_reg = 0x2b0c,
1207 .md_reg = 0x2b08,
1208 .mn = {
1209 .mnctr_en_bit = 8,
1210 .mnctr_reset_bit = 7,
1211 .mnctr_mode_shift = 5,
1212 .n_val_shift = 16,
1213 .m_val_shift = 16,
1214 .width = 8,
1215 },
1216 .p = {
1217 .pre_div_shift = 3,
1218 .pre_div_width = 2,
1219 },
1220 .s = {
1221 .src_sel_shift = 0,
1222 .parent_map = gcc_pxo_pll8_map,
1223 },
1224 .freq_tbl = clk_tbl_gsbi_qup,
1225 .clkr = {
1226 .enable_reg = 0x2b0c,
1227 .enable_mask = BIT(11),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gsbi11_qup_src",
1230 .parent_names = gcc_pxo_pll8,
1231 .num_parents = 2,
1232 .ops = &clk_rcg_ops,
1233 .flags = CLK_SET_PARENT_GATE,
1234 },
1235 },
1236 };
1237
1238 static struct clk_branch gsbi11_qup_clk = {
1239 .halt_reg = 0x2fd4,
1240 .halt_bit = 15,
1241 .clkr = {
1242 .enable_reg = 0x2b0c,
1243 .enable_mask = BIT(9),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "gsbi11_qup_clk",
1246 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1247 .num_parents = 1,
1248 .ops = &clk_branch_ops,
1249 .flags = CLK_SET_RATE_PARENT,
1250 },
1251 },
1252 };
1253
1254 static struct clk_rcg gsbi12_qup_src = {
1255 .ns_reg = 0x2b2c,
1256 .md_reg = 0x2b28,
1257 .mn = {
1258 .mnctr_en_bit = 8,
1259 .mnctr_reset_bit = 7,
1260 .mnctr_mode_shift = 5,
1261 .n_val_shift = 16,
1262 .m_val_shift = 16,
1263 .width = 8,
1264 },
1265 .p = {
1266 .pre_div_shift = 3,
1267 .pre_div_width = 2,
1268 },
1269 .s = {
1270 .src_sel_shift = 0,
1271 .parent_map = gcc_pxo_pll8_map,
1272 },
1273 .freq_tbl = clk_tbl_gsbi_qup,
1274 .clkr = {
1275 .enable_reg = 0x2b2c,
1276 .enable_mask = BIT(11),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gsbi12_qup_src",
1279 .parent_names = gcc_pxo_pll8,
1280 .num_parents = 2,
1281 .ops = &clk_rcg_ops,
1282 .flags = CLK_SET_PARENT_GATE,
1283 },
1284 },
1285 };
1286
1287 static struct clk_branch gsbi12_qup_clk = {
1288 .halt_reg = 0x2fd4,
1289 .halt_bit = 11,
1290 .clkr = {
1291 .enable_reg = 0x2b2c,
1292 .enable_mask = BIT(9),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "gsbi12_qup_clk",
1295 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1296 .num_parents = 1,
1297 .ops = &clk_branch_ops,
1298 .flags = CLK_SET_RATE_PARENT,
1299 },
1300 },
1301 };
1302
1303 static const struct freq_tbl clk_tbl_gp[] = {
1304 { 9600000, P_CXO, 2, 0, 0 },
1305 { 13500000, P_PXO, 2, 0, 0 },
1306 { 19200000, P_CXO, 1, 0, 0 },
1307 { 27000000, P_PXO, 1, 0, 0 },
1308 { 64000000, P_PLL8, 2, 1, 3 },
1309 { 76800000, P_PLL8, 1, 1, 5 },
1310 { 96000000, P_PLL8, 4, 0, 0 },
1311 { 128000000, P_PLL8, 3, 0, 0 },
1312 { 192000000, P_PLL8, 2, 0, 0 },
1313 { }
1314 };
1315
1316 static struct clk_rcg gp0_src = {
1317 .ns_reg = 0x2d24,
1318 .md_reg = 0x2d00,
1319 .mn = {
1320 .mnctr_en_bit = 8,
1321 .mnctr_reset_bit = 7,
1322 .mnctr_mode_shift = 5,
1323 .n_val_shift = 16,
1324 .m_val_shift = 16,
1325 .width = 8,
1326 },
1327 .p = {
1328 .pre_div_shift = 3,
1329 .pre_div_width = 2,
1330 },
1331 .s = {
1332 .src_sel_shift = 0,
1333 .parent_map = gcc_pxo_pll8_cxo_map,
1334 },
1335 .freq_tbl = clk_tbl_gp,
1336 .clkr = {
1337 .enable_reg = 0x2d24,
1338 .enable_mask = BIT(11),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "gp0_src",
1341 .parent_names = gcc_pxo_pll8_cxo,
1342 .num_parents = 3,
1343 .ops = &clk_rcg_ops,
1344 .flags = CLK_SET_PARENT_GATE,
1345 },
1346 }
1347 };
1348
1349 static struct clk_branch gp0_clk = {
1350 .halt_reg = 0x2fd8,
1351 .halt_bit = 7,
1352 .clkr = {
1353 .enable_reg = 0x2d24,
1354 .enable_mask = BIT(9),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gp0_clk",
1357 .parent_names = (const char *[]){ "gp0_src" },
1358 .num_parents = 1,
1359 .ops = &clk_branch_ops,
1360 .flags = CLK_SET_RATE_PARENT,
1361 },
1362 },
1363 };
1364
1365 static struct clk_rcg gp1_src = {
1366 .ns_reg = 0x2d44,
1367 .md_reg = 0x2d40,
1368 .mn = {
1369 .mnctr_en_bit = 8,
1370 .mnctr_reset_bit = 7,
1371 .mnctr_mode_shift = 5,
1372 .n_val_shift = 16,
1373 .m_val_shift = 16,
1374 .width = 8,
1375 },
1376 .p = {
1377 .pre_div_shift = 3,
1378 .pre_div_width = 2,
1379 },
1380 .s = {
1381 .src_sel_shift = 0,
1382 .parent_map = gcc_pxo_pll8_cxo_map,
1383 },
1384 .freq_tbl = clk_tbl_gp,
1385 .clkr = {
1386 .enable_reg = 0x2d44,
1387 .enable_mask = BIT(11),
1388 .hw.init = &(struct clk_init_data){
1389 .name = "gp1_src",
1390 .parent_names = gcc_pxo_pll8_cxo,
1391 .num_parents = 3,
1392 .ops = &clk_rcg_ops,
1393 .flags = CLK_SET_RATE_GATE,
1394 },
1395 }
1396 };
1397
1398 static struct clk_branch gp1_clk = {
1399 .halt_reg = 0x2fd8,
1400 .halt_bit = 6,
1401 .clkr = {
1402 .enable_reg = 0x2d44,
1403 .enable_mask = BIT(9),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "gp1_clk",
1406 .parent_names = (const char *[]){ "gp1_src" },
1407 .num_parents = 1,
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_SET_RATE_PARENT,
1410 },
1411 },
1412 };
1413
1414 static struct clk_rcg gp2_src = {
1415 .ns_reg = 0x2d64,
1416 .md_reg = 0x2d60,
1417 .mn = {
1418 .mnctr_en_bit = 8,
1419 .mnctr_reset_bit = 7,
1420 .mnctr_mode_shift = 5,
1421 .n_val_shift = 16,
1422 .m_val_shift = 16,
1423 .width = 8,
1424 },
1425 .p = {
1426 .pre_div_shift = 3,
1427 .pre_div_width = 2,
1428 },
1429 .s = {
1430 .src_sel_shift = 0,
1431 .parent_map = gcc_pxo_pll8_cxo_map,
1432 },
1433 .freq_tbl = clk_tbl_gp,
1434 .clkr = {
1435 .enable_reg = 0x2d64,
1436 .enable_mask = BIT(11),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "gp2_src",
1439 .parent_names = gcc_pxo_pll8_cxo,
1440 .num_parents = 3,
1441 .ops = &clk_rcg_ops,
1442 .flags = CLK_SET_RATE_GATE,
1443 },
1444 }
1445 };
1446
1447 static struct clk_branch gp2_clk = {
1448 .halt_reg = 0x2fd8,
1449 .halt_bit = 5,
1450 .clkr = {
1451 .enable_reg = 0x2d64,
1452 .enable_mask = BIT(9),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gp2_clk",
1455 .parent_names = (const char *[]){ "gp2_src" },
1456 .num_parents = 1,
1457 .ops = &clk_branch_ops,
1458 .flags = CLK_SET_RATE_PARENT,
1459 },
1460 },
1461 };
1462
1463 static struct clk_branch pmem_clk = {
1464 .hwcg_reg = 0x25a0,
1465 .hwcg_bit = 6,
1466 .halt_reg = 0x2fc8,
1467 .halt_bit = 20,
1468 .clkr = {
1469 .enable_reg = 0x25a0,
1470 .enable_mask = BIT(4),
1471 .hw.init = &(struct clk_init_data){
1472 .name = "pmem_clk",
1473 .ops = &clk_branch_ops,
1474 },
1475 },
1476 };
1477
1478 static struct clk_rcg prng_src = {
1479 .ns_reg = 0x2e80,
1480 .p = {
1481 .pre_div_shift = 3,
1482 .pre_div_width = 4,
1483 },
1484 .s = {
1485 .src_sel_shift = 0,
1486 .parent_map = gcc_pxo_pll8_map,
1487 },
1488 .clkr.hw = {
1489 .init = &(struct clk_init_data){
1490 .name = "prng_src",
1491 .parent_names = gcc_pxo_pll8,
1492 .num_parents = 2,
1493 .ops = &clk_rcg_ops,
1494 },
1495 },
1496 };
1497
1498 static struct clk_branch prng_clk = {
1499 .halt_reg = 0x2fd8,
1500 .halt_check = BRANCH_HALT_VOTED,
1501 .halt_bit = 10,
1502 .clkr = {
1503 .enable_reg = 0x3080,
1504 .enable_mask = BIT(10),
1505 .hw.init = &(struct clk_init_data){
1506 .name = "prng_clk",
1507 .parent_names = (const char *[]){ "prng_src" },
1508 .num_parents = 1,
1509 .ops = &clk_branch_ops,
1510 },
1511 },
1512 };
1513
1514 static const struct freq_tbl clk_tbl_sdc[] = {
1515 { 144000, P_PXO, 3, 2, 125 },
1516 { 400000, P_PLL8, 4, 1, 240 },
1517 { 16000000, P_PLL8, 4, 1, 6 },
1518 { 17070000, P_PLL8, 1, 2, 45 },
1519 { 20210000, P_PLL8, 1, 1, 19 },
1520 { 24000000, P_PLL8, 4, 1, 4 },
1521 { 48000000, P_PLL8, 4, 1, 2 },
1522 { }
1523 };
1524
1525 static struct clk_rcg sdc1_src = {
1526 .ns_reg = 0x282c,
1527 .md_reg = 0x2828,
1528 .mn = {
1529 .mnctr_en_bit = 8,
1530 .mnctr_reset_bit = 7,
1531 .mnctr_mode_shift = 5,
1532 .n_val_shift = 16,
1533 .m_val_shift = 16,
1534 .width = 8,
1535 },
1536 .p = {
1537 .pre_div_shift = 3,
1538 .pre_div_width = 2,
1539 },
1540 .s = {
1541 .src_sel_shift = 0,
1542 .parent_map = gcc_pxo_pll8_map,
1543 },
1544 .freq_tbl = clk_tbl_sdc,
1545 .clkr = {
1546 .enable_reg = 0x282c,
1547 .enable_mask = BIT(11),
1548 .hw.init = &(struct clk_init_data){
1549 .name = "sdc1_src",
1550 .parent_names = gcc_pxo_pll8,
1551 .num_parents = 2,
1552 .ops = &clk_rcg_ops,
1553 },
1554 }
1555 };
1556
1557 static struct clk_branch sdc1_clk = {
1558 .halt_reg = 0x2fc8,
1559 .halt_bit = 6,
1560 .clkr = {
1561 .enable_reg = 0x282c,
1562 .enable_mask = BIT(9),
1563 .hw.init = &(struct clk_init_data){
1564 .name = "sdc1_clk",
1565 .parent_names = (const char *[]){ "sdc1_src" },
1566 .num_parents = 1,
1567 .ops = &clk_branch_ops,
1568 .flags = CLK_SET_RATE_PARENT,
1569 },
1570 },
1571 };
1572
1573 static struct clk_rcg sdc2_src = {
1574 .ns_reg = 0x284c,
1575 .md_reg = 0x2848,
1576 .mn = {
1577 .mnctr_en_bit = 8,
1578 .mnctr_reset_bit = 7,
1579 .mnctr_mode_shift = 5,
1580 .n_val_shift = 16,
1581 .m_val_shift = 16,
1582 .width = 8,
1583 },
1584 .p = {
1585 .pre_div_shift = 3,
1586 .pre_div_width = 2,
1587 },
1588 .s = {
1589 .src_sel_shift = 0,
1590 .parent_map = gcc_pxo_pll8_map,
1591 },
1592 .freq_tbl = clk_tbl_sdc,
1593 .clkr = {
1594 .enable_reg = 0x284c,
1595 .enable_mask = BIT(11),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "sdc2_src",
1598 .parent_names = gcc_pxo_pll8,
1599 .num_parents = 2,
1600 .ops = &clk_rcg_ops,
1601 },
1602 }
1603 };
1604
1605 static struct clk_branch sdc2_clk = {
1606 .halt_reg = 0x2fc8,
1607 .halt_bit = 5,
1608 .clkr = {
1609 .enable_reg = 0x284c,
1610 .enable_mask = BIT(9),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "sdc2_clk",
1613 .parent_names = (const char *[]){ "sdc2_src" },
1614 .num_parents = 1,
1615 .ops = &clk_branch_ops,
1616 .flags = CLK_SET_RATE_PARENT,
1617 },
1618 },
1619 };
1620
1621 static struct clk_rcg sdc3_src = {
1622 .ns_reg = 0x286c,
1623 .md_reg = 0x2868,
1624 .mn = {
1625 .mnctr_en_bit = 8,
1626 .mnctr_reset_bit = 7,
1627 .mnctr_mode_shift = 5,
1628 .n_val_shift = 16,
1629 .m_val_shift = 16,
1630 .width = 8,
1631 },
1632 .p = {
1633 .pre_div_shift = 3,
1634 .pre_div_width = 2,
1635 },
1636 .s = {
1637 .src_sel_shift = 0,
1638 .parent_map = gcc_pxo_pll8_map,
1639 },
1640 .freq_tbl = clk_tbl_sdc,
1641 .clkr = {
1642 .enable_reg = 0x286c,
1643 .enable_mask = BIT(11),
1644 .hw.init = &(struct clk_init_data){
1645 .name = "sdc3_src",
1646 .parent_names = gcc_pxo_pll8,
1647 .num_parents = 2,
1648 .ops = &clk_rcg_ops,
1649 },
1650 }
1651 };
1652
1653 static struct clk_branch sdc3_clk = {
1654 .halt_reg = 0x2fc8,
1655 .halt_bit = 4,
1656 .clkr = {
1657 .enable_reg = 0x286c,
1658 .enable_mask = BIT(9),
1659 .hw.init = &(struct clk_init_data){
1660 .name = "sdc3_clk",
1661 .parent_names = (const char *[]){ "sdc3_src" },
1662 .num_parents = 1,
1663 .ops = &clk_branch_ops,
1664 .flags = CLK_SET_RATE_PARENT,
1665 },
1666 },
1667 };
1668
1669 static struct clk_rcg sdc4_src = {
1670 .ns_reg = 0x288c,
1671 .md_reg = 0x2888,
1672 .mn = {
1673 .mnctr_en_bit = 8,
1674 .mnctr_reset_bit = 7,
1675 .mnctr_mode_shift = 5,
1676 .n_val_shift = 16,
1677 .m_val_shift = 16,
1678 .width = 8,
1679 },
1680 .p = {
1681 .pre_div_shift = 3,
1682 .pre_div_width = 2,
1683 },
1684 .s = {
1685 .src_sel_shift = 0,
1686 .parent_map = gcc_pxo_pll8_map,
1687 },
1688 .freq_tbl = clk_tbl_sdc,
1689 .clkr = {
1690 .enable_reg = 0x288c,
1691 .enable_mask = BIT(11),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "sdc4_src",
1694 .parent_names = gcc_pxo_pll8,
1695 .num_parents = 2,
1696 .ops = &clk_rcg_ops,
1697 },
1698 }
1699 };
1700
1701 static struct clk_branch sdc4_clk = {
1702 .halt_reg = 0x2fc8,
1703 .halt_bit = 3,
1704 .clkr = {
1705 .enable_reg = 0x288c,
1706 .enable_mask = BIT(9),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "sdc4_clk",
1709 .parent_names = (const char *[]){ "sdc4_src" },
1710 .num_parents = 1,
1711 .ops = &clk_branch_ops,
1712 .flags = CLK_SET_RATE_PARENT,
1713 },
1714 },
1715 };
1716
1717 static struct clk_rcg sdc5_src = {
1718 .ns_reg = 0x28ac,
1719 .md_reg = 0x28a8,
1720 .mn = {
1721 .mnctr_en_bit = 8,
1722 .mnctr_reset_bit = 7,
1723 .mnctr_mode_shift = 5,
1724 .n_val_shift = 16,
1725 .m_val_shift = 16,
1726 .width = 8,
1727 },
1728 .p = {
1729 .pre_div_shift = 3,
1730 .pre_div_width = 2,
1731 },
1732 .s = {
1733 .src_sel_shift = 0,
1734 .parent_map = gcc_pxo_pll8_map,
1735 },
1736 .freq_tbl = clk_tbl_sdc,
1737 .clkr = {
1738 .enable_reg = 0x28ac,
1739 .enable_mask = BIT(11),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "sdc5_src",
1742 .parent_names = gcc_pxo_pll8,
1743 .num_parents = 2,
1744 .ops = &clk_rcg_ops,
1745 },
1746 }
1747 };
1748
1749 static struct clk_branch sdc5_clk = {
1750 .halt_reg = 0x2fc8,
1751 .halt_bit = 2,
1752 .clkr = {
1753 .enable_reg = 0x28ac,
1754 .enable_mask = BIT(9),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "sdc5_clk",
1757 .parent_names = (const char *[]){ "sdc5_src" },
1758 .num_parents = 1,
1759 .ops = &clk_branch_ops,
1760 .flags = CLK_SET_RATE_PARENT,
1761 },
1762 },
1763 };
1764
1765 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1766 { 105000, P_PXO, 1, 1, 256 },
1767 { }
1768 };
1769
1770 static struct clk_rcg tsif_ref_src = {
1771 .ns_reg = 0x2710,
1772 .md_reg = 0x270c,
1773 .mn = {
1774 .mnctr_en_bit = 8,
1775 .mnctr_reset_bit = 7,
1776 .mnctr_mode_shift = 5,
1777 .n_val_shift = 16,
1778 .m_val_shift = 16,
1779 .width = 16,
1780 },
1781 .p = {
1782 .pre_div_shift = 3,
1783 .pre_div_width = 2,
1784 },
1785 .s = {
1786 .src_sel_shift = 0,
1787 .parent_map = gcc_pxo_pll8_map,
1788 },
1789 .freq_tbl = clk_tbl_tsif_ref,
1790 .clkr = {
1791 .enable_reg = 0x2710,
1792 .enable_mask = BIT(11),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "tsif_ref_src",
1795 .parent_names = gcc_pxo_pll8,
1796 .num_parents = 2,
1797 .ops = &clk_rcg_ops,
1798 .flags = CLK_SET_RATE_GATE,
1799 },
1800 }
1801 };
1802
1803 static struct clk_branch tsif_ref_clk = {
1804 .halt_reg = 0x2fd4,
1805 .halt_bit = 5,
1806 .clkr = {
1807 .enable_reg = 0x2710,
1808 .enable_mask = BIT(9),
1809 .hw.init = &(struct clk_init_data){
1810 .name = "tsif_ref_clk",
1811 .parent_names = (const char *[]){ "tsif_ref_src" },
1812 .num_parents = 1,
1813 .ops = &clk_branch_ops,
1814 .flags = CLK_SET_RATE_PARENT,
1815 },
1816 },
1817 };
1818
1819 static const struct freq_tbl clk_tbl_usb[] = {
1820 { 60000000, P_PLL8, 1, 5, 32 },
1821 { }
1822 };
1823
1824 static struct clk_rcg usb_hs1_xcvr_src = {
1825 .ns_reg = 0x290c,
1826 .md_reg = 0x2908,
1827 .mn = {
1828 .mnctr_en_bit = 8,
1829 .mnctr_reset_bit = 7,
1830 .mnctr_mode_shift = 5,
1831 .n_val_shift = 16,
1832 .m_val_shift = 16,
1833 .width = 8,
1834 },
1835 .p = {
1836 .pre_div_shift = 3,
1837 .pre_div_width = 2,
1838 },
1839 .s = {
1840 .src_sel_shift = 0,
1841 .parent_map = gcc_pxo_pll8_map,
1842 },
1843 .freq_tbl = clk_tbl_usb,
1844 .clkr = {
1845 .enable_reg = 0x290c,
1846 .enable_mask = BIT(11),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "usb_hs1_xcvr_src",
1849 .parent_names = gcc_pxo_pll8,
1850 .num_parents = 2,
1851 .ops = &clk_rcg_ops,
1852 .flags = CLK_SET_RATE_GATE,
1853 },
1854 }
1855 };
1856
1857 static struct clk_branch usb_hs1_xcvr_clk = {
1858 .halt_reg = 0x2fc8,
1859 .halt_bit = 0,
1860 .clkr = {
1861 .enable_reg = 0x290c,
1862 .enable_mask = BIT(9),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "usb_hs1_xcvr_clk",
1865 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1866 .num_parents = 1,
1867 .ops = &clk_branch_ops,
1868 .flags = CLK_SET_RATE_PARENT,
1869 },
1870 },
1871 };
1872
1873 static struct clk_rcg usb_fs1_xcvr_fs_src = {
1874 .ns_reg = 0x2968,
1875 .md_reg = 0x2964,
1876 .mn = {
1877 .mnctr_en_bit = 8,
1878 .mnctr_reset_bit = 7,
1879 .mnctr_mode_shift = 5,
1880 .n_val_shift = 16,
1881 .m_val_shift = 16,
1882 .width = 8,
1883 },
1884 .p = {
1885 .pre_div_shift = 3,
1886 .pre_div_width = 2,
1887 },
1888 .s = {
1889 .src_sel_shift = 0,
1890 .parent_map = gcc_pxo_pll8_map,
1891 },
1892 .freq_tbl = clk_tbl_usb,
1893 .clkr = {
1894 .enable_reg = 0x2968,
1895 .enable_mask = BIT(11),
1896 .hw.init = &(struct clk_init_data){
1897 .name = "usb_fs1_xcvr_fs_src",
1898 .parent_names = gcc_pxo_pll8,
1899 .num_parents = 2,
1900 .ops = &clk_rcg_ops,
1901 .flags = CLK_SET_RATE_GATE,
1902 },
1903 }
1904 };
1905
1906 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
1907
1908 static struct clk_branch usb_fs1_xcvr_fs_clk = {
1909 .halt_reg = 0x2fcc,
1910 .halt_bit = 15,
1911 .clkr = {
1912 .enable_reg = 0x2968,
1913 .enable_mask = BIT(9),
1914 .hw.init = &(struct clk_init_data){
1915 .name = "usb_fs1_xcvr_fs_clk",
1916 .parent_names = usb_fs1_xcvr_fs_src_p,
1917 .num_parents = 1,
1918 .ops = &clk_branch_ops,
1919 .flags = CLK_SET_RATE_PARENT,
1920 },
1921 },
1922 };
1923
1924 static struct clk_branch usb_fs1_system_clk = {
1925 .halt_reg = 0x2fcc,
1926 .halt_bit = 16,
1927 .clkr = {
1928 .enable_reg = 0x296c,
1929 .enable_mask = BIT(4),
1930 .hw.init = &(struct clk_init_data){
1931 .parent_names = usb_fs1_xcvr_fs_src_p,
1932 .num_parents = 1,
1933 .name = "usb_fs1_system_clk",
1934 .ops = &clk_branch_ops,
1935 .flags = CLK_SET_RATE_PARENT,
1936 },
1937 },
1938 };
1939
1940 static struct clk_rcg usb_fs2_xcvr_fs_src = {
1941 .ns_reg = 0x2988,
1942 .md_reg = 0x2984,
1943 .mn = {
1944 .mnctr_en_bit = 8,
1945 .mnctr_reset_bit = 7,
1946 .mnctr_mode_shift = 5,
1947 .n_val_shift = 16,
1948 .m_val_shift = 16,
1949 .width = 8,
1950 },
1951 .p = {
1952 .pre_div_shift = 3,
1953 .pre_div_width = 2,
1954 },
1955 .s = {
1956 .src_sel_shift = 0,
1957 .parent_map = gcc_pxo_pll8_map,
1958 },
1959 .freq_tbl = clk_tbl_usb,
1960 .clkr = {
1961 .enable_reg = 0x2988,
1962 .enable_mask = BIT(11),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "usb_fs2_xcvr_fs_src",
1965 .parent_names = gcc_pxo_pll8,
1966 .num_parents = 2,
1967 .ops = &clk_rcg_ops,
1968 .flags = CLK_SET_RATE_GATE,
1969 },
1970 }
1971 };
1972
1973 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
1974
1975 static struct clk_branch usb_fs2_xcvr_fs_clk = {
1976 .halt_reg = 0x2fcc,
1977 .halt_bit = 12,
1978 .clkr = {
1979 .enable_reg = 0x2988,
1980 .enable_mask = BIT(9),
1981 .hw.init = &(struct clk_init_data){
1982 .name = "usb_fs2_xcvr_fs_clk",
1983 .parent_names = usb_fs2_xcvr_fs_src_p,
1984 .num_parents = 1,
1985 .ops = &clk_branch_ops,
1986 .flags = CLK_SET_RATE_PARENT,
1987 },
1988 },
1989 };
1990
1991 static struct clk_branch usb_fs2_system_clk = {
1992 .halt_reg = 0x2fcc,
1993 .halt_bit = 13,
1994 .clkr = {
1995 .enable_reg = 0x298c,
1996 .enable_mask = BIT(4),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "usb_fs2_system_clk",
1999 .parent_names = usb_fs2_xcvr_fs_src_p,
2000 .num_parents = 1,
2001 .ops = &clk_branch_ops,
2002 .flags = CLK_SET_RATE_PARENT,
2003 },
2004 },
2005 };
2006
2007 static struct clk_branch gsbi1_h_clk = {
2008 .halt_reg = 0x2fcc,
2009 .halt_bit = 11,
2010 .clkr = {
2011 .enable_reg = 0x29c0,
2012 .enable_mask = BIT(4),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gsbi1_h_clk",
2015 .ops = &clk_branch_ops,
2016 },
2017 },
2018 };
2019
2020 static struct clk_branch gsbi2_h_clk = {
2021 .halt_reg = 0x2fcc,
2022 .halt_bit = 7,
2023 .clkr = {
2024 .enable_reg = 0x29e0,
2025 .enable_mask = BIT(4),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gsbi2_h_clk",
2028 .ops = &clk_branch_ops,
2029 },
2030 },
2031 };
2032
2033 static struct clk_branch gsbi3_h_clk = {
2034 .halt_reg = 0x2fcc,
2035 .halt_bit = 3,
2036 .clkr = {
2037 .enable_reg = 0x2a00,
2038 .enable_mask = BIT(4),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gsbi3_h_clk",
2041 .ops = &clk_branch_ops,
2042 },
2043 },
2044 };
2045
2046 static struct clk_branch gsbi4_h_clk = {
2047 .halt_reg = 0x2fd0,
2048 .halt_bit = 27,
2049 .clkr = {
2050 .enable_reg = 0x2a20,
2051 .enable_mask = BIT(4),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gsbi4_h_clk",
2054 .ops = &clk_branch_ops,
2055 },
2056 },
2057 };
2058
2059 static struct clk_branch gsbi5_h_clk = {
2060 .halt_reg = 0x2fd0,
2061 .halt_bit = 23,
2062 .clkr = {
2063 .enable_reg = 0x2a40,
2064 .enable_mask = BIT(4),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "gsbi5_h_clk",
2067 .ops = &clk_branch_ops,
2068 },
2069 },
2070 };
2071
2072 static struct clk_branch gsbi6_h_clk = {
2073 .halt_reg = 0x2fd0,
2074 .halt_bit = 19,
2075 .clkr = {
2076 .enable_reg = 0x2a60,
2077 .enable_mask = BIT(4),
2078 .hw.init = &(struct clk_init_data){
2079 .name = "gsbi6_h_clk",
2080 .ops = &clk_branch_ops,
2081 },
2082 },
2083 };
2084
2085 static struct clk_branch gsbi7_h_clk = {
2086 .halt_reg = 0x2fd0,
2087 .halt_bit = 15,
2088 .clkr = {
2089 .enable_reg = 0x2a80,
2090 .enable_mask = BIT(4),
2091 .hw.init = &(struct clk_init_data){
2092 .name = "gsbi7_h_clk",
2093 .ops = &clk_branch_ops,
2094 },
2095 },
2096 };
2097
2098 static struct clk_branch gsbi8_h_clk = {
2099 .halt_reg = 0x2fd0,
2100 .halt_bit = 11,
2101 .clkr = {
2102 .enable_reg = 0x2aa0,
2103 .enable_mask = BIT(4),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gsbi8_h_clk",
2106 .ops = &clk_branch_ops,
2107 },
2108 },
2109 };
2110
2111 static struct clk_branch gsbi9_h_clk = {
2112 .halt_reg = 0x2fd0,
2113 .halt_bit = 7,
2114 .clkr = {
2115 .enable_reg = 0x2ac0,
2116 .enable_mask = BIT(4),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gsbi9_h_clk",
2119 .ops = &clk_branch_ops,
2120 },
2121 },
2122 };
2123
2124 static struct clk_branch gsbi10_h_clk = {
2125 .halt_reg = 0x2fd0,
2126 .halt_bit = 3,
2127 .clkr = {
2128 .enable_reg = 0x2ae0,
2129 .enable_mask = BIT(4),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "gsbi10_h_clk",
2132 .ops = &clk_branch_ops,
2133 },
2134 },
2135 };
2136
2137 static struct clk_branch gsbi11_h_clk = {
2138 .halt_reg = 0x2fd4,
2139 .halt_bit = 18,
2140 .clkr = {
2141 .enable_reg = 0x2b00,
2142 .enable_mask = BIT(4),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gsbi11_h_clk",
2145 .ops = &clk_branch_ops,
2146 },
2147 },
2148 };
2149
2150 static struct clk_branch gsbi12_h_clk = {
2151 .halt_reg = 0x2fd4,
2152 .halt_bit = 14,
2153 .clkr = {
2154 .enable_reg = 0x2b20,
2155 .enable_mask = BIT(4),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "gsbi12_h_clk",
2158 .ops = &clk_branch_ops,
2159 },
2160 },
2161 };
2162
2163 static struct clk_branch tsif_h_clk = {
2164 .halt_reg = 0x2fd4,
2165 .halt_bit = 7,
2166 .clkr = {
2167 .enable_reg = 0x2700,
2168 .enable_mask = BIT(4),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "tsif_h_clk",
2171 .ops = &clk_branch_ops,
2172 },
2173 },
2174 };
2175
2176 static struct clk_branch usb_fs1_h_clk = {
2177 .halt_reg = 0x2fcc,
2178 .halt_bit = 17,
2179 .clkr = {
2180 .enable_reg = 0x2960,
2181 .enable_mask = BIT(4),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "usb_fs1_h_clk",
2184 .ops = &clk_branch_ops,
2185 },
2186 },
2187 };
2188
2189 static struct clk_branch usb_fs2_h_clk = {
2190 .halt_reg = 0x2fcc,
2191 .halt_bit = 14,
2192 .clkr = {
2193 .enable_reg = 0x2980,
2194 .enable_mask = BIT(4),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "usb_fs2_h_clk",
2197 .ops = &clk_branch_ops,
2198 },
2199 },
2200 };
2201
2202 static struct clk_branch usb_hs1_h_clk = {
2203 .halt_reg = 0x2fc8,
2204 .halt_bit = 1,
2205 .clkr = {
2206 .enable_reg = 0x2900,
2207 .enable_mask = BIT(4),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "usb_hs1_h_clk",
2210 .ops = &clk_branch_ops,
2211 },
2212 },
2213 };
2214
2215 static struct clk_branch sdc1_h_clk = {
2216 .halt_reg = 0x2fc8,
2217 .halt_bit = 11,
2218 .clkr = {
2219 .enable_reg = 0x2820,
2220 .enable_mask = BIT(4),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "sdc1_h_clk",
2223 .ops = &clk_branch_ops,
2224 },
2225 },
2226 };
2227
2228 static struct clk_branch sdc2_h_clk = {
2229 .halt_reg = 0x2fc8,
2230 .halt_bit = 10,
2231 .clkr = {
2232 .enable_reg = 0x2840,
2233 .enable_mask = BIT(4),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "sdc2_h_clk",
2236 .ops = &clk_branch_ops,
2237 },
2238 },
2239 };
2240
2241 static struct clk_branch sdc3_h_clk = {
2242 .halt_reg = 0x2fc8,
2243 .halt_bit = 9,
2244 .clkr = {
2245 .enable_reg = 0x2860,
2246 .enable_mask = BIT(4),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "sdc3_h_clk",
2249 .ops = &clk_branch_ops,
2250 },
2251 },
2252 };
2253
2254 static struct clk_branch sdc4_h_clk = {
2255 .halt_reg = 0x2fc8,
2256 .halt_bit = 8,
2257 .clkr = {
2258 .enable_reg = 0x2880,
2259 .enable_mask = BIT(4),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "sdc4_h_clk",
2262 .ops = &clk_branch_ops,
2263 },
2264 },
2265 };
2266
2267 static struct clk_branch sdc5_h_clk = {
2268 .halt_reg = 0x2fc8,
2269 .halt_bit = 7,
2270 .clkr = {
2271 .enable_reg = 0x28a0,
2272 .enable_mask = BIT(4),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "sdc5_h_clk",
2275 .ops = &clk_branch_ops,
2276 },
2277 },
2278 };
2279
2280 static struct clk_branch ebi2_2x_clk = {
2281 .halt_reg = 0x2fcc,
2282 .halt_bit = 18,
2283 .clkr = {
2284 .enable_reg = 0x2660,
2285 .enable_mask = BIT(4),
2286 .hw.init = &(struct clk_init_data){
2287 .name = "ebi2_2x_clk",
2288 .ops = &clk_branch_ops,
2289 },
2290 },
2291 };
2292
2293 static struct clk_branch ebi2_clk = {
2294 .halt_reg = 0x2fcc,
2295 .halt_bit = 19,
2296 .clkr = {
2297 .enable_reg = 0x2664,
2298 .enable_mask = BIT(4),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "ebi2_clk",
2301 .ops = &clk_branch_ops,
2302 },
2303 },
2304 };
2305
2306 static struct clk_branch adm0_clk = {
2307 .halt_reg = 0x2fdc,
2308 .halt_check = BRANCH_HALT_VOTED,
2309 .halt_bit = 14,
2310 .clkr = {
2311 .enable_reg = 0x3080,
2312 .enable_mask = BIT(2),
2313 .hw.init = &(struct clk_init_data){
2314 .name = "adm0_clk",
2315 .ops = &clk_branch_ops,
2316 },
2317 },
2318 };
2319
2320 static struct clk_branch adm0_pbus_clk = {
2321 .halt_reg = 0x2fdc,
2322 .halt_check = BRANCH_HALT_VOTED,
2323 .halt_bit = 13,
2324 .clkr = {
2325 .enable_reg = 0x3080,
2326 .enable_mask = BIT(3),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "adm0_pbus_clk",
2329 .ops = &clk_branch_ops,
2330 },
2331 },
2332 };
2333
2334 static struct clk_branch adm1_clk = {
2335 .halt_reg = 0x2fdc,
2336 .halt_bit = 12,
2337 .halt_check = BRANCH_HALT_VOTED,
2338 .clkr = {
2339 .enable_reg = 0x3080,
2340 .enable_mask = BIT(4),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "adm1_clk",
2343 .ops = &clk_branch_ops,
2344 },
2345 },
2346 };
2347
2348 static struct clk_branch adm1_pbus_clk = {
2349 .halt_reg = 0x2fdc,
2350 .halt_bit = 11,
2351 .halt_check = BRANCH_HALT_VOTED,
2352 .clkr = {
2353 .enable_reg = 0x3080,
2354 .enable_mask = BIT(5),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "adm1_pbus_clk",
2357 .ops = &clk_branch_ops,
2358 },
2359 },
2360 };
2361
2362 static struct clk_branch modem_ahb1_h_clk = {
2363 .halt_reg = 0x2fdc,
2364 .halt_bit = 8,
2365 .halt_check = BRANCH_HALT_VOTED,
2366 .clkr = {
2367 .enable_reg = 0x3080,
2368 .enable_mask = BIT(0),
2369 .hw.init = &(struct clk_init_data){
2370 .name = "modem_ahb1_h_clk",
2371 .ops = &clk_branch_ops,
2372 },
2373 },
2374 };
2375
2376 static struct clk_branch modem_ahb2_h_clk = {
2377 .halt_reg = 0x2fdc,
2378 .halt_bit = 7,
2379 .halt_check = BRANCH_HALT_VOTED,
2380 .clkr = {
2381 .enable_reg = 0x3080,
2382 .enable_mask = BIT(1),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "modem_ahb2_h_clk",
2385 .ops = &clk_branch_ops,
2386 },
2387 },
2388 };
2389
2390 static struct clk_branch pmic_arb0_h_clk = {
2391 .halt_reg = 0x2fd8,
2392 .halt_check = BRANCH_HALT_VOTED,
2393 .halt_bit = 22,
2394 .clkr = {
2395 .enable_reg = 0x3080,
2396 .enable_mask = BIT(8),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "pmic_arb0_h_clk",
2399 .ops = &clk_branch_ops,
2400 },
2401 },
2402 };
2403
2404 static struct clk_branch pmic_arb1_h_clk = {
2405 .halt_reg = 0x2fd8,
2406 .halt_check = BRANCH_HALT_VOTED,
2407 .halt_bit = 21,
2408 .clkr = {
2409 .enable_reg = 0x3080,
2410 .enable_mask = BIT(9),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "pmic_arb1_h_clk",
2413 .ops = &clk_branch_ops,
2414 },
2415 },
2416 };
2417
2418 static struct clk_branch pmic_ssbi2_clk = {
2419 .halt_reg = 0x2fd8,
2420 .halt_check = BRANCH_HALT_VOTED,
2421 .halt_bit = 23,
2422 .clkr = {
2423 .enable_reg = 0x3080,
2424 .enable_mask = BIT(7),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "pmic_ssbi2_clk",
2427 .ops = &clk_branch_ops,
2428 },
2429 },
2430 };
2431
2432 static struct clk_branch rpm_msg_ram_h_clk = {
2433 .hwcg_reg = 0x27e0,
2434 .hwcg_bit = 6,
2435 .halt_reg = 0x2fd8,
2436 .halt_check = BRANCH_HALT_VOTED,
2437 .halt_bit = 12,
2438 .clkr = {
2439 .enable_reg = 0x3080,
2440 .enable_mask = BIT(6),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "rpm_msg_ram_h_clk",
2443 .ops = &clk_branch_ops,
2444 },
2445 },
2446 };
2447
2448 static struct clk_regmap *gcc_msm8660_clks[] = {
2449 [PLL8] = &pll8.clkr,
2450 [PLL8_VOTE] = &pll8_vote,
2451 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2452 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2453 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2454 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2455 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2456 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2457 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2458 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2459 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2460 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2461 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2462 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2463 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2464 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2465 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2466 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2467 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2468 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2469 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2470 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2471 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2472 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2473 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2474 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2475 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2476 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2477 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2478 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2479 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2480 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2481 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2482 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2483 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2484 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2485 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2486 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2487 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2488 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2489 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2490 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2491 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2492 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2493 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2494 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2495 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2496 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2497 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2498 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2499 [GP0_SRC] = &gp0_src.clkr,
2500 [GP0_CLK] = &gp0_clk.clkr,
2501 [GP1_SRC] = &gp1_src.clkr,
2502 [GP1_CLK] = &gp1_clk.clkr,
2503 [GP2_SRC] = &gp2_src.clkr,
2504 [GP2_CLK] = &gp2_clk.clkr,
2505 [PMEM_CLK] = &pmem_clk.clkr,
2506 [PRNG_SRC] = &prng_src.clkr,
2507 [PRNG_CLK] = &prng_clk.clkr,
2508 [SDC1_SRC] = &sdc1_src.clkr,
2509 [SDC1_CLK] = &sdc1_clk.clkr,
2510 [SDC2_SRC] = &sdc2_src.clkr,
2511 [SDC2_CLK] = &sdc2_clk.clkr,
2512 [SDC3_SRC] = &sdc3_src.clkr,
2513 [SDC3_CLK] = &sdc3_clk.clkr,
2514 [SDC4_SRC] = &sdc4_src.clkr,
2515 [SDC4_CLK] = &sdc4_clk.clkr,
2516 [SDC5_SRC] = &sdc5_src.clkr,
2517 [SDC5_CLK] = &sdc5_clk.clkr,
2518 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2519 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2520 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2521 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2522 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2523 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2524 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2525 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2526 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2527 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2528 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2529 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2530 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2531 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2532 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2533 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2534 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2535 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2536 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2537 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2538 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2539 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2540 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2541 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2542 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2543 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2544 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2545 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2546 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2547 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2548 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2549 [EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
2550 [EBI2_CLK] = &ebi2_clk.clkr,
2551 [ADM0_CLK] = &adm0_clk.clkr,
2552 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2553 [ADM1_CLK] = &adm1_clk.clkr,
2554 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2555 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2556 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2557 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2558 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2559 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2560 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2561 };
2562
2563 static const struct qcom_reset_map gcc_msm8660_resets[] = {
2564 [AFAB_CORE_RESET] = { 0x2080, 7 },
2565 [SCSS_SYS_RESET] = { 0x20b4, 1 },
2566 [SCSS_SYS_POR_RESET] = { 0x20b4 },
2567 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2568 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2569 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2570 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2571 [SFAB_CORE_RESET] = { 0x2120, 7 },
2572 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2573 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2574 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2575 [ADM0_C2_RESET] = { 0x220c, 4 },
2576 [ADM0_C1_RESET] = { 0x220c, 3 },
2577 [ADM0_C0_RESET] = { 0x220c, 2 },
2578 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2579 [ADM0_RESET] = { 0x220c },
2580 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2581 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2582 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2583 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2584 [ADM1_C3_RESET] = { 0x226c, 5 },
2585 [ADM1_C2_RESET] = { 0x226c, 4 },
2586 [ADM1_C1_RESET] = { 0x226c, 3 },
2587 [ADM1_C0_RESET] = { 0x226c, 2 },
2588 [ADM1_PBUS_RESET] = { 0x226c, 1 },
2589 [ADM1_RESET] = { 0x226c },
2590 [IMEM0_RESET] = { 0x2280, 7 },
2591 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2592 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2593 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2594 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2595 [DFAB_CORE_RESET] = { 0x24ac, 7 },
2596 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2597 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2598 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2599 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2600 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2601 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2602 [PPSS_PROC_RESET] = { 0x2594, 1 },
2603 [PPSS_RESET] = { 0x2594 },
2604 [PMEM_RESET] = { 0x25a0, 7 },
2605 [DMA_BAM_RESET] = { 0x25c0, 7 },
2606 [SIC_RESET] = { 0x25e0, 7 },
2607 [SPS_TIC_RESET] = { 0x2600, 7 },
2608 [CFBP0_RESET] = { 0x2650, 7 },
2609 [CFBP1_RESET] = { 0x2654, 7 },
2610 [CFBP2_RESET] = { 0x2658, 7 },
2611 [EBI2_RESET] = { 0x2664, 7 },
2612 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2613 [CFPB_MASTER_RESET] = { 0x26a0, 7 },
2614 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2615 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2616 [TSIF_RESET] = { 0x2700, 7 },
2617 [CE1_RESET] = { 0x2720, 7 },
2618 [CE2_RESET] = { 0x2740, 7 },
2619 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2620 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2621 [RPM_PROC_RESET] = { 0x27c0, 7 },
2622 [RPM_BUS_RESET] = { 0x27c4, 7 },
2623 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2624 [PMIC_ARB0_RESET] = { 0x2800, 7 },
2625 [PMIC_ARB1_RESET] = { 0x2804, 7 },
2626 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2627 [SDC1_RESET] = { 0x2830 },
2628 [SDC2_RESET] = { 0x2850 },
2629 [SDC3_RESET] = { 0x2870 },
2630 [SDC4_RESET] = { 0x2890 },
2631 [SDC5_RESET] = { 0x28b0 },
2632 [USB_HS1_RESET] = { 0x2910 },
2633 [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2634 [USB_HS2_RESET] = { 0x2934 },
2635 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2636 [USB_FS1_RESET] = { 0x2974 },
2637 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2638 [USB_FS2_RESET] = { 0x2994 },
2639 [GSBI1_RESET] = { 0x29dc },
2640 [GSBI2_RESET] = { 0x29fc },
2641 [GSBI3_RESET] = { 0x2a1c },
2642 [GSBI4_RESET] = { 0x2a3c },
2643 [GSBI5_RESET] = { 0x2a5c },
2644 [GSBI6_RESET] = { 0x2a7c },
2645 [GSBI7_RESET] = { 0x2a9c },
2646 [GSBI8_RESET] = { 0x2abc },
2647 [GSBI9_RESET] = { 0x2adc },
2648 [GSBI10_RESET] = { 0x2afc },
2649 [GSBI11_RESET] = { 0x2b1c },
2650 [GSBI12_RESET] = { 0x2b3c },
2651 [SPDM_RESET] = { 0x2b6c },
2652 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2653 [TLMM_H_RESET] = { 0x2ba0, 7 },
2654 [TLMM_RESET] = { 0x2ba4, 7 },
2655 [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2656 [MARM_RESET] = { 0x2bd4 },
2657 [MAHB1_RESET] = { 0x2be4, 7 },
2658 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2659 [MAHB2_RESET] = { 0x2c20, 7 },
2660 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2661 [MODEM_RESET] = { 0x2c48 },
2662 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2663 [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2664 [MSS_SLP_RESET] = { 0x2c60, 7 },
2665 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2666 [MSS_WDOG_RESET] = { 0x2c68 },
2667 [TSSC_RESET] = { 0x2ca0, 7 },
2668 [PDM_RESET] = { 0x2cc0, 12 },
2669 [SCSS_CORE0_RESET] = { 0x2d60, 1 },
2670 [SCSS_CORE0_POR_RESET] = { 0x2d60 },
2671 [SCSS_CORE1_RESET] = { 0x2d80, 1 },
2672 [SCSS_CORE1_POR_RESET] = { 0x2d80 },
2673 [MPM_RESET] = { 0x2da4, 1 },
2674 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2675 [EBI1_RESET] = { 0x2dec, 7 },
2676 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2677 [USB_PHY0_RESET] = { 0x2e20 },
2678 [USB_PHY1_RESET] = { 0x2e40 },
2679 [PRNG_RESET] = { 0x2e80, 12 },
2680 };
2681
2682 static const struct regmap_config gcc_msm8660_regmap_config = {
2683 .reg_bits = 32,
2684 .reg_stride = 4,
2685 .val_bits = 32,
2686 .max_register = 0x363c,
2687 .fast_io = true,
2688 };
2689
2690 static const struct qcom_cc_desc gcc_msm8660_desc = {
2691 .config = &gcc_msm8660_regmap_config,
2692 .clks = gcc_msm8660_clks,
2693 .num_clks = ARRAY_SIZE(gcc_msm8660_clks),
2694 .resets = gcc_msm8660_resets,
2695 .num_resets = ARRAY_SIZE(gcc_msm8660_resets),
2696 };
2697
2698 static const struct of_device_id gcc_msm8660_match_table[] = {
2699 { .compatible = "qcom,gcc-msm8660" },
2700 { }
2701 };
2702 MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2703
gcc_msm8660_probe(struct platform_device * pdev)2704 static int gcc_msm8660_probe(struct platform_device *pdev)
2705 {
2706 int ret;
2707 struct device *dev = &pdev->dev;
2708
2709 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
2710 if (ret)
2711 return ret;
2712
2713 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
2714 if (ret)
2715 return ret;
2716
2717 return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2718 }
2719
2720 static struct platform_driver gcc_msm8660_driver = {
2721 .probe = gcc_msm8660_probe,
2722 .driver = {
2723 .name = "gcc-msm8660",
2724 .of_match_table = gcc_msm8660_match_table,
2725 },
2726 };
2727
gcc_msm8660_init(void)2728 static int __init gcc_msm8660_init(void)
2729 {
2730 return platform_driver_register(&gcc_msm8660_driver);
2731 }
2732 core_initcall(gcc_msm8660_init);
2733
gcc_msm8660_exit(void)2734 static void __exit gcc_msm8660_exit(void)
2735 {
2736 platform_driver_unregister(&gcc_msm8660_driver);
2737 }
2738 module_exit(gcc_msm8660_exit);
2739
2740 MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2741 MODULE_LICENSE("GPL v2");
2742 MODULE_ALIAS("platform:gcc-msm8660");
2743
