1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8
9 #include "clk-mtk.h"
10 #include "clk-gate.h"
11
12 #include <dt-bindings/clock/mt8183-clk.h>
13
14 static const struct mtk_gate_regs ipu_adl_cg_regs = {
15 .set_ofs = 0x204,
16 .clr_ofs = 0x204,
17 .sta_ofs = 0x204,
18 };
19
20 #define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
22 &mtk_clk_gate_ops_no_setclr_inv)
23
24 static const struct mtk_gate ipu_adl_clks[] = {
25 GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
26 };
27
clk_mt8183_ipu_adl_probe(struct platform_device * pdev)28 static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
29 {
30 struct clk_onecell_data *clk_data;
31 struct device_node *node = pdev->dev.of_node;
32
33 clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
34
35 mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
36 clk_data);
37
38 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
39 }
40
41 static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
42 { .compatible = "mediatek,mt8183-ipu_adl", },
43 {}
44 };
45
46 static struct platform_driver clk_mt8183_ipu_adl_drv = {
47 .probe = clk_mt8183_ipu_adl_probe,
48 .driver = {
49 .name = "clk-mt8183-ipu_adl",
50 .of_match_table = of_match_clk_mt8183_ipu_adl,
51 },
52 };
53
54 builtin_platform_driver(clk_mt8183_ipu_adl_drv);
55
