1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * Rabeeh Khoury <rabeeh@solid-run.com>
7 *
8 * References:
9 * [1] "Si5351A/B/C Data Sheet"
10 * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
11 * [2] "Manually Generating an Si5351 Register Map"
12 * http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/rational.h>
23 #include <linux/i2c.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_data/si5351.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <asm/div64.h>
30
31 #include "clk-si5351.h"
32
33 struct si5351_driver_data;
34
35 struct si5351_parameters {
36 unsigned long p1;
37 unsigned long p2;
38 unsigned long p3;
39 int valid;
40 };
41
42 struct si5351_hw_data {
43 struct clk_hw hw;
44 struct si5351_driver_data *drvdata;
45 struct si5351_parameters params;
46 unsigned char num;
47 };
48
49 struct si5351_driver_data {
50 enum si5351_variant variant;
51 struct i2c_client *client;
52 struct regmap *regmap;
53
54 struct clk *pxtal;
55 const char *pxtal_name;
56 struct clk_hw xtal;
57 struct clk *pclkin;
58 const char *pclkin_name;
59 struct clk_hw clkin;
60
61 struct si5351_hw_data pll[2];
62 struct si5351_hw_data *msynth;
63 struct si5351_hw_data *clkout;
64 size_t num_clkout;
65 };
66
67 static const char * const si5351_input_names[] = {
68 "xtal", "clkin"
69 };
70 static const char * const si5351_pll_names[] = {
71 "si5351_plla", "si5351_pllb", "si5351_vxco"
72 };
73 static const char * const si5351_msynth_names[] = {
74 "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
75 };
76 static const char * const si5351_clkout_names[] = {
77 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
78 };
79
80 /*
81 * Si5351 i2c regmap
82 */
si5351_reg_read(struct si5351_driver_data * drvdata,u8 reg)83 static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
84 {
85 u32 val;
86 int ret;
87
88 ret = regmap_read(drvdata->regmap, reg, &val);
89 if (ret) {
90 dev_err(&drvdata->client->dev,
91 "unable to read from reg%02x\n", reg);
92 return 0;
93 }
94
95 return (u8)val;
96 }
97
si5351_bulk_read(struct si5351_driver_data * drvdata,u8 reg,u8 count,u8 * buf)98 static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
99 u8 reg, u8 count, u8 *buf)
100 {
101 return regmap_bulk_read(drvdata->regmap, reg, buf, count);
102 }
103
si5351_reg_write(struct si5351_driver_data * drvdata,u8 reg,u8 val)104 static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
105 u8 reg, u8 val)
106 {
107 return regmap_write(drvdata->regmap, reg, val);
108 }
109
si5351_bulk_write(struct si5351_driver_data * drvdata,u8 reg,u8 count,const u8 * buf)110 static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
111 u8 reg, u8 count, const u8 *buf)
112 {
113 return regmap_raw_write(drvdata->regmap, reg, buf, count);
114 }
115
si5351_set_bits(struct si5351_driver_data * drvdata,u8 reg,u8 mask,u8 val)116 static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
117 u8 reg, u8 mask, u8 val)
118 {
119 return regmap_update_bits(drvdata->regmap, reg, mask, val);
120 }
121
si5351_msynth_params_address(int num)122 static inline u8 si5351_msynth_params_address(int num)
123 {
124 if (num > 5)
125 return SI5351_CLK6_PARAMETERS + (num - 6);
126 return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
127 }
128
si5351_read_parameters(struct si5351_driver_data * drvdata,u8 reg,struct si5351_parameters * params)129 static void si5351_read_parameters(struct si5351_driver_data *drvdata,
130 u8 reg, struct si5351_parameters *params)
131 {
132 u8 buf[SI5351_PARAMETERS_LENGTH];
133
134 switch (reg) {
135 case SI5351_CLK6_PARAMETERS:
136 case SI5351_CLK7_PARAMETERS:
137 buf[0] = si5351_reg_read(drvdata, reg);
138 params->p1 = buf[0];
139 params->p2 = 0;
140 params->p3 = 1;
141 break;
142 default:
143 si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
144 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
145 params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
146 params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
147 }
148 params->valid = 1;
149 }
150
si5351_write_parameters(struct si5351_driver_data * drvdata,u8 reg,struct si5351_parameters * params)151 static void si5351_write_parameters(struct si5351_driver_data *drvdata,
152 u8 reg, struct si5351_parameters *params)
153 {
154 u8 buf[SI5351_PARAMETERS_LENGTH];
155
156 switch (reg) {
157 case SI5351_CLK6_PARAMETERS:
158 case SI5351_CLK7_PARAMETERS:
159 buf[0] = params->p1 & 0xff;
160 si5351_reg_write(drvdata, reg, buf[0]);
161 break;
162 default:
163 buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
164 buf[1] = params->p3 & 0xff;
165 /* save rdiv and divby4 */
166 buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
167 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
168 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
169 buf[4] = params->p1 & 0xff;
170 buf[5] = ((params->p3 & 0xf0000) >> 12) |
171 ((params->p2 & 0xf0000) >> 16);
172 buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
173 buf[7] = params->p2 & 0xff;
174 si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
175 }
176 }
177
si5351_regmap_is_volatile(struct device * dev,unsigned int reg)178 static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
179 {
180 switch (reg) {
181 case SI5351_DEVICE_STATUS:
182 case SI5351_INTERRUPT_STATUS:
183 case SI5351_PLL_RESET:
184 return true;
185 }
186 return false;
187 }
188
si5351_regmap_is_writeable(struct device * dev,unsigned int reg)189 static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
190 {
191 /* reserved registers */
192 if (reg >= 4 && reg <= 8)
193 return false;
194 if (reg >= 10 && reg <= 14)
195 return false;
196 if (reg >= 173 && reg <= 176)
197 return false;
198 if (reg >= 178 && reg <= 182)
199 return false;
200 /* read-only */
201 if (reg == SI5351_DEVICE_STATUS)
202 return false;
203 return true;
204 }
205
206 static const struct regmap_config si5351_regmap_config = {
207 .reg_bits = 8,
208 .val_bits = 8,
209 .cache_type = REGCACHE_RBTREE,
210 .max_register = 187,
211 .writeable_reg = si5351_regmap_is_writeable,
212 .volatile_reg = si5351_regmap_is_volatile,
213 };
214
215 /*
216 * Si5351 xtal clock input
217 */
si5351_xtal_prepare(struct clk_hw * hw)218 static int si5351_xtal_prepare(struct clk_hw *hw)
219 {
220 struct si5351_driver_data *drvdata =
221 container_of(hw, struct si5351_driver_data, xtal);
222 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
223 SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
224 return 0;
225 }
226
si5351_xtal_unprepare(struct clk_hw * hw)227 static void si5351_xtal_unprepare(struct clk_hw *hw)
228 {
229 struct si5351_driver_data *drvdata =
230 container_of(hw, struct si5351_driver_data, xtal);
231 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
232 SI5351_XTAL_ENABLE, 0);
233 }
234
235 static const struct clk_ops si5351_xtal_ops = {
236 .prepare = si5351_xtal_prepare,
237 .unprepare = si5351_xtal_unprepare,
238 };
239
240 /*
241 * Si5351 clkin clock input (Si5351C only)
242 */
si5351_clkin_prepare(struct clk_hw * hw)243 static int si5351_clkin_prepare(struct clk_hw *hw)
244 {
245 struct si5351_driver_data *drvdata =
246 container_of(hw, struct si5351_driver_data, clkin);
247 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
248 SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
249 return 0;
250 }
251
si5351_clkin_unprepare(struct clk_hw * hw)252 static void si5351_clkin_unprepare(struct clk_hw *hw)
253 {
254 struct si5351_driver_data *drvdata =
255 container_of(hw, struct si5351_driver_data, clkin);
256 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
257 SI5351_CLKIN_ENABLE, 0);
258 }
259
260 /*
261 * CMOS clock source constraints:
262 * The input frequency range of the PLL is 10Mhz to 40MHz.
263 * If CLKIN is >40MHz, the input divider must be used.
264 */
si5351_clkin_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)265 static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
266 unsigned long parent_rate)
267 {
268 struct si5351_driver_data *drvdata =
269 container_of(hw, struct si5351_driver_data, clkin);
270 unsigned long rate;
271 unsigned char idiv;
272
273 rate = parent_rate;
274 if (parent_rate > 160000000) {
275 idiv = SI5351_CLKIN_DIV_8;
276 rate /= 8;
277 } else if (parent_rate > 80000000) {
278 idiv = SI5351_CLKIN_DIV_4;
279 rate /= 4;
280 } else if (parent_rate > 40000000) {
281 idiv = SI5351_CLKIN_DIV_2;
282 rate /= 2;
283 } else {
284 idiv = SI5351_CLKIN_DIV_1;
285 }
286
287 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
288 SI5351_CLKIN_DIV_MASK, idiv);
289
290 dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
291 __func__, (1 << (idiv >> 6)), rate);
292
293 return rate;
294 }
295
296 static const struct clk_ops si5351_clkin_ops = {
297 .prepare = si5351_clkin_prepare,
298 .unprepare = si5351_clkin_unprepare,
299 .recalc_rate = si5351_clkin_recalc_rate,
300 };
301
302 /*
303 * Si5351 vxco clock input (Si5351B only)
304 */
305
si5351_vxco_prepare(struct clk_hw * hw)306 static int si5351_vxco_prepare(struct clk_hw *hw)
307 {
308 struct si5351_hw_data *hwdata =
309 container_of(hw, struct si5351_hw_data, hw);
310
311 dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
312
313 return 0;
314 }
315
si5351_vxco_unprepare(struct clk_hw * hw)316 static void si5351_vxco_unprepare(struct clk_hw *hw)
317 {
318 }
319
si5351_vxco_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)320 static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
321 unsigned long parent_rate)
322 {
323 return 0;
324 }
325
si5351_vxco_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent)326 static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
327 unsigned long parent)
328 {
329 return 0;
330 }
331
332 static const struct clk_ops si5351_vxco_ops = {
333 .prepare = si5351_vxco_prepare,
334 .unprepare = si5351_vxco_unprepare,
335 .recalc_rate = si5351_vxco_recalc_rate,
336 .set_rate = si5351_vxco_set_rate,
337 };
338
339 /*
340 * Si5351 pll a/b
341 *
342 * Feedback Multisynth Divider Equations [2]
343 *
344 * fVCO = fIN * (a + b/c)
345 *
346 * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
347 * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
348 *
349 * Feedback Multisynth Register Equations
350 *
351 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
352 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
353 * (3) MSNx_P3[19:0] = c
354 *
355 * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
356 *
357 * Using (4) on (1) yields:
358 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
359 * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
360 *
361 * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
362 * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
363 *
364 */
_si5351_pll_reparent(struct si5351_driver_data * drvdata,int num,enum si5351_pll_src parent)365 static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
366 int num, enum si5351_pll_src parent)
367 {
368 u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
369
370 if (parent == SI5351_PLL_SRC_DEFAULT)
371 return 0;
372
373 if (num > 2)
374 return -EINVAL;
375
376 if (drvdata->variant != SI5351_VARIANT_C &&
377 parent != SI5351_PLL_SRC_XTAL)
378 return -EINVAL;
379
380 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
381 (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
382 return 0;
383 }
384
si5351_pll_get_parent(struct clk_hw * hw)385 static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
386 {
387 struct si5351_hw_data *hwdata =
388 container_of(hw, struct si5351_hw_data, hw);
389 u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
390 u8 val;
391
392 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
393
394 return (val & mask) ? 1 : 0;
395 }
396
si5351_pll_set_parent(struct clk_hw * hw,u8 index)397 static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
398 {
399 struct si5351_hw_data *hwdata =
400 container_of(hw, struct si5351_hw_data, hw);
401
402 if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
403 index > 0)
404 return -EPERM;
405
406 if (index > 1)
407 return -EINVAL;
408
409 return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
410 (index == 0) ? SI5351_PLL_SRC_XTAL :
411 SI5351_PLL_SRC_CLKIN);
412 }
413
si5351_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)414 static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
415 unsigned long parent_rate)
416 {
417 struct si5351_hw_data *hwdata =
418 container_of(hw, struct si5351_hw_data, hw);
419 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
420 SI5351_PLLB_PARAMETERS;
421 unsigned long long rate;
422
423 if (!hwdata->params.valid)
424 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
425
426 if (hwdata->params.p3 == 0)
427 return parent_rate;
428
429 /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
430 rate = hwdata->params.p1 * hwdata->params.p3;
431 rate += 512 * hwdata->params.p3;
432 rate += hwdata->params.p2;
433 rate *= parent_rate;
434 do_div(rate, 128 * hwdata->params.p3);
435
436 dev_dbg(&hwdata->drvdata->client->dev,
437 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
438 __func__, clk_hw_get_name(hw),
439 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
440 parent_rate, (unsigned long)rate);
441
442 return (unsigned long)rate;
443 }
444
si5351_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)445 static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
446 unsigned long *parent_rate)
447 {
448 struct si5351_hw_data *hwdata =
449 container_of(hw, struct si5351_hw_data, hw);
450 unsigned long rfrac, denom, a, b, c;
451 unsigned long long lltmp;
452
453 if (rate < SI5351_PLL_VCO_MIN)
454 rate = SI5351_PLL_VCO_MIN;
455 if (rate > SI5351_PLL_VCO_MAX)
456 rate = SI5351_PLL_VCO_MAX;
457
458 /* determine integer part of feedback equation */
459 a = rate / *parent_rate;
460
461 if (a < SI5351_PLL_A_MIN)
462 rate = *parent_rate * SI5351_PLL_A_MIN;
463 if (a > SI5351_PLL_A_MAX)
464 rate = *parent_rate * SI5351_PLL_A_MAX;
465
466 /* find best approximation for b/c = fVCO mod fIN */
467 denom = 1000 * 1000;
468 lltmp = rate % (*parent_rate);
469 lltmp *= denom;
470 do_div(lltmp, *parent_rate);
471 rfrac = (unsigned long)lltmp;
472
473 b = 0;
474 c = 1;
475 if (rfrac)
476 rational_best_approximation(rfrac, denom,
477 SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
478
479 /* calculate parameters */
480 hwdata->params.p3 = c;
481 hwdata->params.p2 = (128 * b) % c;
482 hwdata->params.p1 = 128 * a;
483 hwdata->params.p1 += (128 * b / c);
484 hwdata->params.p1 -= 512;
485
486 /* recalculate rate by fIN * (a + b/c) */
487 lltmp = *parent_rate;
488 lltmp *= b;
489 do_div(lltmp, c);
490
491 rate = (unsigned long)lltmp;
492 rate += *parent_rate * a;
493
494 dev_dbg(&hwdata->drvdata->client->dev,
495 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
496 __func__, clk_hw_get_name(hw), a, b, c,
497 *parent_rate, rate);
498
499 return rate;
500 }
501
si5351_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)502 static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
503 unsigned long parent_rate)
504 {
505 struct si5351_hw_data *hwdata =
506 container_of(hw, struct si5351_hw_data, hw);
507 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
508 SI5351_PLLB_PARAMETERS;
509
510 /* write multisynth parameters */
511 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
512
513 /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
514 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
515 SI5351_CLK_INTEGER_MODE,
516 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
517
518 /* Do a pll soft reset on the affected pll */
519 si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
520 hwdata->num == 0 ? SI5351_PLL_RESET_A :
521 SI5351_PLL_RESET_B);
522
523 dev_dbg(&hwdata->drvdata->client->dev,
524 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
525 __func__, clk_hw_get_name(hw),
526 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
527 parent_rate, rate);
528
529 return 0;
530 }
531
532 static const struct clk_ops si5351_pll_ops = {
533 .set_parent = si5351_pll_set_parent,
534 .get_parent = si5351_pll_get_parent,
535 .recalc_rate = si5351_pll_recalc_rate,
536 .round_rate = si5351_pll_round_rate,
537 .set_rate = si5351_pll_set_rate,
538 };
539
540 /*
541 * Si5351 multisync divider
542 *
543 * for fOUT <= 150 MHz:
544 *
545 * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
546 *
547 * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
548 * fIN = fVCO0, fVCO1
549 *
550 * Output Clock Multisynth Register Equations
551 *
552 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
553 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
554 * MSx_P3[19:0] = c
555 *
556 * MS[6,7] are integer (P1) divide only, P1 = divide value,
557 * P2 and P3 are not applicable
558 *
559 * for 150MHz < fOUT <= 160MHz:
560 *
561 * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
562 */
_si5351_msynth_reparent(struct si5351_driver_data * drvdata,int num,enum si5351_multisynth_src parent)563 static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
564 int num, enum si5351_multisynth_src parent)
565 {
566 if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
567 return 0;
568
569 if (num > 8)
570 return -EINVAL;
571
572 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
573 (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
574 SI5351_CLK_PLL_SELECT);
575 return 0;
576 }
577
si5351_msynth_get_parent(struct clk_hw * hw)578 static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
579 {
580 struct si5351_hw_data *hwdata =
581 container_of(hw, struct si5351_hw_data, hw);
582 u8 val;
583
584 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
585
586 return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
587 }
588
si5351_msynth_set_parent(struct clk_hw * hw,u8 index)589 static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
590 {
591 struct si5351_hw_data *hwdata =
592 container_of(hw, struct si5351_hw_data, hw);
593
594 return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
595 (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
596 SI5351_MULTISYNTH_SRC_VCO1);
597 }
598
si5351_msynth_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)599 static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
600 unsigned long parent_rate)
601 {
602 struct si5351_hw_data *hwdata =
603 container_of(hw, struct si5351_hw_data, hw);
604 u8 reg = si5351_msynth_params_address(hwdata->num);
605 unsigned long long rate;
606 unsigned long m;
607
608 if (!hwdata->params.valid)
609 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
610
611 /*
612 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
613 * multisync6-7: fOUT = fIN / P1
614 */
615 rate = parent_rate;
616 if (hwdata->num > 5) {
617 m = hwdata->params.p1;
618 } else if (hwdata->params.p3 == 0) {
619 return parent_rate;
620 } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
621 SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
622 m = 4;
623 } else {
624 rate *= 128 * hwdata->params.p3;
625 m = hwdata->params.p1 * hwdata->params.p3;
626 m += hwdata->params.p2;
627 m += 512 * hwdata->params.p3;
628 }
629
630 if (m == 0)
631 return 0;
632 do_div(rate, m);
633
634 dev_dbg(&hwdata->drvdata->client->dev,
635 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
636 __func__, clk_hw_get_name(hw),
637 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
638 m, parent_rate, (unsigned long)rate);
639
640 return (unsigned long)rate;
641 }
642
si5351_msynth_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)643 static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
644 unsigned long *parent_rate)
645 {
646 struct si5351_hw_data *hwdata =
647 container_of(hw, struct si5351_hw_data, hw);
648 unsigned long long lltmp;
649 unsigned long a, b, c;
650 int divby4;
651
652 /* multisync6-7 can only handle freqencies < 150MHz */
653 if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
654 rate = SI5351_MULTISYNTH67_MAX_FREQ;
655
656 /* multisync frequency is 1MHz .. 160MHz */
657 if (rate > SI5351_MULTISYNTH_MAX_FREQ)
658 rate = SI5351_MULTISYNTH_MAX_FREQ;
659 if (rate < SI5351_MULTISYNTH_MIN_FREQ)
660 rate = SI5351_MULTISYNTH_MIN_FREQ;
661
662 divby4 = 0;
663 if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
664 divby4 = 1;
665
666 /* multisync can set pll */
667 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
668 /*
669 * find largest integer divider for max
670 * vco frequency and given target rate
671 */
672 if (divby4 == 0) {
673 lltmp = SI5351_PLL_VCO_MAX;
674 do_div(lltmp, rate);
675 a = (unsigned long)lltmp;
676 } else
677 a = 4;
678
679 b = 0;
680 c = 1;
681
682 *parent_rate = a * rate;
683 } else if (hwdata->num >= 6) {
684 /* determine the closest integer divider */
685 a = DIV_ROUND_CLOSEST(*parent_rate, rate);
686 if (a < SI5351_MULTISYNTH_A_MIN)
687 a = SI5351_MULTISYNTH_A_MIN;
688 if (a > SI5351_MULTISYNTH67_A_MAX)
689 a = SI5351_MULTISYNTH67_A_MAX;
690
691 b = 0;
692 c = 1;
693 } else {
694 unsigned long rfrac, denom;
695
696 /* disable divby4 */
697 if (divby4) {
698 rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
699 divby4 = 0;
700 }
701
702 /* determine integer part of divider equation */
703 a = *parent_rate / rate;
704 if (a < SI5351_MULTISYNTH_A_MIN)
705 a = SI5351_MULTISYNTH_A_MIN;
706 if (a > SI5351_MULTISYNTH_A_MAX)
707 a = SI5351_MULTISYNTH_A_MAX;
708
709 /* find best approximation for b/c = fVCO mod fOUT */
710 denom = 1000 * 1000;
711 lltmp = (*parent_rate) % rate;
712 lltmp *= denom;
713 do_div(lltmp, rate);
714 rfrac = (unsigned long)lltmp;
715
716 b = 0;
717 c = 1;
718 if (rfrac)
719 rational_best_approximation(rfrac, denom,
720 SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
721 &b, &c);
722 }
723
724 /* recalculate rate by fOUT = fIN / (a + b/c) */
725 lltmp = *parent_rate;
726 lltmp *= c;
727 do_div(lltmp, a * c + b);
728 rate = (unsigned long)lltmp;
729
730 /* calculate parameters */
731 if (divby4) {
732 hwdata->params.p3 = 1;
733 hwdata->params.p2 = 0;
734 hwdata->params.p1 = 0;
735 } else if (hwdata->num >= 6) {
736 hwdata->params.p3 = 0;
737 hwdata->params.p2 = 0;
738 hwdata->params.p1 = a;
739 } else {
740 hwdata->params.p3 = c;
741 hwdata->params.p2 = (128 * b) % c;
742 hwdata->params.p1 = 128 * a;
743 hwdata->params.p1 += (128 * b / c);
744 hwdata->params.p1 -= 512;
745 }
746
747 dev_dbg(&hwdata->drvdata->client->dev,
748 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
749 __func__, clk_hw_get_name(hw), a, b, c, divby4,
750 *parent_rate, rate);
751
752 return rate;
753 }
754
si5351_msynth_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)755 static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
756 unsigned long parent_rate)
757 {
758 struct si5351_hw_data *hwdata =
759 container_of(hw, struct si5351_hw_data, hw);
760 u8 reg = si5351_msynth_params_address(hwdata->num);
761 int divby4 = 0;
762
763 /* write multisynth parameters */
764 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
765
766 if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
767 divby4 = 1;
768
769 /* enable/disable integer mode and divby4 on multisynth0-5 */
770 if (hwdata->num < 6) {
771 si5351_set_bits(hwdata->drvdata, reg + 2,
772 SI5351_OUTPUT_CLK_DIVBY4,
773 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
774 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
775 SI5351_CLK_INTEGER_MODE,
776 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
777 }
778
779 dev_dbg(&hwdata->drvdata->client->dev,
780 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
781 __func__, clk_hw_get_name(hw),
782 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
783 divby4, parent_rate, rate);
784
785 return 0;
786 }
787
788 static const struct clk_ops si5351_msynth_ops = {
789 .set_parent = si5351_msynth_set_parent,
790 .get_parent = si5351_msynth_get_parent,
791 .recalc_rate = si5351_msynth_recalc_rate,
792 .round_rate = si5351_msynth_round_rate,
793 .set_rate = si5351_msynth_set_rate,
794 };
795
796 /*
797 * Si5351 clkout divider
798 */
_si5351_clkout_reparent(struct si5351_driver_data * drvdata,int num,enum si5351_clkout_src parent)799 static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
800 int num, enum si5351_clkout_src parent)
801 {
802 u8 val;
803
804 if (num > 8)
805 return -EINVAL;
806
807 switch (parent) {
808 case SI5351_CLKOUT_SRC_MSYNTH_N:
809 val = SI5351_CLK_INPUT_MULTISYNTH_N;
810 break;
811 case SI5351_CLKOUT_SRC_MSYNTH_0_4:
812 /* clk0/clk4 can only connect to its own multisync */
813 if (num == 0 || num == 4)
814 val = SI5351_CLK_INPUT_MULTISYNTH_N;
815 else
816 val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
817 break;
818 case SI5351_CLKOUT_SRC_XTAL:
819 val = SI5351_CLK_INPUT_XTAL;
820 break;
821 case SI5351_CLKOUT_SRC_CLKIN:
822 if (drvdata->variant != SI5351_VARIANT_C)
823 return -EINVAL;
824
825 val = SI5351_CLK_INPUT_CLKIN;
826 break;
827 default:
828 return 0;
829 }
830
831 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
832 SI5351_CLK_INPUT_MASK, val);
833 return 0;
834 }
835
_si5351_clkout_set_drive_strength(struct si5351_driver_data * drvdata,int num,enum si5351_drive_strength drive)836 static int _si5351_clkout_set_drive_strength(
837 struct si5351_driver_data *drvdata, int num,
838 enum si5351_drive_strength drive)
839 {
840 u8 mask;
841
842 if (num > 8)
843 return -EINVAL;
844
845 switch (drive) {
846 case SI5351_DRIVE_2MA:
847 mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
848 break;
849 case SI5351_DRIVE_4MA:
850 mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
851 break;
852 case SI5351_DRIVE_6MA:
853 mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
854 break;
855 case SI5351_DRIVE_8MA:
856 mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
857 break;
858 default:
859 return 0;
860 }
861
862 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
863 SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
864 return 0;
865 }
866
_si5351_clkout_set_disable_state(struct si5351_driver_data * drvdata,int num,enum si5351_disable_state state)867 static int _si5351_clkout_set_disable_state(
868 struct si5351_driver_data *drvdata, int num,
869 enum si5351_disable_state state)
870 {
871 u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
872 SI5351_CLK7_4_DISABLE_STATE;
873 u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
874 u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
875 u8 val;
876
877 if (num > 8)
878 return -EINVAL;
879
880 switch (state) {
881 case SI5351_DISABLE_LOW:
882 val = SI5351_CLK_DISABLE_STATE_LOW;
883 break;
884 case SI5351_DISABLE_HIGH:
885 val = SI5351_CLK_DISABLE_STATE_HIGH;
886 break;
887 case SI5351_DISABLE_FLOATING:
888 val = SI5351_CLK_DISABLE_STATE_FLOAT;
889 break;
890 case SI5351_DISABLE_NEVER:
891 val = SI5351_CLK_DISABLE_STATE_NEVER;
892 break;
893 default:
894 return 0;
895 }
896
897 si5351_set_bits(drvdata, reg, mask, val << shift);
898
899 return 0;
900 }
901
_si5351_clkout_reset_pll(struct si5351_driver_data * drvdata,int num)902 static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
903 {
904 u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
905
906 switch (val & SI5351_CLK_INPUT_MASK) {
907 case SI5351_CLK_INPUT_XTAL:
908 case SI5351_CLK_INPUT_CLKIN:
909 return; /* pll not used, no need to reset */
910 }
911
912 si5351_reg_write(drvdata, SI5351_PLL_RESET,
913 val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
914 SI5351_PLL_RESET_A);
915
916 dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
917 __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
918 (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
919 }
920
si5351_clkout_prepare(struct clk_hw * hw)921 static int si5351_clkout_prepare(struct clk_hw *hw)
922 {
923 struct si5351_hw_data *hwdata =
924 container_of(hw, struct si5351_hw_data, hw);
925 struct si5351_platform_data *pdata =
926 hwdata->drvdata->client->dev.platform_data;
927
928 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
929 SI5351_CLK_POWERDOWN, 0);
930
931 /*
932 * Do a pll soft reset on the parent pll -- needed to get a
933 * deterministic phase relationship between the output clocks.
934 */
935 if (pdata->clkout[hwdata->num].pll_reset)
936 _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
937
938 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
939 (1 << hwdata->num), 0);
940 return 0;
941 }
942
si5351_clkout_unprepare(struct clk_hw * hw)943 static void si5351_clkout_unprepare(struct clk_hw *hw)
944 {
945 struct si5351_hw_data *hwdata =
946 container_of(hw, struct si5351_hw_data, hw);
947
948 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
949 SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
950 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
951 (1 << hwdata->num), (1 << hwdata->num));
952 }
953
si5351_clkout_get_parent(struct clk_hw * hw)954 static u8 si5351_clkout_get_parent(struct clk_hw *hw)
955 {
956 struct si5351_hw_data *hwdata =
957 container_of(hw, struct si5351_hw_data, hw);
958 int index = 0;
959 unsigned char val;
960
961 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
962 switch (val & SI5351_CLK_INPUT_MASK) {
963 case SI5351_CLK_INPUT_MULTISYNTH_N:
964 index = 0;
965 break;
966 case SI5351_CLK_INPUT_MULTISYNTH_0_4:
967 index = 1;
968 break;
969 case SI5351_CLK_INPUT_XTAL:
970 index = 2;
971 break;
972 case SI5351_CLK_INPUT_CLKIN:
973 index = 3;
974 break;
975 }
976
977 return index;
978 }
979
si5351_clkout_set_parent(struct clk_hw * hw,u8 index)980 static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
981 {
982 struct si5351_hw_data *hwdata =
983 container_of(hw, struct si5351_hw_data, hw);
984 enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
985
986 switch (index) {
987 case 0:
988 parent = SI5351_CLKOUT_SRC_MSYNTH_N;
989 break;
990 case 1:
991 parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
992 break;
993 case 2:
994 parent = SI5351_CLKOUT_SRC_XTAL;
995 break;
996 case 3:
997 parent = SI5351_CLKOUT_SRC_CLKIN;
998 break;
999 }
1000
1001 return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
1002 }
1003
si5351_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1004 static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
1005 unsigned long parent_rate)
1006 {
1007 struct si5351_hw_data *hwdata =
1008 container_of(hw, struct si5351_hw_data, hw);
1009 unsigned char reg;
1010 unsigned char rdiv;
1011
1012 if (hwdata->num <= 5)
1013 reg = si5351_msynth_params_address(hwdata->num) + 2;
1014 else
1015 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
1016
1017 rdiv = si5351_reg_read(hwdata->drvdata, reg);
1018 if (hwdata->num == 6) {
1019 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
1020 } else {
1021 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
1022 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
1023 }
1024
1025 return parent_rate >> rdiv;
1026 }
1027
si5351_clkout_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1028 static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
1029 unsigned long *parent_rate)
1030 {
1031 struct si5351_hw_data *hwdata =
1032 container_of(hw, struct si5351_hw_data, hw);
1033 unsigned char rdiv;
1034
1035 /* clkout6/7 can only handle output freqencies < 150MHz */
1036 if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
1037 rate = SI5351_CLKOUT67_MAX_FREQ;
1038
1039 /* clkout freqency is 8kHz - 160MHz */
1040 if (rate > SI5351_CLKOUT_MAX_FREQ)
1041 rate = SI5351_CLKOUT_MAX_FREQ;
1042 if (rate < SI5351_CLKOUT_MIN_FREQ)
1043 rate = SI5351_CLKOUT_MIN_FREQ;
1044
1045 /* request frequency if multisync master */
1046 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
1047 /* use r divider for frequencies below 1MHz */
1048 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1049 while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
1050 rdiv < SI5351_OUTPUT_CLK_DIV_128) {
1051 rdiv += 1;
1052 rate *= 2;
1053 }
1054 *parent_rate = rate;
1055 } else {
1056 unsigned long new_rate, new_err, err;
1057
1058 /* round to closed rdiv */
1059 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1060 new_rate = *parent_rate;
1061 err = abs(new_rate - rate);
1062 do {
1063 new_rate >>= 1;
1064 new_err = abs(new_rate - rate);
1065 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1066 break;
1067 rdiv++;
1068 err = new_err;
1069 } while (1);
1070 }
1071 rate = *parent_rate >> rdiv;
1072
1073 dev_dbg(&hwdata->drvdata->client->dev,
1074 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1075 __func__, clk_hw_get_name(hw), (1 << rdiv),
1076 *parent_rate, rate);
1077
1078 return rate;
1079 }
1080
si5351_clkout_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1081 static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1082 unsigned long parent_rate)
1083 {
1084 struct si5351_hw_data *hwdata =
1085 container_of(hw, struct si5351_hw_data, hw);
1086 unsigned long new_rate, new_err, err;
1087 unsigned char rdiv;
1088
1089 /* round to closed rdiv */
1090 rdiv = SI5351_OUTPUT_CLK_DIV_1;
1091 new_rate = parent_rate;
1092 err = abs(new_rate - rate);
1093 do {
1094 new_rate >>= 1;
1095 new_err = abs(new_rate - rate);
1096 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1097 break;
1098 rdiv++;
1099 err = new_err;
1100 } while (1);
1101
1102 /* write output divider */
1103 switch (hwdata->num) {
1104 case 6:
1105 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1106 SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
1107 break;
1108 case 7:
1109 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1110 SI5351_OUTPUT_CLK_DIV_MASK,
1111 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1112 break;
1113 default:
1114 si5351_set_bits(hwdata->drvdata,
1115 si5351_msynth_params_address(hwdata->num) + 2,
1116 SI5351_OUTPUT_CLK_DIV_MASK,
1117 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1118 }
1119
1120 /* powerup clkout */
1121 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1122 SI5351_CLK_POWERDOWN, 0);
1123
1124 dev_dbg(&hwdata->drvdata->client->dev,
1125 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1126 __func__, clk_hw_get_name(hw), (1 << rdiv),
1127 parent_rate, rate);
1128
1129 return 0;
1130 }
1131
1132 static const struct clk_ops si5351_clkout_ops = {
1133 .prepare = si5351_clkout_prepare,
1134 .unprepare = si5351_clkout_unprepare,
1135 .set_parent = si5351_clkout_set_parent,
1136 .get_parent = si5351_clkout_get_parent,
1137 .recalc_rate = si5351_clkout_recalc_rate,
1138 .round_rate = si5351_clkout_round_rate,
1139 .set_rate = si5351_clkout_set_rate,
1140 };
1141
1142 /*
1143 * Si5351 i2c probe and DT
1144 */
1145 #ifdef CONFIG_OF
1146 static const struct of_device_id si5351_dt_ids[] = {
1147 { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
1148 { .compatible = "silabs,si5351a-msop",
1149 .data = (void *)SI5351_VARIANT_A3, },
1150 { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
1151 { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
1152 { }
1153 };
1154 MODULE_DEVICE_TABLE(of, si5351_dt_ids);
1155
si5351_dt_parse(struct i2c_client * client,enum si5351_variant variant)1156 static int si5351_dt_parse(struct i2c_client *client,
1157 enum si5351_variant variant)
1158 {
1159 struct device_node *child, *np = client->dev.of_node;
1160 struct si5351_platform_data *pdata;
1161 struct property *prop;
1162 const __be32 *p;
1163 int num = 0;
1164 u32 val;
1165
1166 if (np == NULL)
1167 return 0;
1168
1169 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1170 if (!pdata)
1171 return -ENOMEM;
1172
1173 /*
1174 * property silabs,pll-source : <num src>, [<..>]
1175 * allow to selectively set pll source
1176 */
1177 of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
1178 if (num >= 2) {
1179 dev_err(&client->dev,
1180 "invalid pll %d on pll-source prop\n", num);
1181 return -EINVAL;
1182 }
1183
1184 p = of_prop_next_u32(prop, p, &val);
1185 if (!p) {
1186 dev_err(&client->dev,
1187 "missing pll-source for pll %d\n", num);
1188 return -EINVAL;
1189 }
1190
1191 switch (val) {
1192 case 0:
1193 pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
1194 break;
1195 case 1:
1196 if (variant != SI5351_VARIANT_C) {
1197 dev_err(&client->dev,
1198 "invalid parent %d for pll %d\n",
1199 val, num);
1200 return -EINVAL;
1201 }
1202 pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
1203 break;
1204 default:
1205 dev_err(&client->dev,
1206 "invalid parent %d for pll %d\n", val, num);
1207 return -EINVAL;
1208 }
1209 }
1210
1211 /* per clkout properties */
1212 for_each_child_of_node(np, child) {
1213 if (of_property_read_u32(child, "reg", &num)) {
1214 dev_err(&client->dev, "missing reg property of %pOFn\n",
1215 child);
1216 goto put_child;
1217 }
1218
1219 if (num >= 8 ||
1220 (variant == SI5351_VARIANT_A3 && num >= 3)) {
1221 dev_err(&client->dev, "invalid clkout %d\n", num);
1222 goto put_child;
1223 }
1224
1225 if (!of_property_read_u32(child, "silabs,multisynth-source",
1226 &val)) {
1227 switch (val) {
1228 case 0:
1229 pdata->clkout[num].multisynth_src =
1230 SI5351_MULTISYNTH_SRC_VCO0;
1231 break;
1232 case 1:
1233 pdata->clkout[num].multisynth_src =
1234 SI5351_MULTISYNTH_SRC_VCO1;
1235 break;
1236 default:
1237 dev_err(&client->dev,
1238 "invalid parent %d for multisynth %d\n",
1239 val, num);
1240 goto put_child;
1241 }
1242 }
1243
1244 if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1245 switch (val) {
1246 case 0:
1247 pdata->clkout[num].clkout_src =
1248 SI5351_CLKOUT_SRC_MSYNTH_N;
1249 break;
1250 case 1:
1251 pdata->clkout[num].clkout_src =
1252 SI5351_CLKOUT_SRC_MSYNTH_0_4;
1253 break;
1254 case 2:
1255 pdata->clkout[num].clkout_src =
1256 SI5351_CLKOUT_SRC_XTAL;
1257 break;
1258 case 3:
1259 if (variant != SI5351_VARIANT_C) {
1260 dev_err(&client->dev,
1261 "invalid parent %d for clkout %d\n",
1262 val, num);
1263 goto put_child;
1264 }
1265 pdata->clkout[num].clkout_src =
1266 SI5351_CLKOUT_SRC_CLKIN;
1267 break;
1268 default:
1269 dev_err(&client->dev,
1270 "invalid parent %d for clkout %d\n",
1271 val, num);
1272 goto put_child;
1273 }
1274 }
1275
1276 if (!of_property_read_u32(child, "silabs,drive-strength",
1277 &val)) {
1278 switch (val) {
1279 case SI5351_DRIVE_2MA:
1280 case SI5351_DRIVE_4MA:
1281 case SI5351_DRIVE_6MA:
1282 case SI5351_DRIVE_8MA:
1283 pdata->clkout[num].drive = val;
1284 break;
1285 default:
1286 dev_err(&client->dev,
1287 "invalid drive strength %d for clkout %d\n",
1288 val, num);
1289 goto put_child;
1290 }
1291 }
1292
1293 if (!of_property_read_u32(child, "silabs,disable-state",
1294 &val)) {
1295 switch (val) {
1296 case 0:
1297 pdata->clkout[num].disable_state =
1298 SI5351_DISABLE_LOW;
1299 break;
1300 case 1:
1301 pdata->clkout[num].disable_state =
1302 SI5351_DISABLE_HIGH;
1303 break;
1304 case 2:
1305 pdata->clkout[num].disable_state =
1306 SI5351_DISABLE_FLOATING;
1307 break;
1308 case 3:
1309 pdata->clkout[num].disable_state =
1310 SI5351_DISABLE_NEVER;
1311 break;
1312 default:
1313 dev_err(&client->dev,
1314 "invalid disable state %d for clkout %d\n",
1315 val, num);
1316 goto put_child;
1317 }
1318 }
1319
1320 if (!of_property_read_u32(child, "clock-frequency", &val))
1321 pdata->clkout[num].rate = val;
1322
1323 pdata->clkout[num].pll_master =
1324 of_property_read_bool(child, "silabs,pll-master");
1325
1326 pdata->clkout[num].pll_reset =
1327 of_property_read_bool(child, "silabs,pll-reset");
1328 }
1329 client->dev.platform_data = pdata;
1330
1331 return 0;
1332 put_child:
1333 of_node_put(child);
1334 return -EINVAL;
1335 }
1336
1337 static struct clk_hw *
si53351_of_clk_get(struct of_phandle_args * clkspec,void * data)1338 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1339 {
1340 struct si5351_driver_data *drvdata = data;
1341 unsigned int idx = clkspec->args[0];
1342
1343 if (idx >= drvdata->num_clkout) {
1344 pr_err("%s: invalid index %u\n", __func__, idx);
1345 return ERR_PTR(-EINVAL);
1346 }
1347
1348 return &drvdata->clkout[idx].hw;
1349 }
1350 #else
si5351_dt_parse(struct i2c_client * client,enum si5351_variant variant)1351 static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
1352 {
1353 return 0;
1354 }
1355
1356 static struct clk_hw *
si53351_of_clk_get(struct of_phandle_args * clkspec,void * data)1357 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1358 {
1359 return NULL;
1360 }
1361 #endif /* CONFIG_OF */
1362
si5351_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)1363 static int si5351_i2c_probe(struct i2c_client *client,
1364 const struct i2c_device_id *id)
1365 {
1366 enum si5351_variant variant = (enum si5351_variant)id->driver_data;
1367 struct si5351_platform_data *pdata;
1368 struct si5351_driver_data *drvdata;
1369 struct clk_init_data init;
1370 const char *parent_names[4];
1371 u8 num_parents, num_clocks;
1372 int ret, n;
1373
1374 ret = si5351_dt_parse(client, variant);
1375 if (ret)
1376 return ret;
1377
1378 pdata = client->dev.platform_data;
1379 if (!pdata)
1380 return -EINVAL;
1381
1382 drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
1383 if (!drvdata)
1384 return -ENOMEM;
1385
1386 i2c_set_clientdata(client, drvdata);
1387 drvdata->client = client;
1388 drvdata->variant = variant;
1389 drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
1390 drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
1391
1392 if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
1393 PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
1394 return -EPROBE_DEFER;
1395
1396 /*
1397 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1398 * VARIANT_C can have CLKIN instead.
1399 */
1400 if (IS_ERR(drvdata->pxtal) &&
1401 (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
1402 dev_err(&client->dev, "missing parent clock\n");
1403 return -EINVAL;
1404 }
1405
1406 drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
1407 if (IS_ERR(drvdata->regmap)) {
1408 dev_err(&client->dev, "failed to allocate register map\n");
1409 return PTR_ERR(drvdata->regmap);
1410 }
1411
1412 /* Disable interrupts */
1413 si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
1414 /* Ensure pll select is on XTAL for Si5351A/B */
1415 if (drvdata->variant != SI5351_VARIANT_C)
1416 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
1417 SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
1418
1419 /* setup clock configuration */
1420 for (n = 0; n < 2; n++) {
1421 ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
1422 if (ret) {
1423 dev_err(&client->dev,
1424 "failed to reparent pll %d to %d\n",
1425 n, pdata->pll_src[n]);
1426 return ret;
1427 }
1428 }
1429
1430 for (n = 0; n < 8; n++) {
1431 ret = _si5351_msynth_reparent(drvdata, n,
1432 pdata->clkout[n].multisynth_src);
1433 if (ret) {
1434 dev_err(&client->dev,
1435 "failed to reparent multisynth %d to %d\n",
1436 n, pdata->clkout[n].multisynth_src);
1437 return ret;
1438 }
1439
1440 ret = _si5351_clkout_reparent(drvdata, n,
1441 pdata->clkout[n].clkout_src);
1442 if (ret) {
1443 dev_err(&client->dev,
1444 "failed to reparent clkout %d to %d\n",
1445 n, pdata->clkout[n].clkout_src);
1446 return ret;
1447 }
1448
1449 ret = _si5351_clkout_set_drive_strength(drvdata, n,
1450 pdata->clkout[n].drive);
1451 if (ret) {
1452 dev_err(&client->dev,
1453 "failed set drive strength of clkout%d to %d\n",
1454 n, pdata->clkout[n].drive);
1455 return ret;
1456 }
1457
1458 ret = _si5351_clkout_set_disable_state(drvdata, n,
1459 pdata->clkout[n].disable_state);
1460 if (ret) {
1461 dev_err(&client->dev,
1462 "failed set disable state of clkout%d to %d\n",
1463 n, pdata->clkout[n].disable_state);
1464 return ret;
1465 }
1466 }
1467
1468 /* register xtal input clock gate */
1469 memset(&init, 0, sizeof(init));
1470 init.name = si5351_input_names[0];
1471 init.ops = &si5351_xtal_ops;
1472 init.flags = 0;
1473 if (!IS_ERR(drvdata->pxtal)) {
1474 drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
1475 init.parent_names = &drvdata->pxtal_name;
1476 init.num_parents = 1;
1477 }
1478 drvdata->xtal.init = &init;
1479 ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
1480 if (ret) {
1481 dev_err(&client->dev, "unable to register %s\n", init.name);
1482 return ret;
1483 }
1484
1485 /* register clkin input clock gate */
1486 if (drvdata->variant == SI5351_VARIANT_C) {
1487 memset(&init, 0, sizeof(init));
1488 init.name = si5351_input_names[1];
1489 init.ops = &si5351_clkin_ops;
1490 if (!IS_ERR(drvdata->pclkin)) {
1491 drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
1492 init.parent_names = &drvdata->pclkin_name;
1493 init.num_parents = 1;
1494 }
1495 drvdata->clkin.init = &init;
1496 ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
1497 if (ret) {
1498 dev_err(&client->dev, "unable to register %s\n",
1499 init.name);
1500 return ret;
1501 }
1502 }
1503
1504 /* Si5351C allows to mux either xtal or clkin to PLL input */
1505 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
1506 parent_names[0] = si5351_input_names[0];
1507 parent_names[1] = si5351_input_names[1];
1508
1509 /* register PLLA */
1510 drvdata->pll[0].num = 0;
1511 drvdata->pll[0].drvdata = drvdata;
1512 drvdata->pll[0].hw.init = &init;
1513 memset(&init, 0, sizeof(init));
1514 init.name = si5351_pll_names[0];
1515 init.ops = &si5351_pll_ops;
1516 init.flags = 0;
1517 init.parent_names = parent_names;
1518 init.num_parents = num_parents;
1519 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
1520 if (ret) {
1521 dev_err(&client->dev, "unable to register %s\n", init.name);
1522 return ret;
1523 }
1524
1525 /* register PLLB or VXCO (Si5351B) */
1526 drvdata->pll[1].num = 1;
1527 drvdata->pll[1].drvdata = drvdata;
1528 drvdata->pll[1].hw.init = &init;
1529 memset(&init, 0, sizeof(init));
1530 if (drvdata->variant == SI5351_VARIANT_B) {
1531 init.name = si5351_pll_names[2];
1532 init.ops = &si5351_vxco_ops;
1533 init.flags = 0;
1534 init.parent_names = NULL;
1535 init.num_parents = 0;
1536 } else {
1537 init.name = si5351_pll_names[1];
1538 init.ops = &si5351_pll_ops;
1539 init.flags = 0;
1540 init.parent_names = parent_names;
1541 init.num_parents = num_parents;
1542 }
1543 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
1544 if (ret) {
1545 dev_err(&client->dev, "unable to register %s\n", init.name);
1546 return ret;
1547 }
1548
1549 /* register clk multisync and clk out divider */
1550 num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
1551 parent_names[0] = si5351_pll_names[0];
1552 if (drvdata->variant == SI5351_VARIANT_B)
1553 parent_names[1] = si5351_pll_names[2];
1554 else
1555 parent_names[1] = si5351_pll_names[1];
1556
1557 drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
1558 sizeof(*drvdata->msynth), GFP_KERNEL);
1559 drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
1560 sizeof(*drvdata->clkout), GFP_KERNEL);
1561 drvdata->num_clkout = num_clocks;
1562
1563 if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
1564 ret = -ENOMEM;
1565 return ret;
1566 }
1567
1568 for (n = 0; n < num_clocks; n++) {
1569 drvdata->msynth[n].num = n;
1570 drvdata->msynth[n].drvdata = drvdata;
1571 drvdata->msynth[n].hw.init = &init;
1572 memset(&init, 0, sizeof(init));
1573 init.name = si5351_msynth_names[n];
1574 init.ops = &si5351_msynth_ops;
1575 init.flags = 0;
1576 if (pdata->clkout[n].pll_master)
1577 init.flags |= CLK_SET_RATE_PARENT;
1578 init.parent_names = parent_names;
1579 init.num_parents = 2;
1580 ret = devm_clk_hw_register(&client->dev,
1581 &drvdata->msynth[n].hw);
1582 if (ret) {
1583 dev_err(&client->dev, "unable to register %s\n",
1584 init.name);
1585 return ret;
1586 }
1587 }
1588
1589 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
1590 parent_names[2] = si5351_input_names[0];
1591 parent_names[3] = si5351_input_names[1];
1592 for (n = 0; n < num_clocks; n++) {
1593 parent_names[0] = si5351_msynth_names[n];
1594 parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
1595 si5351_msynth_names[4];
1596
1597 drvdata->clkout[n].num = n;
1598 drvdata->clkout[n].drvdata = drvdata;
1599 drvdata->clkout[n].hw.init = &init;
1600 memset(&init, 0, sizeof(init));
1601 init.name = si5351_clkout_names[n];
1602 init.ops = &si5351_clkout_ops;
1603 init.flags = 0;
1604 if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
1605 init.flags |= CLK_SET_RATE_PARENT;
1606 init.parent_names = parent_names;
1607 init.num_parents = num_parents;
1608 ret = devm_clk_hw_register(&client->dev,
1609 &drvdata->clkout[n].hw);
1610 if (ret) {
1611 dev_err(&client->dev, "unable to register %s\n",
1612 init.name);
1613 return ret;
1614 }
1615
1616 /* set initial clkout rate */
1617 if (pdata->clkout[n].rate != 0) {
1618 int ret;
1619 ret = clk_set_rate(drvdata->clkout[n].hw.clk,
1620 pdata->clkout[n].rate);
1621 if (ret != 0) {
1622 dev_err(&client->dev, "Cannot set rate : %d\n",
1623 ret);
1624 }
1625 }
1626 }
1627
1628 ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get,
1629 drvdata);
1630 if (ret) {
1631 dev_err(&client->dev, "unable to add clk provider\n");
1632 return ret;
1633 }
1634
1635 return 0;
1636 }
1637
si5351_i2c_remove(struct i2c_client * client)1638 static int si5351_i2c_remove(struct i2c_client *client)
1639 {
1640 of_clk_del_provider(client->dev.of_node);
1641
1642 return 0;
1643 }
1644
1645 static const struct i2c_device_id si5351_i2c_ids[] = {
1646 { "si5351a", SI5351_VARIANT_A },
1647 { "si5351a-msop", SI5351_VARIANT_A3 },
1648 { "si5351b", SI5351_VARIANT_B },
1649 { "si5351c", SI5351_VARIANT_C },
1650 { }
1651 };
1652 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
1653
1654 static struct i2c_driver si5351_driver = {
1655 .driver = {
1656 .name = "si5351",
1657 .of_match_table = of_match_ptr(si5351_dt_ids),
1658 },
1659 .probe = si5351_i2c_probe,
1660 .remove = si5351_i2c_remove,
1661 .id_table = si5351_i2c_ids,
1662 };
1663 module_i2c_driver(si5351_driver);
1664
1665 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1666 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1667 MODULE_LICENSE("GPL");
1668
