1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * DaVinci DA850 AHCI SATA platform driver
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pm.h>
9 #include <linux/device.h>
10 #include <linux/platform_device.h>
11 #include <linux/libata.h>
12 #include <linux/ahci_platform.h>
13 #include "ahci.h"
14 
15 #define DRV_NAME		"ahci_da850"
16 #define HARDRESET_RETRIES	5
17 
18 /* SATA PHY Control Register offset from AHCI base */
19 #define SATA_P0PHYCR_REG	0x178
20 
21 #define SATA_PHY_MPY(x)		((x) << 0)
22 #define SATA_PHY_LOS(x)		((x) << 6)
23 #define SATA_PHY_RXCDR(x)	((x) << 10)
24 #define SATA_PHY_RXEQ(x)	((x) << 13)
25 #define SATA_PHY_TXSWING(x)	((x) << 19)
26 #define SATA_PHY_ENPLL(x)	((x) << 31)
27 
da850_sata_init(struct device * dev,void __iomem * pwrdn_reg,void __iomem * ahci_base,u32 mpy)28 static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
29 			    void __iomem *ahci_base, u32 mpy)
30 {
31 	unsigned int val;
32 
33 	/* Enable SATA clock receiver */
34 	val = readl(pwrdn_reg);
35 	val &= ~BIT(0);
36 	writel(val, pwrdn_reg);
37 
38 	val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) |
39 	      SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1);
40 
41 	writel(val, ahci_base + SATA_P0PHYCR_REG);
42 }
43 
ahci_da850_calculate_mpy(unsigned long refclk_rate)44 static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate)
45 {
46 	u32 pll_output = 1500000000, needed;
47 
48 	/*
49 	 * We need to determine the value of the multiplier (MPY) bits.
50 	 * In order to include the 12.5 multiplier we need to first divide
51 	 * the refclk rate by ten.
52 	 *
53 	 * __div64_32() turned out to be unreliable, sometimes returning
54 	 * false results.
55 	 */
56 	WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");
57 	needed = pll_output / (refclk_rate / 10);
58 
59 	/*
60 	 * What we have now is (multiplier * 10).
61 	 *
62 	 * Let's determine the actual register value we need to write.
63 	 */
64 
65 	switch (needed) {
66 	case 50:
67 		return 0x1;
68 	case 60:
69 		return 0x2;
70 	case 80:
71 		return 0x4;
72 	case 100:
73 		return 0x5;
74 	case 120:
75 		return 0x6;
76 	case 125:
77 		return 0x7;
78 	case 150:
79 		return 0x8;
80 	case 200:
81 		return 0x9;
82 	case 250:
83 		return 0xa;
84 	default:
85 		/*
86 		 * We should have divided evenly - if not, return an invalid
87 		 * value.
88 		 */
89 		return 0;
90 	}
91 }
92 
ahci_da850_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)93 static int ahci_da850_softreset(struct ata_link *link,
94 				unsigned int *class, unsigned long deadline)
95 {
96 	int pmp, ret;
97 
98 	pmp = sata_srst_pmp(link);
99 
100 	/*
101 	 * There's an issue with the SATA controller on da850 SoCs: if we
102 	 * enable Port Multiplier support, but the drive is connected directly
103 	 * to the board, it can't be detected. As a workaround: if PMP is
104 	 * enabled, we first call ahci_do_softreset() and pass it the result of
105 	 * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
106 	 */
107 	ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
108 	if (pmp && ret == -EBUSY)
109 		return ahci_do_softreset(link, class, 0,
110 					 deadline, ahci_check_ready);
111 
112 	return ret;
113 }
114 
ahci_da850_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)115 static int ahci_da850_hardreset(struct ata_link *link,
116 				unsigned int *class, unsigned long deadline)
117 {
118 	int ret, retry = HARDRESET_RETRIES;
119 	bool online;
120 
121 	/*
122 	 * In order to correctly service the LCD controller of the da850 SoC,
123 	 * we increased the PLL0 frequency to 456MHz from the default 300MHz.
124 	 *
125 	 * This made the SATA controller unstable and the hardreset operation
126 	 * does not always succeed the first time. Before really giving up to
127 	 * bring up the link, retry the reset a couple times.
128 	 */
129 	do {
130 		ret = ahci_do_hardreset(link, class, deadline, &online);
131 		if (online)
132 			return ret;
133 	} while (retry--);
134 
135 	return ret;
136 }
137 
138 static struct ata_port_operations ahci_da850_port_ops = {
139 	.inherits = &ahci_platform_ops,
140 	.softreset = ahci_da850_softreset,
141 	/*
142 	 * No need to override .pmp_softreset - it's only used for actual
143 	 * PMP-enabled ports.
144 	 */
145 	.hardreset = ahci_da850_hardreset,
146 	.pmp_hardreset = ahci_da850_hardreset,
147 };
148 
149 static const struct ata_port_info ahci_da850_port_info = {
150 	.flags		= AHCI_FLAG_COMMON,
151 	.pio_mask	= ATA_PIO4,
152 	.udma_mask	= ATA_UDMA6,
153 	.port_ops	= &ahci_da850_port_ops,
154 };
155 
156 static struct scsi_host_template ahci_platform_sht = {
157 	AHCI_SHT(DRV_NAME),
158 };
159 
ahci_da850_probe(struct platform_device * pdev)160 static int ahci_da850_probe(struct platform_device *pdev)
161 {
162 	struct device *dev = &pdev->dev;
163 	struct ahci_host_priv *hpriv;
164 	void __iomem *pwrdn_reg;
165 	struct resource *res;
166 	struct clk *clk;
167 	u32 mpy;
168 	int rc;
169 
170 	hpriv = ahci_platform_get_resources(pdev, 0);
171 	if (IS_ERR(hpriv))
172 		return PTR_ERR(hpriv);
173 
174 	/*
175 	 * Internally ahci_platform_get_resources() calls clk_get(dev, NULL)
176 	 * when trying to obtain the functional clock. This SATA controller
177 	 * uses two clocks for which we specify two connection ids. If we don't
178 	 * have the functional clock at this point - call clk_get() again with
179 	 * con_id = "fck".
180 	 */
181 	if (!hpriv->clks[0]) {
182 		clk = clk_get(dev, "fck");
183 		if (IS_ERR(clk))
184 			return PTR_ERR(clk);
185 
186 		hpriv->clks[0] = clk;
187 	}
188 
189 	/*
190 	 * The second clock used by ahci-da850 is the external REFCLK. If we
191 	 * didn't get it from ahci_platform_get_resources(), let's try to
192 	 * specify the con_id in clk_get().
193 	 */
194 	if (!hpriv->clks[1]) {
195 		clk = clk_get(dev, "refclk");
196 		if (IS_ERR(clk)) {
197 			dev_err(dev, "unable to obtain the reference clock");
198 			return -ENODEV;
199 		}
200 
201 		hpriv->clks[1] = clk;
202 	}
203 
204 	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1]));
205 	if (mpy == 0) {
206 		dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);
207 		return -EINVAL;
208 	}
209 
210 	rc = ahci_platform_enable_resources(hpriv);
211 	if (rc)
212 		return rc;
213 
214 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
215 	if (!res) {
216 		rc = -ENODEV;
217 		goto disable_resources;
218 	}
219 
220 	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
221 	if (!pwrdn_reg) {
222 		rc = -ENOMEM;
223 		goto disable_resources;
224 	}
225 
226 	da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);
227 
228 	rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info,
229 				     &ahci_platform_sht);
230 	if (rc)
231 		goto disable_resources;
232 
233 	return 0;
234 disable_resources:
235 	ahci_platform_disable_resources(hpriv);
236 	return rc;
237 }
238 
239 static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
240 			 ahci_platform_resume);
241 
242 static const struct of_device_id ahci_da850_of_match[] = {
243 	{ .compatible = "ti,da850-ahci", },
244 	{ },
245 };
246 MODULE_DEVICE_TABLE(of, ahci_da850_of_match);
247 
248 static struct platform_driver ahci_da850_driver = {
249 	.probe = ahci_da850_probe,
250 	.remove = ata_platform_remove_one,
251 	.driver = {
252 		.name = DRV_NAME,
253 		.of_match_table = ahci_da850_of_match,
254 		.pm = &ahci_da850_pm_ops,
255 	},
256 };
257 module_platform_driver(ahci_da850_driver);
258 
259 MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
260 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
261 MODULE_LICENSE("GPL");
262