1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Co-processor register definitions for PKUnity SoC and UniCore ISA
4  *
5  * Copyright (C) 2001-2012 GUAN Xue-tao
6  */
7 #ifndef __UNICORE_HWDEF_COPRO_H__
8 #define __UNICORE_HWDEF_COPRO_H__
9 
10 /*
11  * Control Register bits (CP#0 CR1)
12  */
13 #define CR_M	(1 << 0)	/* MMU enable				*/
14 #define CR_A	(1 << 1)	/* Alignment abort enable		*/
15 #define CR_D	(1 << 2)	/* Dcache enable			*/
16 #define CR_I	(1 << 3)	/* Icache enable			*/
17 #define CR_B	(1 << 4)	/* Dcache write mechanism: write back	*/
18 #define CR_T	(1 << 5)	/* Burst enable				*/
19 #define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
20 
21 #ifndef __ASSEMBLY__
22 
23 #define vectors_high()		(cr_alignment & CR_V)
24 
25 extern unsigned long cr_no_alignment;	/* defined in entry.S */
26 extern unsigned long cr_alignment;	/* defined in entry.S */
27 
get_cr(void)28 static inline unsigned int get_cr(void)
29 {
30 	unsigned int val;
31 	asm("movc %0, p0.c1, #0" : "=r" (val) : : "cc");
32 	return val;
33 }
34 
set_cr(unsigned int val)35 static inline void set_cr(unsigned int val)
36 {
37 	asm volatile("movc p0.c1, %0, #0" : : "r" (val) : "cc");
38 	isb();
39 }
40 
41 extern void adjust_cr(unsigned long mask, unsigned long set);
42 
43 #endif /* __ASSEMBLY__ */
44 
45 #endif /* __UNICORE_HWDEF_COPRO_H__ */
46