1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
4 *
5 * X-ES board-specific functionality
6 *
7 * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
8 *
9 * Author: Nate Case <ncase@xes-inc.com>
10 */
11
12 #include <linux/stddef.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/kdev_t.h>
16 #include <linux/delay.h>
17 #include <linux/seq_file.h>
18 #include <linux/interrupt.h>
19 #include <linux/of_platform.h>
20
21 #include <asm/time.h>
22 #include <asm/machdep.h>
23 #include <asm/pci-bridge.h>
24 #include <mm/mmu_decl.h>
25 #include <asm/prom.h>
26 #include <asm/udbg.h>
27 #include <asm/mpic.h>
28
29 #include <sysdev/fsl_soc.h>
30 #include <sysdev/fsl_pci.h>
31 #include "smp.h"
32
33 #include "mpc85xx.h"
34
35 /* A few bit definitions needed for fixups on some boards */
36 #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
37 #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
38 #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
39
xes_mpc85xx_pic_init(void)40 void __init xes_mpc85xx_pic_init(void)
41 {
42 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
43 0, 256, " OpenPIC ");
44 BUG_ON(mpic == NULL);
45 mpic_init(mpic);
46 }
47
xes_mpc85xx_configure_l2(void __iomem * l2_base)48 static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
49 {
50 volatile uint32_t ctl, tmp;
51
52 asm volatile("msync; isync");
53 tmp = in_be32(l2_base);
54
55 /*
56 * xMon may have enabled part of L2 as SRAM, so we need to set it
57 * up for all cache mode just to be safe.
58 */
59 printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
60
61 ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
62 if (of_machine_is_compatible("MPC8540") ||
63 of_machine_is_compatible("MPC8560"))
64 /*
65 * Assume L2 SRAM is used fully for cache, so set
66 * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
67 */
68 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
69
70 asm volatile("msync; isync");
71 out_be32(l2_base, ctl);
72 asm volatile("msync; isync");
73 }
74
xes_mpc85xx_fixups(void)75 static void xes_mpc85xx_fixups(void)
76 {
77 struct device_node *np;
78 int err;
79
80 /*
81 * Legacy xMon firmware on some X-ES boards does not enable L2
82 * as cache. We must ensure that they get enabled here.
83 */
84 for_each_node_by_name(np, "l2-cache-controller") {
85 struct resource r[2];
86 void __iomem *l2_base;
87
88 /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
89 if (!of_device_is_compatible(np,
90 "fsl,mpc8548-l2-cache-controller") &&
91 !of_device_is_compatible(np,
92 "fsl,mpc8540-l2-cache-controller") &&
93 !of_device_is_compatible(np,
94 "fsl,mpc8560-l2-cache-controller"))
95 continue;
96
97 err = of_address_to_resource(np, 0, &r[0]);
98 if (err) {
99 printk(KERN_WARNING "xes_mpc85xx: Could not get "
100 "resource for device tree node '%pOF'",
101 np);
102 continue;
103 }
104
105 l2_base = ioremap(r[0].start, resource_size(&r[0]));
106
107 xes_mpc85xx_configure_l2(l2_base);
108 }
109 }
110
111 /*
112 * Setup the architecture
113 */
xes_mpc85xx_setup_arch(void)114 static void __init xes_mpc85xx_setup_arch(void)
115 {
116 struct device_node *root;
117 const char *model = "Unknown";
118
119 root = of_find_node_by_path("/");
120 if (root == NULL)
121 return;
122
123 model = of_get_property(root, "model", NULL);
124
125 printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
126 model + strlen("xes,"));
127
128 xes_mpc85xx_fixups();
129
130 mpc85xx_smp_init();
131
132 fsl_pci_assign_primary();
133 }
134
135 machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
136 machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
137 machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
138
139 /*
140 * Called very early, device-tree isn't unflattened
141 */
xes_mpc8572_probe(void)142 static int __init xes_mpc8572_probe(void)
143 {
144 return of_machine_is_compatible("xes,MPC8572");
145 }
146
xes_mpc8548_probe(void)147 static int __init xes_mpc8548_probe(void)
148 {
149 return of_machine_is_compatible("xes,MPC8548");
150 }
151
xes_mpc8540_probe(void)152 static int __init xes_mpc8540_probe(void)
153 {
154 return of_machine_is_compatible("xes,MPC8540");
155 }
156
define_machine(xes_mpc8572)157 define_machine(xes_mpc8572) {
158 .name = "X-ES MPC8572",
159 .probe = xes_mpc8572_probe,
160 .setup_arch = xes_mpc85xx_setup_arch,
161 .init_IRQ = xes_mpc85xx_pic_init,
162 #ifdef CONFIG_PCI
163 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
164 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
165 #endif
166 .get_irq = mpic_get_irq,
167 .calibrate_decr = generic_calibrate_decr,
168 .progress = udbg_progress,
169 };
170
define_machine(xes_mpc8548)171 define_machine(xes_mpc8548) {
172 .name = "X-ES MPC8548",
173 .probe = xes_mpc8548_probe,
174 .setup_arch = xes_mpc85xx_setup_arch,
175 .init_IRQ = xes_mpc85xx_pic_init,
176 #ifdef CONFIG_PCI
177 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
178 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
179 #endif
180 .get_irq = mpic_get_irq,
181 .calibrate_decr = generic_calibrate_decr,
182 .progress = udbg_progress,
183 };
184
define_machine(xes_mpc8540)185 define_machine(xes_mpc8540) {
186 .name = "X-ES MPC8540",
187 .probe = xes_mpc8540_probe,
188 .setup_arch = xes_mpc85xx_setup_arch,
189 .init_IRQ = xes_mpc85xx_pic_init,
190 #ifdef CONFIG_PCI
191 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
192 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
193 #endif
194 .get_irq = mpic_get_irq,
195 .calibrate_decr = generic_calibrate_decr,
196 .progress = udbg_progress,
197 };
198
