1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
4 *
5 * Author: Li Yang <LeoLi@freescale.com>
6 * Yin Olivia <Hong-hua.Yin@freescale.com>
7 *
8 * Description:
9 * MPC8360E MDS board specific routines.
10 *
11 * Changelog:
12 * Jun 21, 2006 Initial version
13 */
14
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/compiler.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/root_dev.h>
28 #include <linux/initrd.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_device.h>
31
32 #include <linux/atomic.h>
33 #include <asm/time.h>
34 #include <asm/io.h>
35 #include <asm/machdep.h>
36 #include <asm/ipic.h>
37 #include <asm/irq.h>
38 #include <asm/prom.h>
39 #include <asm/udbg.h>
40 #include <sysdev/fsl_soc.h>
41 #include <sysdev/fsl_pci.h>
42 #include <sysdev/simple_gpio.h>
43 #include <soc/fsl/qe/qe.h>
44 #include <soc/fsl/qe/qe_ic.h>
45
46 #include "mpc83xx.h"
47
48 #undef DEBUG
49 #ifdef DEBUG
50 #define DBG(fmt...) udbg_printf(fmt)
51 #else
52 #define DBG(fmt...)
53 #endif
54
55 /* ************************************************************************
56 *
57 * Setup the architecture
58 *
59 */
mpc836x_mds_setup_arch(void)60 static void __init mpc836x_mds_setup_arch(void)
61 {
62 struct device_node *np;
63 u8 __iomem *bcsr_regs = NULL;
64
65 mpc83xx_setup_arch();
66
67 /* Map BCSR area */
68 np = of_find_node_by_name(NULL, "bcsr");
69 if (np) {
70 struct resource res;
71
72 of_address_to_resource(np, 0, &res);
73 bcsr_regs = ioremap(res.start, resource_size(&res));
74 of_node_put(np);
75 }
76
77 #ifdef CONFIG_QUICC_ENGINE
78 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
79 par_io_init(np);
80 of_node_put(np);
81
82 for_each_node_by_name(np, "ucc")
83 par_io_of_config(np);
84 #ifdef CONFIG_QE_USB
85 /* Must fixup Par IO before QE GPIO chips are registered. */
86 par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
87 par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
88 par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
89 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
90 par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
91 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
92 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
93 #endif /* CONFIG_QE_USB */
94 }
95
96 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
97 != NULL){
98 uint svid;
99
100 /* Reset the Ethernet PHY */
101 #define BCSR9_GETHRST 0x20
102 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
103 udelay(1000);
104 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
105
106 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
107 svid = mfspr(SPRN_SVR);
108 if (svid == 0x80480021) {
109 void __iomem *immap;
110
111 immap = ioremap(get_immrbase() + 0x14a8, 8);
112
113 /*
114 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
115 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
116 */
117 setbits32(immap, 0x0c003000);
118
119 /*
120 * IMMR + 0x14AC[20:27] = 10101010
121 * (data delay for both UCC's)
122 */
123 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
124
125 iounmap(immap);
126 }
127
128 iounmap(bcsr_regs);
129 of_node_put(np);
130 }
131 #endif /* CONFIG_QUICC_ENGINE */
132 }
133
134 machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
135
136 #ifdef CONFIG_QE_USB
mpc836x_usb_cfg(void)137 static int __init mpc836x_usb_cfg(void)
138 {
139 u8 __iomem *bcsr;
140 struct device_node *np;
141 const char *mode;
142 int ret = 0;
143
144 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
145 if (!np)
146 return -ENODEV;
147
148 bcsr = of_iomap(np, 0);
149 of_node_put(np);
150 if (!bcsr)
151 return -ENOMEM;
152
153 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
154 if (!np) {
155 ret = -ENODEV;
156 goto err;
157 }
158
159 #define BCSR8_TSEC1M_MASK (0x3 << 6)
160 #define BCSR8_TSEC1M_RGMII (0x0 << 6)
161 #define BCSR8_TSEC2M_MASK (0x3 << 4)
162 #define BCSR8_TSEC2M_RGMII (0x0 << 4)
163 /*
164 * Default is GMII (2), but we should set it to RGMII (0) if we use
165 * USB (Eth PHY is in RGMII mode anyway).
166 */
167 clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
168 BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
169
170 #define BCSR13_USBMASK 0x0f
171 #define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
172 #define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
173 #define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
174 #define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
175
176 clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
177
178 mode = of_get_property(np, "mode", NULL);
179 if (mode && !strcmp(mode, "peripheral")) {
180 setbits8(&bcsr[13], BCSR13_nUSBVCC);
181 qe_usb_clock_set(QE_CLK21, 48000000);
182 } else {
183 setbits8(&bcsr[13], BCSR13_USBMODE);
184 /*
185 * The BCSR GPIOs are used to control power and
186 * speed of the USB transceiver. This is needed for
187 * the USB Host only.
188 */
189 simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
190 }
191
192 of_node_put(np);
193 err:
194 iounmap(bcsr);
195 return ret;
196 }
197 machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
198 #endif /* CONFIG_QE_USB */
199
200 /*
201 * Called very early, MMU is off, device-tree isn't unflattened
202 */
mpc836x_mds_probe(void)203 static int __init mpc836x_mds_probe(void)
204 {
205 return of_machine_is_compatible("MPC836xMDS");
206 }
207
define_machine(mpc836x_mds)208 define_machine(mpc836x_mds) {
209 .name = "MPC836x MDS",
210 .probe = mpc836x_mds_probe,
211 .setup_arch = mpc836x_mds_setup_arch,
212 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
213 .get_irq = ipic_get_irq,
214 .restart = mpc83xx_restart,
215 .time_init = mpc83xx_time_init,
216 .calibrate_decr = generic_calibrate_decr,
217 .progress = udbg_progress,
218 };
219
