1// SPDX-License-Identifier: GPL-2.0 2/ { 3 #address-cells = <1>; 4 #size-cells = <1>; 5 compatible = "brcm,bcm3368"; 6 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 mips-hpt-frequency = <150000000>; 12 13 cpu@0 { 14 compatible = "brcm,bmips4350"; 15 device_type = "cpu"; 16 reg = <0>; 17 }; 18 19 cpu@1 { 20 compatible = "brcm,bmips4350"; 21 device_type = "cpu"; 22 reg = <1>; 23 }; 24 }; 25 26 clocks { 27 periph_clk: periph-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <50000000>; 31 }; 32 }; 33 34 aliases { 35 serial0 = &uart0; 36 serial1 = &uart1; 37 }; 38 39 cpu_intc: interrupt-controller { 40 #address-cells = <0>; 41 compatible = "mti,cpu-interrupt-controller"; 42 43 interrupt-controller; 44 #interrupt-cells = <1>; 45 }; 46 47 ubus { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 compatible = "simple-bus"; 52 ranges; 53 54 clkctl: clock-controller@fff8c004 { 55 compatible = "brcm,bcm3368-clocks"; 56 reg = <0xfff8c004 0x4>; 57 #clock-cells = <1>; 58 }; 59 60 periph_cntl: syscon@fff8c008 { 61 compatible = "syscon"; 62 reg = <0xfff8c000 0x4>; 63 native-endian; 64 }; 65 66 reboot: syscon-reboot@fff8c008 { 67 compatible = "syscon-reboot"; 68 regmap = <&periph_cntl>; 69 offset = <0x0>; 70 mask = <0x1>; 71 }; 72 73 periph_intc: interrupt-controller@fff8c00c { 74 compatible = "brcm,bcm6345-l1-intc"; 75 reg = <0xfff8c00c 0x8>; 76 77 interrupt-controller; 78 #interrupt-cells = <1>; 79 80 interrupt-parent = <&cpu_intc>; 81 interrupts = <2>; 82 }; 83 84 uart0: serial@fff8c100 { 85 compatible = "brcm,bcm6345-uart"; 86 reg = <0xfff8c100 0x18>; 87 88 interrupt-parent = <&periph_intc>; 89 interrupts = <2>; 90 91 clocks = <&periph_clk>; 92 clock-names = "refclk"; 93 94 status = "disabled"; 95 }; 96 97 uart1: serial@fff8c120 { 98 compatible = "brcm,bcm6345-uart"; 99 reg = <0xfff8c120 0x18>; 100 101 interrupt-parent = <&periph_intc>; 102 interrupts = <3>; 103 104 clocks = <&periph_clk>; 105 clock-names = "refclk"; 106 107 status = "disabled"; 108 }; 109 }; 110}; 111