1/* 2 * Spreadtrum Whale2 platform peripherals 3 * 4 * Copyright (C) 2016, Spreadtrum Communications Inc. 5 * 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 */ 8 9#include <dt-bindings/clock/sprd,sc9860-clk.h> 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 soc: soc { 17 compatible = "simple-bus"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 ap_ahb_regs: syscon@20210000 { 23 compatible = "syscon"; 24 reg = <0 0x20210000 0 0x10000>; 25 }; 26 27 pmu_regs: syscon@402b0000 { 28 compatible = "syscon"; 29 reg = <0 0x402b0000 0 0x10000>; 30 }; 31 32 aon_regs: syscon@402e0000 { 33 compatible = "syscon"; 34 reg = <0 0x402e0000 0 0x10000>; 35 }; 36 37 ana_regs: syscon@40400000 { 38 compatible = "syscon"; 39 reg = <0 0x40400000 0 0x10000>; 40 }; 41 42 agcp_regs: syscon@415e0000 { 43 compatible = "syscon"; 44 reg = <0 0x415e0000 0 0x1000000>; 45 }; 46 47 vsp_regs: syscon@61100000 { 48 compatible = "syscon"; 49 reg = <0 0x61100000 0 0x10000>; 50 }; 51 52 cam_regs: syscon@62100000 { 53 compatible = "syscon"; 54 reg = <0 0x62100000 0 0x10000>; 55 }; 56 57 disp_regs: syscon@63100000 { 58 compatible = "syscon"; 59 reg = <0 0x63100000 0 0x10000>; 60 }; 61 62 ap_apb_regs: syscon@70b00000 { 63 compatible = "syscon"; 64 reg = <0 0x70b00000 0 0x40000>; 65 }; 66 67 ap-apb { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 0x0 0x70000000 0x10000000>; 72 73 uart0: serial@0 { 74 compatible = "sprd,sc9860-uart", 75 "sprd,sc9836-uart"; 76 reg = <0x0 0x100>; 77 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 78 clock-names = "enable", "uart", "source"; 79 clocks = <&apapb_gate CLK_UART0_EB>, 80 <&ap_clk CLK_UART0>, <&ext_26m>; 81 status = "disabled"; 82 }; 83 84 uart1: serial@100000 { 85 compatible = "sprd,sc9860-uart", 86 "sprd,sc9836-uart"; 87 reg = <0x100000 0x100>; 88 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 89 clock-names = "enable", "uart", "source"; 90 clocks = <&apapb_gate CLK_UART1_EB>, 91 <&ap_clk CLK_UART1>, <&ext_26m>; 92 status = "disabled"; 93 }; 94 95 uart2: serial@200000 { 96 compatible = "sprd,sc9860-uart", 97 "sprd,sc9836-uart"; 98 reg = <0x200000 0x100>; 99 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 100 clock-names = "enable", "uart", "source"; 101 clocks = <&apapb_gate CLK_UART2_EB>, 102 <&ap_clk CLK_UART2>, <&ext_26m>; 103 status = "disabled"; 104 }; 105 106 uart3: serial@300000 { 107 compatible = "sprd,sc9860-uart", 108 "sprd,sc9836-uart"; 109 reg = <0x300000 0x100>; 110 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 111 clock-names = "enable", "uart", "source"; 112 clocks = <&apapb_gate CLK_UART3_EB>, 113 <&ap_clk CLK_UART3>, <&ext_26m>; 114 status = "disabled"; 115 }; 116 }; 117 118 ap-ahb { 119 compatible = "simple-bus"; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges; 123 124 ap_dma: dma-controller@20100000 { 125 compatible = "sprd,sc9860-dma"; 126 reg = <0 0x20100000 0 0x4000>; 127 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 128 #dma-cells = <1>; 129 #dma-channels = <32>; 130 clock-names = "enable"; 131 clocks = <&apahb_gate CLK_DMA_EB>; 132 }; 133 134 sdio3: sdio@50430000 { 135 compatible = "sprd,sdhci-r11"; 136 reg = <0 0x50430000 0 0x1000>; 137 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 138 139 clock-names = "sdio", "enable", "2x_enable"; 140 clocks = <&aon_prediv CLK_EMMC_2X>, 141 <&apahb_gate CLK_EMMC_EB>, 142 <&aon_gate CLK_EMMC_2X_EN>; 143 assigned-clocks = <&aon_prediv CLK_EMMC_2X>; 144 assigned-clock-parents = <&clk_l0_409m6>; 145 146 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; 147 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; 148 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; 149 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; 150 vmmc-supply = <&vddemmccore>; 151 bus-width = <8>; 152 non-removable; 153 no-sdio; 154 no-sd; 155 cap-mmc-hw-reset; 156 mmc-hs400-enhanced-strobe; 157 mmc-hs400-1_8v; 158 mmc-hs200-1_8v; 159 mmc-ddr-1_8v; 160 }; 161 }; 162 163 aon { 164 compatible = "simple-bus"; 165 #address-cells = <2>; 166 #size-cells = <2>; 167 ranges; 168 169 adi_bus: spi@40030000 { 170 compatible = "sprd,sc9860-adi"; 171 reg = <0 0x40030000 0 0x10000>; 172 hwlocks = <&hwlock 0>; 173 hwlock-names = "adi"; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 }; 177 178 timer@40050000 { 179 compatible = "sprd,sc9860-timer"; 180 reg = <0 0x40050000 0 0x20>; 181 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&ext_32k>; 183 }; 184 185 timer@40050020 { 186 compatible = "sprd,sc9860-suspend-timer"; 187 reg = <0 0x40050020 0 0x20>; 188 clocks = <&ext_32k>; 189 }; 190 191 hwlock: hwspinlock@40500000 { 192 compatible = "sprd,hwspinlock-r3p0"; 193 reg = <0 0x40500000 0 0x1000>; 194 #hwlock-cells = <1>; 195 clock-names = "enable"; 196 clocks = <&aon_gate CLK_SPLK_EB>; 197 }; 198 199 eic_debounce: gpio@40210000 { 200 compatible = "sprd,sc9860-eic-debounce"; 201 reg = <0 0x40210000 0 0x80>; 202 gpio-controller; 203 #gpio-cells = <2>; 204 interrupt-controller; 205 #interrupt-cells = <2>; 206 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 207 }; 208 209 eic_latch: gpio@40210080 { 210 compatible = "sprd,sc9860-eic-latch"; 211 reg = <0 0x40210080 0 0x20>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 217 }; 218 219 eic_async: gpio@402100a0 { 220 compatible = "sprd,sc9860-eic-async"; 221 reg = <0 0x402100a0 0 0x20>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 interrupt-controller; 225 #interrupt-cells = <2>; 226 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 eic_sync: gpio@402100c0 { 230 compatible = "sprd,sc9860-eic-sync"; 231 reg = <0 0x402100c0 0 0x20>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 237 }; 238 239 ap_gpio: gpio@40280000 { 240 compatible = "sprd,sc9860-gpio"; 241 reg = <0 0x40280000 0 0x1000>; 242 gpio-controller; 243 #gpio-cells = <2>; 244 interrupt-controller; 245 #interrupt-cells = <2>; 246 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 247 }; 248 249 pin_controller: pinctrl@402a0000 { 250 compatible = "sprd,sc9860-pinctrl"; 251 reg = <0 0x402a0000 0 0x10000>; 252 }; 253 254 watchdog@40310000 { 255 compatible = "sprd,sp9860-wdt"; 256 reg = <0 0x40310000 0 0x1000>; 257 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 258 timeout-sec = <12>; 259 clock-names = "enable", "rtc_enable"; 260 clocks = <&aon_gate CLK_APCPU_WDG_EB>, 261 <&aon_gate CLK_AP_WDG_RTC_EB>; 262 }; 263 }; 264 265 agcp { 266 compatible = "simple-bus"; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges; 270 271 agcp_dma: dma-controller@41580000 { 272 compatible = "sprd,sc9860-dma"; 273 reg = <0 0x41580000 0 0x4000>; 274 #dma-cells = <1>; 275 #dma-channels = <32>; 276 clock-names = "enable", "ashb_eb"; 277 clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 278 <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 279 }; 280 }; 281 }; 282 283 ext_32k: ext_32k { 284 compatible = "fixed-clock"; 285 #clock-cells = <0>; 286 clock-frequency = <32768>; 287 clock-output-names = "ext-32k"; 288 }; 289 290 ext_26m: ext_26m { 291 compatible = "fixed-clock"; 292 #clock-cells = <0>; 293 clock-frequency = <26000000>; 294 clock-output-names = "ext-26m"; 295 }; 296 297 ext_rco_100m: ext_rco_100m { 298 compatible = "fixed-clock"; 299 #clock-cells = <0>; 300 clock-frequency = <100000000>; 301 clock-output-names = "ext-rco-100m"; 302 }; 303 304 clk_l0_409m6: clk_l0_409m6 { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <409600000>; 308 clock-output-names = "ext-409m6"; 309 }; 310}; 311
