1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/power/qcom-rpmpd.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 qcom,msm-id = <292 0x0>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 memory { 21 device_type = "memory"; 22 /* We expect the bootloader to fill in the reg */ 23 reg = <0 0 0 0>; 24 }; 25 26 reserved-memory { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 memory@85800000 { 32 reg = <0x0 0x85800000 0x0 0x800000>; 33 no-map; 34 }; 35 36 smem_mem: smem-mem@86000000 { 37 reg = <0x0 0x86000000 0x0 0x200000>; 38 no-map; 39 }; 40 41 memory@86200000 { 42 reg = <0x0 0x86200000 0x0 0x2d00000>; 43 no-map; 44 }; 45 46 rmtfs { 47 compatible = "qcom,rmtfs-mem"; 48 49 size = <0x0 0x200000>; 50 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 51 no-map; 52 53 qcom,client-id = <1>; 54 qcom,vmid = <15>; 55 }; 56 }; 57 58 clocks { 59 xo: xo-board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <19200000>; 63 clock-output-names = "xo_board"; 64 }; 65 66 sleep_clk { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <32764>; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <2>; 75 #size-cells = <0>; 76 77 CPU0: cpu@0 { 78 device_type = "cpu"; 79 compatible = "arm,armv8"; 80 reg = <0x0 0x0>; 81 enable-method = "psci"; 82 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 83 next-level-cache = <&L2_0>; 84 L2_0: l2-cache { 85 compatible = "arm,arch-cache"; 86 cache-level = <2>; 87 }; 88 L1_I_0: l1-icache { 89 compatible = "arm,arch-cache"; 90 }; 91 L1_D_0: l1-dcache { 92 compatible = "arm,arch-cache"; 93 }; 94 }; 95 96 CPU1: cpu@1 { 97 device_type = "cpu"; 98 compatible = "arm,armv8"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 102 next-level-cache = <&L2_0>; 103 L1_I_1: l1-icache { 104 compatible = "arm,arch-cache"; 105 }; 106 L1_D_1: l1-dcache { 107 compatible = "arm,arch-cache"; 108 }; 109 }; 110 111 CPU2: cpu@2 { 112 device_type = "cpu"; 113 compatible = "arm,armv8"; 114 reg = <0x0 0x2>; 115 enable-method = "psci"; 116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 117 next-level-cache = <&L2_0>; 118 L1_I_2: l1-icache { 119 compatible = "arm,arch-cache"; 120 }; 121 L1_D_2: l1-dcache { 122 compatible = "arm,arch-cache"; 123 }; 124 }; 125 126 CPU3: cpu@3 { 127 device_type = "cpu"; 128 compatible = "arm,armv8"; 129 reg = <0x0 0x3>; 130 enable-method = "psci"; 131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 132 next-level-cache = <&L2_0>; 133 L1_I_3: l1-icache { 134 compatible = "arm,arch-cache"; 135 }; 136 L1_D_3: l1-dcache { 137 compatible = "arm,arch-cache"; 138 }; 139 }; 140 141 CPU4: cpu@100 { 142 device_type = "cpu"; 143 compatible = "arm,armv8"; 144 reg = <0x0 0x100>; 145 enable-method = "psci"; 146 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 147 next-level-cache = <&L2_1>; 148 L2_1: l2-cache { 149 compatible = "arm,arch-cache"; 150 cache-level = <2>; 151 }; 152 L1_I_100: l1-icache { 153 compatible = "arm,arch-cache"; 154 }; 155 L1_D_100: l1-dcache { 156 compatible = "arm,arch-cache"; 157 }; 158 }; 159 160 CPU5: cpu@101 { 161 device_type = "cpu"; 162 compatible = "arm,armv8"; 163 reg = <0x0 0x101>; 164 enable-method = "psci"; 165 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 166 next-level-cache = <&L2_1>; 167 L1_I_101: l1-icache { 168 compatible = "arm,arch-cache"; 169 }; 170 L1_D_101: l1-dcache { 171 compatible = "arm,arch-cache"; 172 }; 173 }; 174 175 CPU6: cpu@102 { 176 device_type = "cpu"; 177 compatible = "arm,armv8"; 178 reg = <0x0 0x102>; 179 enable-method = "psci"; 180 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 181 next-level-cache = <&L2_1>; 182 L1_I_102: l1-icache { 183 compatible = "arm,arch-cache"; 184 }; 185 L1_D_102: l1-dcache { 186 compatible = "arm,arch-cache"; 187 }; 188 }; 189 190 CPU7: cpu@103 { 191 device_type = "cpu"; 192 compatible = "arm,armv8"; 193 reg = <0x0 0x103>; 194 enable-method = "psci"; 195 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 196 next-level-cache = <&L2_1>; 197 L1_I_103: l1-icache { 198 compatible = "arm,arch-cache"; 199 }; 200 L1_D_103: l1-dcache { 201 compatible = "arm,arch-cache"; 202 }; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&CPU0>; 209 }; 210 211 core1 { 212 cpu = <&CPU1>; 213 }; 214 215 core2 { 216 cpu = <&CPU2>; 217 }; 218 219 core3 { 220 cpu = <&CPU3>; 221 }; 222 }; 223 224 cluster1 { 225 core0 { 226 cpu = <&CPU4>; 227 }; 228 229 core1 { 230 cpu = <&CPU5>; 231 }; 232 233 core2 { 234 cpu = <&CPU6>; 235 }; 236 237 core3 { 238 cpu = <&CPU7>; 239 }; 240 }; 241 }; 242 243 idle-states { 244 entry-method = "psci"; 245 246 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "little-retention"; 249 arm,psci-suspend-param = <0x00000002>; 250 entry-latency-us = <81>; 251 exit-latency-us = <86>; 252 min-residency-us = <200>; 253 }; 254 255 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "little-power-collapse"; 258 arm,psci-suspend-param = <0x40000003>; 259 entry-latency-us = <273>; 260 exit-latency-us = <612>; 261 min-residency-us = <1000>; 262 local-timer-stop; 263 }; 264 265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "big-retention"; 268 arm,psci-suspend-param = <0x00000002>; 269 entry-latency-us = <79>; 270 exit-latency-us = <82>; 271 min-residency-us = <200>; 272 }; 273 274 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "big-power-collapse"; 277 arm,psci-suspend-param = <0x40000003>; 278 entry-latency-us = <336>; 279 exit-latency-us = <525>; 280 min-residency-us = <1000>; 281 local-timer-stop; 282 }; 283 }; 284 }; 285 286 firmware { 287 scm { 288 compatible = "qcom,scm-msm8998", "qcom,scm"; 289 }; 290 }; 291 292 tcsr_mutex: hwlock { 293 compatible = "qcom,tcsr-mutex"; 294 syscon = <&tcsr_mutex_regs 0 0x1000>; 295 #hwlock-cells = <1>; 296 }; 297 298 psci { 299 compatible = "arm,psci-1.0"; 300 method = "smc"; 301 }; 302 303 rpm-glink { 304 compatible = "qcom,glink-rpm"; 305 306 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 307 qcom,rpm-msg-ram = <&rpm_msg_ram>; 308 mboxes = <&apcs_glb 0>; 309 310 rpm_requests: rpm-requests { 311 compatible = "qcom,rpm-msm8998"; 312 qcom,glink-channels = "rpm_requests"; 313 314 rpmcc: clock-controller { 315 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 316 #clock-cells = <1>; 317 }; 318 319 rpmpd: power-controller { 320 compatible = "qcom,msm8998-rpmpd"; 321 #power-domain-cells = <1>; 322 operating-points-v2 = <&rpmpd_opp_table>; 323 324 rpmpd_opp_table: opp-table { 325 compatible = "operating-points-v2"; 326 327 rpmpd_opp_ret: opp1 { 328 opp-level = <16>; 329 }; 330 331 rpmpd_opp_ret_plus: opp2 { 332 opp-level = <32>; 333 }; 334 335 rpmpd_opp_min_svs: opp3 { 336 opp-level = <48>; 337 }; 338 339 rpmpd_opp_low_svs: opp4 { 340 opp-level = <64>; 341 }; 342 343 rpmpd_opp_svs: opp5 { 344 opp-level = <128>; 345 }; 346 347 rpmpd_opp_svs_plus: opp6 { 348 opp-level = <192>; 349 }; 350 351 rpmpd_opp_nom: opp7 { 352 opp-level = <256>; 353 }; 354 355 rpmpd_opp_nom_plus: opp8 { 356 opp-level = <320>; 357 }; 358 359 rpmpd_opp_turbo: opp9 { 360 opp-level = <384>; 361 }; 362 363 rpmpd_opp_turbo_plus: opp10 { 364 opp-level = <512>; 365 }; 366 }; 367 }; 368 }; 369 }; 370 371 smem { 372 compatible = "qcom,smem"; 373 memory-region = <&smem_mem>; 374 hwlocks = <&tcsr_mutex 3>; 375 }; 376 377 smp2p-lpass { 378 compatible = "qcom,smp2p"; 379 qcom,smem = <443>, <429>; 380 381 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 382 383 mboxes = <&apcs_glb 10>; 384 385 qcom,local-pid = <0>; 386 qcom,remote-pid = <2>; 387 388 adsp_smp2p_out: master-kernel { 389 qcom,entry-name = "master-kernel"; 390 #qcom,smem-state-cells = <1>; 391 }; 392 393 adsp_smp2p_in: slave-kernel { 394 qcom,entry-name = "slave-kernel"; 395 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 }; 399 }; 400 401 smp2p-mpss { 402 compatible = "qcom,smp2p"; 403 qcom,smem = <435>, <428>; 404 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 405 mboxes = <&apcs_glb 14>; 406 qcom,local-pid = <0>; 407 qcom,remote-pid = <1>; 408 409 modem_smp2p_out: master-kernel { 410 qcom,entry-name = "master-kernel"; 411 #qcom,smem-state-cells = <1>; 412 }; 413 414 modem_smp2p_in: slave-kernel { 415 qcom,entry-name = "slave-kernel"; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 }; 419 }; 420 421 smp2p-slpi { 422 compatible = "qcom,smp2p"; 423 qcom,smem = <481>, <430>; 424 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 425 mboxes = <&apcs_glb 26>; 426 qcom,local-pid = <0>; 427 qcom,remote-pid = <3>; 428 429 slpi_smp2p_out: master-kernel { 430 qcom,entry-name = "master-kernel"; 431 #qcom,smem-state-cells = <1>; 432 }; 433 434 slpi_smp2p_in: slave-kernel { 435 qcom,entry-name = "slave-kernel"; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 thermal-zones { 442 cpu0-thermal { 443 polling-delay-passive = <250>; 444 polling-delay = <1000>; 445 446 thermal-sensors = <&tsens0 1>; 447 448 trips { 449 cpu0_alert0: trip-point@0 { 450 temperature = <75000>; 451 hysteresis = <2000>; 452 type = "passive"; 453 }; 454 455 cpu0_crit: cpu_crit { 456 temperature = <110000>; 457 hysteresis = <2000>; 458 type = "critical"; 459 }; 460 }; 461 }; 462 463 cpu1-thermal { 464 polling-delay-passive = <250>; 465 polling-delay = <1000>; 466 467 thermal-sensors = <&tsens0 2>; 468 469 trips { 470 cpu1_alert0: trip-point@0 { 471 temperature = <75000>; 472 hysteresis = <2000>; 473 type = "passive"; 474 }; 475 476 cpu1_crit: cpu_crit { 477 temperature = <110000>; 478 hysteresis = <2000>; 479 type = "critical"; 480 }; 481 }; 482 }; 483 484 cpu2-thermal { 485 polling-delay-passive = <250>; 486 polling-delay = <1000>; 487 488 thermal-sensors = <&tsens0 3>; 489 490 trips { 491 cpu2_alert0: trip-point@0 { 492 temperature = <75000>; 493 hysteresis = <2000>; 494 type = "passive"; 495 }; 496 497 cpu2_crit: cpu_crit { 498 temperature = <110000>; 499 hysteresis = <2000>; 500 type = "critical"; 501 }; 502 }; 503 }; 504 505 cpu3-thermal { 506 polling-delay-passive = <250>; 507 polling-delay = <1000>; 508 509 thermal-sensors = <&tsens0 4>; 510 511 trips { 512 cpu3_alert0: trip-point@0 { 513 temperature = <75000>; 514 hysteresis = <2000>; 515 type = "passive"; 516 }; 517 518 cpu3_crit: cpu_crit { 519 temperature = <110000>; 520 hysteresis = <2000>; 521 type = "critical"; 522 }; 523 }; 524 }; 525 526 cpu4-thermal { 527 polling-delay-passive = <250>; 528 polling-delay = <1000>; 529 530 thermal-sensors = <&tsens0 7>; 531 532 trips { 533 cpu4_alert0: trip-point@0 { 534 temperature = <75000>; 535 hysteresis = <2000>; 536 type = "passive"; 537 }; 538 539 cpu4_crit: cpu_crit { 540 temperature = <110000>; 541 hysteresis = <2000>; 542 type = "critical"; 543 }; 544 }; 545 }; 546 547 cpu5-thermal { 548 polling-delay-passive = <250>; 549 polling-delay = <1000>; 550 551 thermal-sensors = <&tsens0 8>; 552 553 trips { 554 cpu5_alert0: trip-point@0 { 555 temperature = <75000>; 556 hysteresis = <2000>; 557 type = "passive"; 558 }; 559 560 cpu5_crit: cpu_crit { 561 temperature = <110000>; 562 hysteresis = <2000>; 563 type = "critical"; 564 }; 565 }; 566 }; 567 568 cpu6-thermal { 569 polling-delay-passive = <250>; 570 polling-delay = <1000>; 571 572 thermal-sensors = <&tsens0 9>; 573 574 trips { 575 cpu6_alert0: trip-point@0 { 576 temperature = <75000>; 577 hysteresis = <2000>; 578 type = "passive"; 579 }; 580 581 cpu6_crit: cpu_crit { 582 temperature = <110000>; 583 hysteresis = <2000>; 584 type = "critical"; 585 }; 586 }; 587 }; 588 589 cpu7-thermal { 590 polling-delay-passive = <250>; 591 polling-delay = <1000>; 592 593 thermal-sensors = <&tsens0 10>; 594 595 trips { 596 cpu7_alert0: trip-point@0 { 597 temperature = <75000>; 598 hysteresis = <2000>; 599 type = "passive"; 600 }; 601 602 cpu7_crit: cpu_crit { 603 temperature = <110000>; 604 hysteresis = <2000>; 605 type = "critical"; 606 }; 607 }; 608 }; 609 610 gpu-thermal-bottom { 611 polling-delay-passive = <250>; 612 polling-delay = <1000>; 613 614 thermal-sensors = <&tsens0 12>; 615 616 trips { 617 gpu1_alert0: trip-point@0 { 618 temperature = <90000>; 619 hysteresis = <2000>; 620 type = "hot"; 621 }; 622 }; 623 }; 624 625 gpu-thermal-top { 626 polling-delay-passive = <250>; 627 polling-delay = <1000>; 628 629 thermal-sensors = <&tsens0 13>; 630 631 trips { 632 gpu2_alert0: trip-point@0 { 633 temperature = <90000>; 634 hysteresis = <2000>; 635 type = "hot"; 636 }; 637 }; 638 }; 639 640 clust0-mhm-thermal { 641 polling-delay-passive = <250>; 642 polling-delay = <1000>; 643 644 thermal-sensors = <&tsens0 5>; 645 646 trips { 647 cluster0_mhm_alert0: trip-point@0 { 648 temperature = <90000>; 649 hysteresis = <2000>; 650 type = "hot"; 651 }; 652 }; 653 }; 654 655 clust1-mhm-thermal { 656 polling-delay-passive = <250>; 657 polling-delay = <1000>; 658 659 thermal-sensors = <&tsens0 6>; 660 661 trips { 662 cluster1_mhm_alert0: trip-point@0 { 663 temperature = <90000>; 664 hysteresis = <2000>; 665 type = "hot"; 666 }; 667 }; 668 }; 669 670 cluster1-l2-thermal { 671 polling-delay-passive = <250>; 672 polling-delay = <1000>; 673 674 thermal-sensors = <&tsens0 11>; 675 676 trips { 677 cluster1_l2_alert0: trip-point@0 { 678 temperature = <90000>; 679 hysteresis = <2000>; 680 type = "hot"; 681 }; 682 }; 683 }; 684 685 modem-thermal { 686 polling-delay-passive = <250>; 687 polling-delay = <1000>; 688 689 thermal-sensors = <&tsens1 1>; 690 691 trips { 692 modem_alert0: trip-point@0 { 693 temperature = <90000>; 694 hysteresis = <2000>; 695 type = "hot"; 696 }; 697 }; 698 }; 699 700 mem-thermal { 701 polling-delay-passive = <250>; 702 polling-delay = <1000>; 703 704 thermal-sensors = <&tsens1 2>; 705 706 trips { 707 mem_alert0: trip-point@0 { 708 temperature = <90000>; 709 hysteresis = <2000>; 710 type = "hot"; 711 }; 712 }; 713 }; 714 715 wlan-thermal { 716 polling-delay-passive = <250>; 717 polling-delay = <1000>; 718 719 thermal-sensors = <&tsens1 3>; 720 721 trips { 722 wlan_alert0: trip-point@0 { 723 temperature = <90000>; 724 hysteresis = <2000>; 725 type = "hot"; 726 }; 727 }; 728 }; 729 730 q6-dsp-thermal { 731 polling-delay-passive = <250>; 732 polling-delay = <1000>; 733 734 thermal-sensors = <&tsens1 4>; 735 736 trips { 737 q6_dsp_alert0: trip-point@0 { 738 temperature = <90000>; 739 hysteresis = <2000>; 740 type = "hot"; 741 }; 742 }; 743 }; 744 745 camera-thermal { 746 polling-delay-passive = <250>; 747 polling-delay = <1000>; 748 749 thermal-sensors = <&tsens1 5>; 750 751 trips { 752 camera_alert0: trip-point@0 { 753 temperature = <90000>; 754 hysteresis = <2000>; 755 type = "hot"; 756 }; 757 }; 758 }; 759 760 multimedia-thermal { 761 polling-delay-passive = <250>; 762 polling-delay = <1000>; 763 764 thermal-sensors = <&tsens1 6>; 765 766 trips { 767 multimedia_alert0: trip-point@0 { 768 temperature = <90000>; 769 hysteresis = <2000>; 770 type = "hot"; 771 }; 772 }; 773 }; 774 }; 775 776 timer { 777 compatible = "arm,armv8-timer"; 778 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 779 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 780 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 781 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 782 }; 783 784 soc: soc { 785 #address-cells = <1>; 786 #size-cells = <1>; 787 ranges = <0 0 0 0xffffffff>; 788 compatible = "simple-bus"; 789 790 gcc: clock-controller@100000 { 791 compatible = "qcom,gcc-msm8998"; 792 #clock-cells = <1>; 793 #reset-cells = <1>; 794 #power-domain-cells = <1>; 795 reg = <0x00100000 0xb0000>; 796 }; 797 798 rpm_msg_ram: memory@778000 { 799 compatible = "qcom,rpm-msg-ram"; 800 reg = <0x00778000 0x7000>; 801 }; 802 803 qfprom: qfprom@780000 { 804 compatible = "qcom,qfprom"; 805 reg = <0x00780000 0x621c>; 806 #address-cells = <1>; 807 #size-cells = <1>; 808 809 qusb2_hstx_trim: hstx-trim@423a { 810 reg = <0x423a 0x1>; 811 bits = <0 4>; 812 }; 813 }; 814 815 tsens0: thermal@10ab000 { 816 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 817 reg = <0x010ab000 0x1000>, /* TM */ 818 <0x010aa000 0x1000>; /* SROT */ 819 820 #qcom,sensors = <14>; 821 #thermal-sensor-cells = <1>; 822 }; 823 824 tsens1: thermal@10ae000 { 825 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 826 reg = <0x010ae000 0x1000>, /* TM */ 827 <0x010ad000 0x1000>; /* SROT */ 828 829 #qcom,sensors = <8>; 830 #thermal-sensor-cells = <1>; 831 }; 832 833 anoc1_smmu: iommu@1680000 { 834 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 835 reg = <0x01680000 0x10000>; 836 #iommu-cells = <1>; 837 838 #global-interrupts = <0>; 839 interrupts = 840 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 841 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 842 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 843 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 844 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 845 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 846 }; 847 848 pcie0: pci@1c00000 { 849 compatible = "qcom,pcie-msm8996"; 850 reg = <0x01c00000 0x2000>, 851 <0x1b000000 0xf1d>, 852 <0x1b000f20 0xa8>, 853 <0x1b100000 0x100000>; 854 reg-names = "parf", "dbi", "elbi", "config"; 855 device_type = "pci"; 856 linux,pci-domain = <0>; 857 bus-range = <0x00 0xff>; 858 #address-cells = <3>; 859 #size-cells = <2>; 860 num-lanes = <1>; 861 phys = <&pciephy>; 862 phy-names = "pciephy"; 863 864 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 865 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 866 867 #interrupt-cells = <1>; 868 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-names = "msi"; 870 interrupt-map-mask = <0 0 0 0x7>; 871 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 872 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 873 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 874 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 875 876 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 877 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 878 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 879 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 880 <&gcc GCC_PCIE_0_AUX_CLK>; 881 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 882 883 power-domains = <&gcc PCIE_0_GDSC>; 884 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 885 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 886 }; 887 888 phy@1c06000 { 889 compatible = "qcom,msm8998-qmp-pcie-phy"; 890 reg = <0x01c06000 0x18c>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 ranges; 894 895 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 896 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 897 <&gcc GCC_PCIE_CLKREF_CLK>; 898 clock-names = "aux", "cfg_ahb", "ref"; 899 900 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 901 reset-names = "phy", "common"; 902 903 vdda-phy-supply = <&vreg_l1a_0p875>; 904 vdda-pll-supply = <&vreg_l2a_1p2>; 905 906 pciephy: lane@1c06800 { 907 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 908 #phy-cells = <0>; 909 910 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 911 clock-names = "pipe0"; 912 clock-output-names = "pcie_0_pipe_clk_src"; 913 #clock-cells = <0>; 914 }; 915 }; 916 917 ufshc: ufshc@1da4000 { 918 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 919 reg = <0x01da4000 0x2500>; 920 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 921 phys = <&ufsphy_lanes>; 922 phy-names = "ufsphy"; 923 lanes-per-direction = <2>; 924 power-domains = <&gcc UFS_GDSC>; 925 #reset-cells = <1>; 926 927 clock-names = 928 "core_clk", 929 "bus_aggr_clk", 930 "iface_clk", 931 "core_clk_unipro", 932 "ref_clk", 933 "tx_lane0_sync_clk", 934 "rx_lane0_sync_clk", 935 "rx_lane1_sync_clk"; 936 clocks = 937 <&gcc GCC_UFS_AXI_CLK>, 938 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 939 <&gcc GCC_UFS_AHB_CLK>, 940 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 941 <&rpmcc RPM_SMD_LN_BB_CLK1>, 942 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 943 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 944 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 945 freq-table-hz = 946 <50000000 200000000>, 947 <0 0>, 948 <0 0>, 949 <37500000 150000000>, 950 <0 0>, 951 <0 0>, 952 <0 0>, 953 <0 0>; 954 955 resets = <&gcc GCC_UFS_BCR>; 956 reset-names = "rst"; 957 }; 958 959 ufsphy: phy@1da7000 { 960 compatible = "qcom,msm8998-qmp-ufs-phy"; 961 reg = <0x01da7000 0x18c>; 962 #address-cells = <1>; 963 #size-cells = <1>; 964 ranges; 965 966 clock-names = 967 "ref", 968 "ref_aux"; 969 clocks = 970 <&gcc GCC_UFS_CLKREF_CLK>, 971 <&gcc GCC_UFS_PHY_AUX_CLK>; 972 973 reset-names = "ufsphy"; 974 resets = <&ufshc 0>; 975 976 ufsphy_lanes: lanes@1da7400 { 977 reg = <0x01da7400 0x128>, 978 <0x01da7600 0x1fc>, 979 <0x01da7c00 0x1dc>, 980 <0x01da7800 0x128>, 981 <0x01da7a00 0x1fc>; 982 #phy-cells = <0>; 983 }; 984 }; 985 986 tcsr_mutex_regs: syscon@1f40000 { 987 compatible = "syscon"; 988 reg = <0x01f40000 0x20000>; 989 }; 990 991 tlmm: pinctrl@3400000 { 992 compatible = "qcom,msm8998-pinctrl"; 993 reg = <0x03400000 0xc00000>; 994 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 995 gpio-controller; 996 #gpio-cells = <0x2>; 997 interrupt-controller; 998 #interrupt-cells = <0x2>; 999 }; 1000 1001 stm@6002000 { 1002 compatible = "arm,coresight-stm", "arm,primecell"; 1003 reg = <0x06002000 0x1000>, 1004 <0x16280000 0x180000>; 1005 reg-names = "stm-base", "stm-data-base"; 1006 1007 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1008 clock-names = "apb_pclk", "atclk"; 1009 1010 out-ports { 1011 port { 1012 stm_out: endpoint { 1013 remote-endpoint = <&funnel0_in7>; 1014 }; 1015 }; 1016 }; 1017 }; 1018 1019 funnel@6041000 { 1020 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1021 reg = <0x06041000 0x1000>; 1022 1023 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1024 clock-names = "apb_pclk", "atclk"; 1025 1026 out-ports { 1027 port { 1028 funnel0_out: endpoint { 1029 remote-endpoint = 1030 <&merge_funnel_in0>; 1031 }; 1032 }; 1033 }; 1034 1035 in-ports { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 1039 port@7 { 1040 reg = <7>; 1041 funnel0_in7: endpoint { 1042 remote-endpoint = <&stm_out>; 1043 }; 1044 }; 1045 }; 1046 }; 1047 1048 funnel@6042000 { 1049 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1050 reg = <0x06042000 0x1000>; 1051 1052 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1053 clock-names = "apb_pclk", "atclk"; 1054 1055 out-ports { 1056 port { 1057 funnel1_out: endpoint { 1058 remote-endpoint = 1059 <&merge_funnel_in1>; 1060 }; 1061 }; 1062 }; 1063 1064 in-ports { 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 port@6 { 1069 reg = <6>; 1070 funnel1_in6: endpoint { 1071 remote-endpoint = 1072 <&apss_merge_funnel_out>; 1073 }; 1074 }; 1075 }; 1076 }; 1077 1078 funnel@6045000 { 1079 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1080 reg = <0x06045000 0x1000>; 1081 1082 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1083 clock-names = "apb_pclk", "atclk"; 1084 1085 out-ports { 1086 port { 1087 merge_funnel_out: endpoint { 1088 remote-endpoint = 1089 <&etf_in>; 1090 }; 1091 }; 1092 }; 1093 1094 in-ports { 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 1098 port@0 { 1099 reg = <0>; 1100 merge_funnel_in0: endpoint { 1101 remote-endpoint = 1102 <&funnel0_out>; 1103 }; 1104 }; 1105 1106 port@1 { 1107 reg = <1>; 1108 merge_funnel_in1: endpoint { 1109 remote-endpoint = 1110 <&funnel1_out>; 1111 }; 1112 }; 1113 }; 1114 }; 1115 1116 replicator@6046000 { 1117 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1118 reg = <0x06046000 0x1000>; 1119 1120 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1121 clock-names = "apb_pclk", "atclk"; 1122 1123 out-ports { 1124 port { 1125 replicator_out: endpoint { 1126 remote-endpoint = <&etr_in>; 1127 }; 1128 }; 1129 }; 1130 1131 in-ports { 1132 port { 1133 replicator_in: endpoint { 1134 remote-endpoint = <&etf_out>; 1135 }; 1136 }; 1137 }; 1138 }; 1139 1140 etf@6047000 { 1141 compatible = "arm,coresight-tmc", "arm,primecell"; 1142 reg = <0x06047000 0x1000>; 1143 1144 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1145 clock-names = "apb_pclk", "atclk"; 1146 1147 out-ports { 1148 port { 1149 etf_out: endpoint { 1150 remote-endpoint = 1151 <&replicator_in>; 1152 }; 1153 }; 1154 }; 1155 1156 in-ports { 1157 port { 1158 etf_in: endpoint { 1159 remote-endpoint = 1160 <&merge_funnel_out>; 1161 }; 1162 }; 1163 }; 1164 }; 1165 1166 etr@6048000 { 1167 compatible = "arm,coresight-tmc", "arm,primecell"; 1168 reg = <0x06048000 0x1000>; 1169 1170 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1171 clock-names = "apb_pclk", "atclk"; 1172 arm,scatter-gather; 1173 1174 in-ports { 1175 port { 1176 etr_in: endpoint { 1177 remote-endpoint = 1178 <&replicator_out>; 1179 }; 1180 }; 1181 }; 1182 }; 1183 1184 etm@7840000 { 1185 compatible = "arm,coresight-etm4x", "arm,primecell"; 1186 reg = <0x07840000 0x1000>; 1187 1188 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1189 clock-names = "apb_pclk", "atclk"; 1190 1191 cpu = <&CPU0>; 1192 1193 out-ports { 1194 port { 1195 etm0_out: endpoint { 1196 remote-endpoint = 1197 <&apss_funnel_in0>; 1198 }; 1199 }; 1200 }; 1201 }; 1202 1203 etm@7940000 { 1204 compatible = "arm,coresight-etm4x", "arm,primecell"; 1205 reg = <0x07940000 0x1000>; 1206 1207 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1208 clock-names = "apb_pclk", "atclk"; 1209 1210 cpu = <&CPU1>; 1211 1212 out-ports { 1213 port { 1214 etm1_out: endpoint { 1215 remote-endpoint = 1216 <&apss_funnel_in1>; 1217 }; 1218 }; 1219 }; 1220 }; 1221 1222 etm@7a40000 { 1223 compatible = "arm,coresight-etm4x", "arm,primecell"; 1224 reg = <0x07a40000 0x1000>; 1225 1226 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1227 clock-names = "apb_pclk", "atclk"; 1228 1229 cpu = <&CPU2>; 1230 1231 out-ports { 1232 port { 1233 etm2_out: endpoint { 1234 remote-endpoint = 1235 <&apss_funnel_in2>; 1236 }; 1237 }; 1238 }; 1239 }; 1240 1241 etm@7b40000 { 1242 compatible = "arm,coresight-etm4x", "arm,primecell"; 1243 reg = <0x07b40000 0x1000>; 1244 1245 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1246 clock-names = "apb_pclk", "atclk"; 1247 1248 cpu = <&CPU3>; 1249 1250 out-ports { 1251 port { 1252 etm3_out: endpoint { 1253 remote-endpoint = 1254 <&apss_funnel_in3>; 1255 }; 1256 }; 1257 }; 1258 }; 1259 1260 funnel@7b60000 { /* APSS Funnel */ 1261 compatible = "arm,coresight-etm4x", "arm,primecell"; 1262 reg = <0x07b60000 0x1000>; 1263 1264 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1265 clock-names = "apb_pclk", "atclk"; 1266 1267 out-ports { 1268 port { 1269 apss_funnel_out: endpoint { 1270 remote-endpoint = 1271 <&apss_merge_funnel_in>; 1272 }; 1273 }; 1274 }; 1275 1276 in-ports { 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 1280 port@0 { 1281 reg = <0>; 1282 apss_funnel_in0: endpoint { 1283 remote-endpoint = 1284 <&etm0_out>; 1285 }; 1286 }; 1287 1288 port@1 { 1289 reg = <1>; 1290 apss_funnel_in1: endpoint { 1291 remote-endpoint = 1292 <&etm1_out>; 1293 }; 1294 }; 1295 1296 port@2 { 1297 reg = <2>; 1298 apss_funnel_in2: endpoint { 1299 remote-endpoint = 1300 <&etm2_out>; 1301 }; 1302 }; 1303 1304 port@3 { 1305 reg = <3>; 1306 apss_funnel_in3: endpoint { 1307 remote-endpoint = 1308 <&etm3_out>; 1309 }; 1310 }; 1311 1312 port@4 { 1313 reg = <4>; 1314 apss_funnel_in4: endpoint { 1315 remote-endpoint = 1316 <&etm4_out>; 1317 }; 1318 }; 1319 1320 port@5 { 1321 reg = <5>; 1322 apss_funnel_in5: endpoint { 1323 remote-endpoint = 1324 <&etm5_out>; 1325 }; 1326 }; 1327 1328 port@6 { 1329 reg = <6>; 1330 apss_funnel_in6: endpoint { 1331 remote-endpoint = 1332 <&etm6_out>; 1333 }; 1334 }; 1335 1336 port@7 { 1337 reg = <7>; 1338 apss_funnel_in7: endpoint { 1339 remote-endpoint = 1340 <&etm7_out>; 1341 }; 1342 }; 1343 }; 1344 }; 1345 1346 funnel@7b70000 { 1347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1348 reg = <0x07b70000 0x1000>; 1349 1350 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1351 clock-names = "apb_pclk", "atclk"; 1352 1353 out-ports { 1354 port { 1355 apss_merge_funnel_out: endpoint { 1356 remote-endpoint = 1357 <&funnel1_in6>; 1358 }; 1359 }; 1360 }; 1361 1362 in-ports { 1363 port { 1364 apss_merge_funnel_in: endpoint { 1365 remote-endpoint = 1366 <&apss_funnel_out>; 1367 }; 1368 }; 1369 }; 1370 }; 1371 1372 etm@7c40000 { 1373 compatible = "arm,coresight-etm4x", "arm,primecell"; 1374 reg = <0x07c40000 0x1000>; 1375 1376 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1377 clock-names = "apb_pclk", "atclk"; 1378 1379 cpu = <&CPU4>; 1380 1381 port{ 1382 etm4_out: endpoint { 1383 remote-endpoint = <&apss_funnel_in4>; 1384 }; 1385 }; 1386 }; 1387 1388 etm@7d40000 { 1389 compatible = "arm,coresight-etm4x", "arm,primecell"; 1390 reg = <0x07d40000 0x1000>; 1391 1392 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1393 clock-names = "apb_pclk", "atclk"; 1394 1395 cpu = <&CPU5>; 1396 1397 port{ 1398 etm5_out: endpoint { 1399 remote-endpoint = <&apss_funnel_in5>; 1400 }; 1401 }; 1402 }; 1403 1404 etm@7e40000 { 1405 compatible = "arm,coresight-etm4x", "arm,primecell"; 1406 reg = <0x07e40000 0x1000>; 1407 1408 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1409 clock-names = "apb_pclk", "atclk"; 1410 1411 cpu = <&CPU6>; 1412 1413 port{ 1414 etm6_out: endpoint { 1415 remote-endpoint = <&apss_funnel_in6>; 1416 }; 1417 }; 1418 }; 1419 1420 etm@7f40000 { 1421 compatible = "arm,coresight-etm4x", "arm,primecell"; 1422 reg = <0x07f40000 0x1000>; 1423 1424 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1425 clock-names = "apb_pclk", "atclk"; 1426 1427 cpu = <&CPU7>; 1428 1429 port{ 1430 etm7_out: endpoint { 1431 remote-endpoint = <&apss_funnel_in7>; 1432 }; 1433 }; 1434 }; 1435 1436 spmi_bus: spmi@800f000 { 1437 compatible = "qcom,spmi-pmic-arb"; 1438 reg = <0x0800f000 0x1000>, 1439 <0x08400000 0x1000000>, 1440 <0x09400000 0x1000000>, 1441 <0x0a400000 0x220000>, 1442 <0x0800a000 0x3000>; 1443 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1444 interrupt-names = "periph_irq"; 1445 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1446 qcom,ee = <0>; 1447 qcom,channel = <0>; 1448 #address-cells = <2>; 1449 #size-cells = <0>; 1450 interrupt-controller; 1451 #interrupt-cells = <4>; 1452 cell-index = <0>; 1453 }; 1454 1455 usb3: usb@a8f8800 { 1456 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 1457 reg = <0x0a8f8800 0x400>; 1458 status = "disabled"; 1459 #address-cells = <1>; 1460 #size-cells = <1>; 1461 ranges; 1462 1463 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1464 <&gcc GCC_USB30_MASTER_CLK>, 1465 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 1466 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1467 <&gcc GCC_USB30_SLEEP_CLK>; 1468 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1469 "sleep"; 1470 1471 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1472 <&gcc GCC_USB30_MASTER_CLK>; 1473 assigned-clock-rates = <19200000>, <120000000>; 1474 1475 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1477 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1478 1479 power-domains = <&gcc USB_30_GDSC>; 1480 1481 resets = <&gcc GCC_USB_30_BCR>; 1482 1483 usb3_dwc3: dwc3@a800000 { 1484 compatible = "snps,dwc3"; 1485 reg = <0x0a800000 0xcd00>; 1486 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1487 snps,dis_u2_susphy_quirk; 1488 snps,dis_enblslpm_quirk; 1489 phys = <&qusb2phy>, <&usb1_ssphy>; 1490 phy-names = "usb2-phy", "usb3-phy"; 1491 snps,has-lpm-erratum; 1492 snps,hird-threshold = /bits/ 8 <0x10>; 1493 }; 1494 }; 1495 1496 usb3phy: phy@c010000 { 1497 compatible = "qcom,msm8998-qmp-usb3-phy"; 1498 reg = <0x0c010000 0x18c>; 1499 status = "disabled"; 1500 #clock-cells = <1>; 1501 #address-cells = <1>; 1502 #size-cells = <1>; 1503 ranges; 1504 1505 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1506 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1507 <&gcc GCC_USB3_CLKREF_CLK>; 1508 clock-names = "aux", "cfg_ahb", "ref"; 1509 1510 resets = <&gcc GCC_USB3_PHY_BCR>, 1511 <&gcc GCC_USB3PHY_PHY_BCR>; 1512 reset-names = "phy", "common"; 1513 1514 usb1_ssphy: lane@c010200 { 1515 reg = <0xc010200 0x128>, 1516 <0xc010400 0x200>, 1517 <0xc010c00 0x20c>, 1518 <0xc010600 0x128>, 1519 <0xc010800 0x200>; 1520 #phy-cells = <0>; 1521 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1522 clock-names = "pipe0"; 1523 clock-output-names = "usb3_phy_pipe_clk_src"; 1524 }; 1525 }; 1526 1527 qusb2phy: phy@c012000 { 1528 compatible = "qcom,msm8998-qusb2-phy"; 1529 reg = <0x0c012000 0x2a8>; 1530 status = "disabled"; 1531 #phy-cells = <0>; 1532 1533 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1534 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1535 clock-names = "cfg_ahb", "ref"; 1536 1537 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1538 1539 nvmem-cells = <&qusb2_hstx_trim>; 1540 }; 1541 1542 sdhc2: sdhci@c0a4900 { 1543 compatible = "qcom,sdhci-msm-v4"; 1544 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 1545 reg-names = "hc_mem", "core_mem"; 1546 1547 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1549 interrupt-names = "hc_irq", "pwr_irq"; 1550 1551 clock-names = "iface", "core", "xo"; 1552 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1553 <&gcc GCC_SDCC2_APPS_CLK>, 1554 <&xo>; 1555 bus-width = <4>; 1556 status = "disabled"; 1557 }; 1558 1559 blsp1_i2c1: i2c@c175000 { 1560 compatible = "qcom,i2c-qup-v2.2.1"; 1561 reg = <0x0c175000 0x600>; 1562 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1563 1564 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1565 <&gcc GCC_BLSP1_AHB_CLK>; 1566 clock-names = "core", "iface"; 1567 clock-frequency = <400000>; 1568 1569 status = "disabled"; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 }; 1573 1574 blsp1_i2c2: i2c@c176000 { 1575 compatible = "qcom,i2c-qup-v2.2.1"; 1576 reg = <0x0c176000 0x600>; 1577 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1578 1579 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1580 <&gcc GCC_BLSP1_AHB_CLK>; 1581 clock-names = "core", "iface"; 1582 clock-frequency = <400000>; 1583 1584 status = "disabled"; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 }; 1588 1589 blsp1_i2c3: i2c@c177000 { 1590 compatible = "qcom,i2c-qup-v2.2.1"; 1591 reg = <0x0c177000 0x600>; 1592 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1593 1594 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1595 <&gcc GCC_BLSP1_AHB_CLK>; 1596 clock-names = "core", "iface"; 1597 clock-frequency = <400000>; 1598 1599 status = "disabled"; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 }; 1603 1604 blsp1_i2c4: i2c@c178000 { 1605 compatible = "qcom,i2c-qup-v2.2.1"; 1606 reg = <0x0c178000 0x600>; 1607 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1608 1609 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1610 <&gcc GCC_BLSP1_AHB_CLK>; 1611 clock-names = "core", "iface"; 1612 clock-frequency = <400000>; 1613 1614 status = "disabled"; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 }; 1618 1619 blsp1_i2c5: i2c@c179000 { 1620 compatible = "qcom,i2c-qup-v2.2.1"; 1621 reg = <0x0c179000 0x600>; 1622 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1623 1624 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1625 <&gcc GCC_BLSP1_AHB_CLK>; 1626 clock-names = "core", "iface"; 1627 clock-frequency = <400000>; 1628 1629 status = "disabled"; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 }; 1633 1634 blsp1_i2c6: i2c@c17a000 { 1635 compatible = "qcom,i2c-qup-v2.2.1"; 1636 reg = <0x0c17a000 0x600>; 1637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1638 1639 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1640 <&gcc GCC_BLSP1_AHB_CLK>; 1641 clock-names = "core", "iface"; 1642 clock-frequency = <400000>; 1643 1644 status = "disabled"; 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 }; 1648 1649 blsp2_uart1: serial@c1b0000 { 1650 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1651 reg = <0x0c1b0000 0x1000>; 1652 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1653 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1654 <&gcc GCC_BLSP2_AHB_CLK>; 1655 clock-names = "core", "iface"; 1656 status = "disabled"; 1657 }; 1658 1659 blsp2_i2c0: i2c@c1b5000 { 1660 compatible = "qcom,i2c-qup-v2.2.1"; 1661 reg = <0x0c1b5000 0x600>; 1662 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1663 1664 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1665 <&gcc GCC_BLSP2_AHB_CLK>; 1666 clock-names = "core", "iface"; 1667 clock-frequency = <400000>; 1668 1669 status = "disabled"; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 }; 1673 1674 blsp2_i2c1: i2c@c1b6000 { 1675 compatible = "qcom,i2c-qup-v2.2.1"; 1676 reg = <0x0c1b6000 0x600>; 1677 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1678 1679 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1680 <&gcc GCC_BLSP2_AHB_CLK>; 1681 clock-names = "core", "iface"; 1682 clock-frequency = <400000>; 1683 1684 status = "disabled"; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 }; 1688 1689 blsp2_i2c2: i2c@c1b7000 { 1690 compatible = "qcom,i2c-qup-v2.2.1"; 1691 reg = <0x0c1b7000 0x600>; 1692 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1693 1694 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1695 <&gcc GCC_BLSP2_AHB_CLK>; 1696 clock-names = "core", "iface"; 1697 clock-frequency = <400000>; 1698 1699 status = "disabled"; 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 }; 1703 1704 blsp2_i2c3: i2c@c1b8000 { 1705 compatible = "qcom,i2c-qup-v2.2.1"; 1706 reg = <0x0c1b8000 0x600>; 1707 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1708 1709 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1710 <&gcc GCC_BLSP2_AHB_CLK>; 1711 clock-names = "core", "iface"; 1712 clock-frequency = <400000>; 1713 1714 status = "disabled"; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 }; 1718 1719 blsp2_i2c4: i2c@c1b9000 { 1720 compatible = "qcom,i2c-qup-v2.2.1"; 1721 reg = <0x0c1b9000 0x600>; 1722 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1723 1724 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1725 <&gcc GCC_BLSP2_AHB_CLK>; 1726 clock-names = "core", "iface"; 1727 clock-frequency = <400000>; 1728 1729 status = "disabled"; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 }; 1733 1734 blsp2_i2c5: i2c@c1ba000 { 1735 compatible = "qcom,i2c-qup-v2.2.1"; 1736 reg = <0x0c1ba000 0x600>; 1737 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1738 1739 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1740 <&gcc GCC_BLSP2_AHB_CLK>; 1741 clock-names = "core", "iface"; 1742 clock-frequency = <400000>; 1743 1744 status = "disabled"; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 }; 1748 1749 apcs_glb: mailbox@17911000 { 1750 compatible = "qcom,msm8998-apcs-hmss-global"; 1751 reg = <0x17911000 0x1000>; 1752 1753 #mbox-cells = <1>; 1754 }; 1755 1756 timer@17920000 { 1757 #address-cells = <1>; 1758 #size-cells = <1>; 1759 ranges; 1760 compatible = "arm,armv7-timer-mem"; 1761 reg = <0x17920000 0x1000>; 1762 1763 frame@17921000 { 1764 frame-number = <0>; 1765 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1767 reg = <0x17921000 0x1000>, 1768 <0x17922000 0x1000>; 1769 }; 1770 1771 frame@17923000 { 1772 frame-number = <1>; 1773 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1774 reg = <0x17923000 0x1000>; 1775 status = "disabled"; 1776 }; 1777 1778 frame@17924000 { 1779 frame-number = <2>; 1780 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1781 reg = <0x17924000 0x1000>; 1782 status = "disabled"; 1783 }; 1784 1785 frame@17925000 { 1786 frame-number = <3>; 1787 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1788 reg = <0x17925000 0x1000>; 1789 status = "disabled"; 1790 }; 1791 1792 frame@17926000 { 1793 frame-number = <4>; 1794 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1795 reg = <0x17926000 0x1000>; 1796 status = "disabled"; 1797 }; 1798 1799 frame@17927000 { 1800 frame-number = <5>; 1801 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1802 reg = <0x17927000 0x1000>; 1803 status = "disabled"; 1804 }; 1805 1806 frame@17928000 { 1807 frame-number = <6>; 1808 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1809 reg = <0x17928000 0x1000>; 1810 status = "disabled"; 1811 }; 1812 }; 1813 1814 intc: interrupt-controller@17a00000 { 1815 compatible = "arm,gic-v3"; 1816 reg = <0x17a00000 0x10000>, /* GICD */ 1817 <0x17b00000 0x100000>; /* GICR * 8 */ 1818 #interrupt-cells = <3>; 1819 #address-cells = <1>; 1820 #size-cells = <1>; 1821 ranges; 1822 interrupt-controller; 1823 #redistributor-regions = <1>; 1824 redistributor-stride = <0x0 0x20000>; 1825 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1826 }; 1827 }; 1828}; 1829 1830#include "msm8998-pins.dtsi" 1831
