1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1046a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 fman0 = &fman0; 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 ethernet2 = &enet2; 26 ethernet3 = &enet3; 27 ethernet4 = &enet4; 28 ethernet5 = &enet5; 29 ethernet6 = &enet6; 30 ethernet7 = &enet7; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a72"; 40 reg = <0x0>; 41 clocks = <&clockgen 1 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PH20>; 44 #cooling-cells = <2>; 45 }; 46 47 cpu1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a72"; 50 reg = <0x1>; 51 clocks = <&clockgen 1 0>; 52 next-level-cache = <&l2>; 53 cpu-idle-states = <&CPU_PH20>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a72"; 60 reg = <0x2>; 61 clocks = <&clockgen 1 0>; 62 next-level-cache = <&l2>; 63 cpu-idle-states = <&CPU_PH20>; 64 #cooling-cells = <2>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a72"; 70 reg = <0x3>; 71 clocks = <&clockgen 1 0>; 72 next-level-cache = <&l2>; 73 cpu-idle-states = <&CPU_PH20>; 74 #cooling-cells = <2>; 75 }; 76 77 l2: l2-cache { 78 compatible = "cache"; 79 }; 80 }; 81 82 idle-states { 83 /* 84 * PSCI node is not added default, U-boot will add missing 85 * parts if it determines to use PSCI. 86 */ 87 entry-method = "psci"; 88 89 CPU_PH20: cpu-ph20 { 90 compatible = "arm,idle-state"; 91 idle-state-name = "PH20"; 92 arm,psci-suspend-param = <0x0>; 93 entry-latency-us = <1000>; 94 exit-latency-us = <1000>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 99 memory@80000000 { 100 device_type = "memory"; 101 /* Real size will be filled by bootloader */ 102 reg = <0x0 0x80000000 0x0 0x0>; 103 }; 104 105 sysclk: sysclk { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <100000000>; 109 clock-output-names = "sysclk"; 110 }; 111 112 reboot { 113 compatible ="syscon-reboot"; 114 regmap = <&dcfg>; 115 offset = <0xb0>; 116 mask = <0x02>; 117 }; 118 119 thermal-zones { 120 cpu_thermal: cpu-thermal { 121 polling-delay-passive = <1000>; 122 polling-delay = <5000>; 123 thermal-sensors = <&tmu 3>; 124 125 trips { 126 cpu_alert: cpu-alert { 127 temperature = <85000>; 128 hysteresis = <2000>; 129 type = "passive"; 130 }; 131 132 cpu_crit: cpu-crit { 133 temperature = <95000>; 134 hysteresis = <2000>; 135 type = "critical"; 136 }; 137 }; 138 139 cooling-maps { 140 map0 { 141 trip = <&cpu_alert>; 142 cooling-device = 143 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 144 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 145 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 146 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 147 }; 148 }; 149 }; 150 }; 151 152 timer { 153 compatible = "arm,armv8-timer"; 154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 155 IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 157 IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 159 IRQ_TYPE_LEVEL_LOW)>, 160 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 161 IRQ_TYPE_LEVEL_LOW)>; 162 }; 163 164 pmu { 165 compatible = "arm,cortex-a72-pmu"; 166 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-affinity = <&cpu0>, 171 <&cpu1>, 172 <&cpu2>, 173 <&cpu3>; 174 }; 175 176 gic: interrupt-controller@1400000 { 177 compatible = "arm,gic-400"; 178 #interrupt-cells = <3>; 179 interrupt-controller; 180 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 181 <0x0 0x1420000 0 0x20000>, /* GICC */ 182 <0x0 0x1440000 0 0x20000>, /* GICH */ 183 <0x0 0x1460000 0 0x20000>; /* GICV */ 184 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 185 IRQ_TYPE_LEVEL_LOW)>; 186 }; 187 188 soc: soc { 189 compatible = "simple-bus"; 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 ddr: memory-controller@1080000 { 195 compatible = "fsl,qoriq-memory-controller"; 196 reg = <0x0 0x1080000 0x0 0x1000>; 197 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 198 big-endian; 199 }; 200 201 ifc: ifc@1530000 { 202 compatible = "fsl,ifc", "simple-bus"; 203 reg = <0x0 0x1530000 0x0 0x10000>; 204 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 205 status = "disabled"; 206 }; 207 208 qspi: spi@1550000 { 209 compatible = "fsl,ls1021a-qspi"; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 reg = <0x0 0x1550000 0x0 0x10000>, 213 <0x0 0x40000000 0x0 0x10000000>; 214 reg-names = "QuadSPI", "QuadSPI-memory"; 215 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 216 clock-names = "qspi_en", "qspi"; 217 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 218 status = "disabled"; 219 }; 220 221 esdhc: esdhc@1560000 { 222 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 223 reg = <0x0 0x1560000 0x0 0x10000>; 224 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&clockgen 2 1>; 226 voltage-ranges = <1800 1800 3300 3300>; 227 sdhci,auto-cmd12; 228 big-endian; 229 bus-width = <4>; 230 }; 231 232 scfg: scfg@1570000 { 233 compatible = "fsl,ls1046a-scfg", "syscon"; 234 reg = <0x0 0x1570000 0x0 0x10000>; 235 big-endian; 236 }; 237 238 crypto: crypto@1700000 { 239 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 240 "fsl,sec-v4.0"; 241 fsl,sec-era = <8>; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0x0 0x00 0x1700000 0x100000>; 245 reg = <0x00 0x1700000 0x0 0x100000>; 246 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 247 248 sec_jr0: jr@10000 { 249 compatible = "fsl,sec-v5.4-job-ring", 250 "fsl,sec-v5.0-job-ring", 251 "fsl,sec-v4.0-job-ring"; 252 reg = <0x10000 0x10000>; 253 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 254 }; 255 256 sec_jr1: jr@20000 { 257 compatible = "fsl,sec-v5.4-job-ring", 258 "fsl,sec-v5.0-job-ring", 259 "fsl,sec-v4.0-job-ring"; 260 reg = <0x20000 0x10000>; 261 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 264 sec_jr2: jr@30000 { 265 compatible = "fsl,sec-v5.4-job-ring", 266 "fsl,sec-v5.0-job-ring", 267 "fsl,sec-v4.0-job-ring"; 268 reg = <0x30000 0x10000>; 269 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 270 }; 271 272 sec_jr3: jr@40000 { 273 compatible = "fsl,sec-v5.4-job-ring", 274 "fsl,sec-v5.0-job-ring", 275 "fsl,sec-v4.0-job-ring"; 276 reg = <0x40000 0x10000>; 277 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 278 }; 279 }; 280 281 qman: qman@1880000 { 282 compatible = "fsl,qman"; 283 reg = <0x0 0x1880000 0x0 0x10000>; 284 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 285 memory-region = <&qman_fqd &qman_pfdr>; 286 287 }; 288 289 bman: bman@1890000 { 290 compatible = "fsl,bman"; 291 reg = <0x0 0x1890000 0x0 0x10000>; 292 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 293 memory-region = <&bman_fbpr>; 294 295 }; 296 297 qportals: qman-portals@500000000 { 298 ranges = <0x0 0x5 0x00000000 0x8000000>; 299 }; 300 301 bportals: bman-portals@508000000 { 302 ranges = <0x0 0x5 0x08000000 0x8000000>; 303 }; 304 305 dcfg: dcfg@1ee0000 { 306 compatible = "fsl,ls1046a-dcfg", "syscon"; 307 reg = <0x0 0x1ee0000 0x0 0x10000>; 308 big-endian; 309 }; 310 311 clockgen: clocking@1ee1000 { 312 compatible = "fsl,ls1046a-clockgen"; 313 reg = <0x0 0x1ee1000 0x0 0x1000>; 314 #clock-cells = <2>; 315 clocks = <&sysclk>; 316 }; 317 318 tmu: tmu@1f00000 { 319 compatible = "fsl,qoriq-tmu"; 320 reg = <0x0 0x1f00000 0x0 0x10000>; 321 interrupts = <0 33 0x4>; 322 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 323 fsl,tmu-calibration = 324 /* Calibration data group 1 */ 325 <0x00000000 0x00000026 326 0x00000001 0x0000002d 327 0x00000002 0x00000032 328 0x00000003 0x00000039 329 0x00000004 0x0000003f 330 0x00000005 0x00000046 331 0x00000006 0x0000004d 332 0x00000007 0x00000054 333 0x00000008 0x0000005a 334 0x00000009 0x00000061 335 0x0000000a 0x0000006a 336 0x0000000b 0x00000071 337 /* Calibration data group 2 */ 338 0x00010000 0x00000025 339 0x00010001 0x0000002c 340 0x00010002 0x00000035 341 0x00010003 0x0000003d 342 0x00010004 0x00000045 343 0x00010005 0x0000004e 344 0x00010006 0x00000057 345 0x00010007 0x00000061 346 0x00010008 0x0000006b 347 0x00010009 0x00000076 348 /* Calibration data group 3 */ 349 0x00020000 0x00000029 350 0x00020001 0x00000033 351 0x00020002 0x0000003d 352 0x00020003 0x00000049 353 0x00020004 0x00000056 354 0x00020005 0x00000061 355 0x00020006 0x0000006d 356 /* Calibration data group 4 */ 357 0x00030000 0x00000021 358 0x00030001 0x0000002a 359 0x00030002 0x0000003c 360 0x00030003 0x0000004e>; 361 big-endian; 362 #thermal-sensor-cells = <1>; 363 }; 364 365 dspi: spi@2100000 { 366 compatible = "fsl,ls1021a-v1.0-dspi"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <0x0 0x2100000 0x0 0x10000>; 370 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 371 clock-names = "dspi"; 372 clocks = <&clockgen 4 1>; 373 spi-num-chipselects = <5>; 374 big-endian; 375 status = "disabled"; 376 }; 377 378 i2c0: i2c@2180000 { 379 compatible = "fsl,vf610-i2c"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <0x0 0x2180000 0x0 0x10000>; 383 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&clockgen 4 1>; 385 dmas = <&edma0 1 39>, 386 <&edma0 1 38>; 387 dma-names = "tx", "rx"; 388 status = "disabled"; 389 }; 390 391 i2c1: i2c@2190000 { 392 compatible = "fsl,vf610-i2c"; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 reg = <0x0 0x2190000 0x0 0x10000>; 396 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&clockgen 4 1>; 398 status = "disabled"; 399 }; 400 401 i2c2: i2c@21a0000 { 402 compatible = "fsl,vf610-i2c"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 reg = <0x0 0x21a0000 0x0 0x10000>; 406 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clockgen 4 1>; 408 status = "disabled"; 409 }; 410 411 i2c3: i2c@21b0000 { 412 compatible = "fsl,vf610-i2c"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0x0 0x21b0000 0x0 0x10000>; 416 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clockgen 4 1>; 418 status = "disabled"; 419 }; 420 421 duart0: serial@21c0500 { 422 compatible = "fsl,ns16550", "ns16550a"; 423 reg = <0x00 0x21c0500 0x0 0x100>; 424 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clockgen 4 1>; 426 status = "disabled"; 427 }; 428 429 duart1: serial@21c0600 { 430 compatible = "fsl,ns16550", "ns16550a"; 431 reg = <0x00 0x21c0600 0x0 0x100>; 432 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clockgen 4 1>; 434 status = "disabled"; 435 }; 436 437 duart2: serial@21d0500 { 438 compatible = "fsl,ns16550", "ns16550a"; 439 reg = <0x0 0x21d0500 0x0 0x100>; 440 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clockgen 4 1>; 442 status = "disabled"; 443 }; 444 445 duart3: serial@21d0600 { 446 compatible = "fsl,ns16550", "ns16550a"; 447 reg = <0x0 0x21d0600 0x0 0x100>; 448 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clockgen 4 1>; 450 status = "disabled"; 451 }; 452 453 gpio0: gpio@2300000 { 454 compatible = "fsl,qoriq-gpio"; 455 reg = <0x0 0x2300000 0x0 0x10000>; 456 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 }; 462 463 gpio1: gpio@2310000 { 464 compatible = "fsl,qoriq-gpio"; 465 reg = <0x0 0x2310000 0x0 0x10000>; 466 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 }; 472 473 gpio2: gpio@2320000 { 474 compatible = "fsl,qoriq-gpio"; 475 reg = <0x0 0x2320000 0x0 0x10000>; 476 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 }; 482 483 gpio3: gpio@2330000 { 484 compatible = "fsl,qoriq-gpio"; 485 reg = <0x0 0x2330000 0x0 0x10000>; 486 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 487 gpio-controller; 488 #gpio-cells = <2>; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 }; 492 493 lpuart0: serial@2950000 { 494 compatible = "fsl,ls1021a-lpuart"; 495 reg = <0x0 0x2950000 0x0 0x1000>; 496 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&clockgen 4 0>; 498 clock-names = "ipg"; 499 status = "disabled"; 500 }; 501 502 lpuart1: serial@2960000 { 503 compatible = "fsl,ls1021a-lpuart"; 504 reg = <0x0 0x2960000 0x0 0x1000>; 505 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clockgen 4 1>; 507 clock-names = "ipg"; 508 status = "disabled"; 509 }; 510 511 lpuart2: serial@2970000 { 512 compatible = "fsl,ls1021a-lpuart"; 513 reg = <0x0 0x2970000 0x0 0x1000>; 514 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clockgen 4 1>; 516 clock-names = "ipg"; 517 status = "disabled"; 518 }; 519 520 lpuart3: serial@2980000 { 521 compatible = "fsl,ls1021a-lpuart"; 522 reg = <0x0 0x2980000 0x0 0x1000>; 523 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clockgen 4 1>; 525 clock-names = "ipg"; 526 status = "disabled"; 527 }; 528 529 lpuart4: serial@2990000 { 530 compatible = "fsl,ls1021a-lpuart"; 531 reg = <0x0 0x2990000 0x0 0x1000>; 532 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&clockgen 4 1>; 534 clock-names = "ipg"; 535 status = "disabled"; 536 }; 537 538 lpuart5: serial@29a0000 { 539 compatible = "fsl,ls1021a-lpuart"; 540 reg = <0x0 0x29a0000 0x0 0x1000>; 541 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clockgen 4 1>; 543 clock-names = "ipg"; 544 status = "disabled"; 545 }; 546 547 wdog0: watchdog@2ad0000 { 548 compatible = "fsl,imx21-wdt"; 549 reg = <0x0 0x2ad0000 0x0 0x10000>; 550 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&clockgen 4 1>; 552 big-endian; 553 }; 554 555 edma0: edma@2c00000 { 556 #dma-cells = <2>; 557 compatible = "fsl,vf610-edma"; 558 reg = <0x0 0x2c00000 0x0 0x10000>, 559 <0x0 0x2c10000 0x0 0x10000>, 560 <0x0 0x2c20000 0x0 0x10000>; 561 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "edma-tx", "edma-err"; 564 dma-channels = <32>; 565 big-endian; 566 clock-names = "dmamux0", "dmamux1"; 567 clocks = <&clockgen 4 1>, 568 <&clockgen 4 1>; 569 }; 570 571 usb0: usb@2f00000 { 572 compatible = "snps,dwc3"; 573 reg = <0x0 0x2f00000 0x0 0x10000>; 574 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 575 dr_mode = "host"; 576 snps,quirk-frame-length-adjustment = <0x20>; 577 snps,dis_rxdet_inp3_quirk; 578 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 579 }; 580 581 usb1: usb@3000000 { 582 compatible = "snps,dwc3"; 583 reg = <0x0 0x3000000 0x0 0x10000>; 584 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 585 dr_mode = "host"; 586 snps,quirk-frame-length-adjustment = <0x20>; 587 snps,dis_rxdet_inp3_quirk; 588 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 589 }; 590 591 usb2: usb@3100000 { 592 compatible = "snps,dwc3"; 593 reg = <0x0 0x3100000 0x0 0x10000>; 594 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 595 dr_mode = "host"; 596 snps,quirk-frame-length-adjustment = <0x20>; 597 snps,dis_rxdet_inp3_quirk; 598 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 599 }; 600 601 sata: sata@3200000 { 602 compatible = "fsl,ls1046a-ahci"; 603 reg = <0x0 0x3200000 0x0 0x10000>, 604 <0x0 0x20140520 0x0 0x4>; 605 reg-names = "ahci", "sata-ecc"; 606 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&clockgen 4 1>; 608 }; 609 610 msi1: msi-controller@1580000 { 611 compatible = "fsl,ls1046a-msi"; 612 msi-controller; 613 reg = <0x0 0x1580000 0x0 0x10000>; 614 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 618 }; 619 620 msi2: msi-controller@1590000 { 621 compatible = "fsl,ls1046a-msi"; 622 msi-controller; 623 reg = <0x0 0x1590000 0x0 0x10000>; 624 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 628 }; 629 630 msi3: msi-controller@15a0000 { 631 compatible = "fsl,ls1046a-msi"; 632 msi-controller; 633 reg = <0x0 0x15a0000 0x0 0x10000>; 634 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 638 }; 639 640 pcie@3400000 { 641 compatible = "fsl,ls1046a-pcie"; 642 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 643 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 644 reg-names = "regs", "config"; 645 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 646 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 647 interrupt-names = "aer", "pme"; 648 #address-cells = <3>; 649 #size-cells = <2>; 650 device_type = "pci"; 651 dma-coherent; 652 num-viewport = <8>; 653 bus-range = <0x0 0xff>; 654 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 655 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 656 msi-parent = <&msi1>, <&msi2>, <&msi3>; 657 #interrupt-cells = <1>; 658 interrupt-map-mask = <0 0 0 7>; 659 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 660 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 661 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 662 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 663 status = "disabled"; 664 }; 665 666 pcie_ep@3400000 { 667 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 668 reg = <0x00 0x03400000 0x0 0x00100000 669 0x40 0x00000000 0x8 0x00000000>; 670 reg-names = "regs", "addr_space"; 671 num-ib-windows = <6>; 672 num-ob-windows = <8>; 673 status = "disabled"; 674 }; 675 676 pcie@3500000 { 677 compatible = "fsl,ls1046a-pcie"; 678 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 679 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 680 reg-names = "regs", "config"; 681 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 682 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 683 interrupt-names = "aer", "pme"; 684 #address-cells = <3>; 685 #size-cells = <2>; 686 device_type = "pci"; 687 dma-coherent; 688 num-viewport = <8>; 689 bus-range = <0x0 0xff>; 690 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 691 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 692 msi-parent = <&msi2>, <&msi3>, <&msi1>; 693 #interrupt-cells = <1>; 694 interrupt-map-mask = <0 0 0 7>; 695 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 696 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 697 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 698 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 699 status = "disabled"; 700 }; 701 702 pcie_ep@3500000 { 703 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 704 reg = <0x00 0x03500000 0x0 0x00100000 705 0x48 0x00000000 0x8 0x00000000>; 706 reg-names = "regs", "addr_space"; 707 num-ib-windows = <6>; 708 num-ob-windows = <8>; 709 status = "disabled"; 710 }; 711 712 pcie@3600000 { 713 compatible = "fsl,ls1046a-pcie"; 714 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 715 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 716 reg-names = "regs", "config"; 717 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 718 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 719 interrupt-names = "aer", "pme"; 720 #address-cells = <3>; 721 #size-cells = <2>; 722 device_type = "pci"; 723 dma-coherent; 724 num-viewport = <8>; 725 bus-range = <0x0 0xff>; 726 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 727 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 728 msi-parent = <&msi3>, <&msi1>, <&msi2>; 729 #interrupt-cells = <1>; 730 interrupt-map-mask = <0 0 0 7>; 731 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 732 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 733 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 734 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 735 status = "disabled"; 736 }; 737 738 pcie_ep@3600000 { 739 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 740 reg = <0x00 0x03600000 0x0 0x00100000 741 0x50 0x00000000 0x8 0x00000000>; 742 reg-names = "regs", "addr_space"; 743 num-ib-windows = <6>; 744 num-ob-windows = <8>; 745 status = "disabled"; 746 }; 747 748 qdma: dma-controller@8380000 { 749 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 750 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 751 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 752 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 753 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 758 interrupt-names = "qdma-error", "qdma-queue0", 759 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 760 dma-channels = <8>; 761 block-number = <1>; 762 block-offset = <0x10000>; 763 fsl,dma-queues = <2>; 764 status-sizes = <64>; 765 queue-sizes = <64 64>; 766 big-endian; 767 }; 768 }; 769 770 reserved-memory { 771 #address-cells = <2>; 772 #size-cells = <2>; 773 ranges; 774 775 bman_fbpr: bman-fbpr { 776 compatible = "shared-dma-pool"; 777 size = <0 0x1000000>; 778 alignment = <0 0x1000000>; 779 no-map; 780 }; 781 782 qman_fqd: qman-fqd { 783 compatible = "shared-dma-pool"; 784 size = <0 0x800000>; 785 alignment = <0 0x800000>; 786 no-map; 787 }; 788 789 qman_pfdr: qman-pfdr { 790 compatible = "shared-dma-pool"; 791 size = <0 0x2000000>; 792 alignment = <0 0x2000000>; 793 no-map; 794 }; 795 }; 796 797 firmware { 798 optee { 799 compatible = "linaro,optee-tz"; 800 method = "smc"; 801 }; 802 }; 803}; 804 805#include "qoriq-qman-portals.dtsi" 806#include "qoriq-bman-portals.dtsi" 807
