1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "ext-osc32k"; 143 }; 144 145 psci { 146 compatible = "arm,psci-0.2"; 147 method = "smc"; 148 }; 149 150 sound: sound { 151 compatible = "simple-audio-card"; 152 simple-audio-card,name = "sun50i-a64-audio"; 153 simple-audio-card,format = "i2s"; 154 simple-audio-card,frame-master = <&cpudai>; 155 simple-audio-card,bitclock-master = <&cpudai>; 156 simple-audio-card,mclk-fs = <128>; 157 simple-audio-card,aux-devs = <&codec_analog>; 158 simple-audio-card,routing = 159 "Left DAC", "AIF1 Slot 0 Left", 160 "Right DAC", "AIF1 Slot 0 Right", 161 "AIF1 Slot 0 Left ADC", "Left ADC", 162 "AIF1 Slot 0 Right ADC", "Right ADC"; 163 status = "disabled"; 164 165 cpudai: simple-audio-card,cpu { 166 sound-dai = <&dai>; 167 }; 168 169 link_codec: simple-audio-card,codec { 170 sound-dai = <&codec>; 171 }; 172 }; 173 174 sound_spdif { 175 compatible = "simple-audio-card"; 176 simple-audio-card,name = "On-board SPDIF"; 177 178 simple-audio-card,cpu { 179 sound-dai = <&spdif>; 180 }; 181 182 simple-audio-card,codec { 183 sound-dai = <&spdif_out>; 184 }; 185 }; 186 187 spdif_out: spdif-out { 188 #sound-dai-cells = <0>; 189 compatible = "linux,spdif-dit"; 190 }; 191 192 timer { 193 compatible = "arm,armv8-timer"; 194 allwinner,erratum-unknown1; 195 interrupts = <GIC_PPI 13 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 197 <GIC_PPI 14 198 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 199 <GIC_PPI 11 200 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 201 <GIC_PPI 10 202 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 }; 204 205 soc { 206 compatible = "simple-bus"; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges; 210 211 bus@1000000 { 212 compatible = "allwinner,sun50i-a64-de2"; 213 reg = <0x1000000 0x400000>; 214 allwinner,sram = <&de2_sram 1>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0 0x1000000 0x400000>; 218 219 display_clocks: clock@0 { 220 compatible = "allwinner,sun50i-a64-de2-clk"; 221 reg = <0x0 0x100000>; 222 clocks = <&ccu CLK_BUS_DE>, 223 <&ccu CLK_DE>; 224 clock-names = "bus", 225 "mod"; 226 resets = <&ccu RST_BUS_DE>; 227 #clock-cells = <1>; 228 #reset-cells = <1>; 229 }; 230 231 mixer0: mixer@100000 { 232 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 233 reg = <0x100000 0x100000>; 234 clocks = <&display_clocks CLK_BUS_MIXER0>, 235 <&display_clocks CLK_MIXER0>; 236 clock-names = "bus", 237 "mod"; 238 resets = <&display_clocks RST_MIXER0>; 239 240 ports { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 mixer0_out: port@1 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 reg = <1>; 248 249 mixer0_out_tcon0: endpoint@0 { 250 reg = <0>; 251 remote-endpoint = <&tcon0_in_mixer0>; 252 }; 253 254 mixer0_out_tcon1: endpoint@1 { 255 reg = <1>; 256 remote-endpoint = <&tcon1_in_mixer0>; 257 }; 258 }; 259 }; 260 }; 261 262 mixer1: mixer@200000 { 263 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 264 reg = <0x200000 0x100000>; 265 clocks = <&display_clocks CLK_BUS_MIXER1>, 266 <&display_clocks CLK_MIXER1>; 267 clock-names = "bus", 268 "mod"; 269 resets = <&display_clocks RST_MIXER1>; 270 271 ports { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 mixer1_out: port@1 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <1>; 279 280 mixer1_out_tcon0: endpoint@0 { 281 reg = <0>; 282 remote-endpoint = <&tcon0_in_mixer1>; 283 }; 284 285 mixer1_out_tcon1: endpoint@1 { 286 reg = <1>; 287 remote-endpoint = <&tcon1_in_mixer1>; 288 }; 289 }; 290 }; 291 }; 292 }; 293 294 syscon: syscon@1c00000 { 295 compatible = "allwinner,sun50i-a64-system-control"; 296 reg = <0x01c00000 0x1000>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 ranges; 300 301 sram_c: sram@18000 { 302 compatible = "mmio-sram"; 303 reg = <0x00018000 0x28000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges = <0 0x00018000 0x28000>; 307 308 de2_sram: sram-section@0 { 309 compatible = "allwinner,sun50i-a64-sram-c"; 310 reg = <0x0000 0x28000>; 311 }; 312 }; 313 314 sram_c1: sram@1d00000 { 315 compatible = "mmio-sram"; 316 reg = <0x01d00000 0x40000>; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges = <0 0x01d00000 0x40000>; 320 321 ve_sram: sram-section@0 { 322 compatible = "allwinner,sun50i-a64-sram-c1", 323 "allwinner,sun4i-a10-sram-c1"; 324 reg = <0x000000 0x40000>; 325 }; 326 }; 327 }; 328 329 dma: dma-controller@1c02000 { 330 compatible = "allwinner,sun50i-a64-dma"; 331 reg = <0x01c02000 0x1000>; 332 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_DMA>; 334 dma-channels = <8>; 335 dma-requests = <27>; 336 resets = <&ccu RST_BUS_DMA>; 337 #dma-cells = <1>; 338 }; 339 340 tcon0: lcd-controller@1c0c000 { 341 compatible = "allwinner,sun50i-a64-tcon-lcd", 342 "allwinner,sun8i-a83t-tcon-lcd"; 343 reg = <0x01c0c000 0x1000>; 344 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 346 clock-names = "ahb", "tcon-ch0"; 347 clock-output-names = "tcon-pixel-clock"; 348 #clock-cells = <0>; 349 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 350 reset-names = "lcd", "lvds"; 351 352 ports { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 356 tcon0_in: port@0 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 reg = <0>; 360 361 tcon0_in_mixer0: endpoint@0 { 362 reg = <0>; 363 remote-endpoint = <&mixer0_out_tcon0>; 364 }; 365 366 tcon0_in_mixer1: endpoint@1 { 367 reg = <1>; 368 remote-endpoint = <&mixer1_out_tcon0>; 369 }; 370 }; 371 372 tcon0_out: port@1 { 373 #address-cells = <1>; 374 #size-cells = <0>; 375 reg = <1>; 376 }; 377 }; 378 }; 379 380 tcon1: lcd-controller@1c0d000 { 381 compatible = "allwinner,sun50i-a64-tcon-tv", 382 "allwinner,sun8i-a83t-tcon-tv"; 383 reg = <0x01c0d000 0x1000>; 384 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 386 clock-names = "ahb", "tcon-ch1"; 387 resets = <&ccu RST_BUS_TCON1>; 388 reset-names = "lcd"; 389 390 ports { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 tcon1_in: port@0 { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 reg = <0>; 398 399 tcon1_in_mixer0: endpoint@0 { 400 reg = <0>; 401 remote-endpoint = <&mixer0_out_tcon1>; 402 }; 403 404 tcon1_in_mixer1: endpoint@1 { 405 reg = <1>; 406 remote-endpoint = <&mixer1_out_tcon1>; 407 }; 408 }; 409 410 tcon1_out: port@1 { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <1>; 414 415 tcon1_out_hdmi: endpoint@1 { 416 reg = <1>; 417 remote-endpoint = <&hdmi_in_tcon1>; 418 }; 419 }; 420 }; 421 }; 422 423 video-codec@1c0e000 { 424 compatible = "allwinner,sun50i-a64-video-engine"; 425 reg = <0x01c0e000 0x1000>; 426 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 427 <&ccu CLK_DRAM_VE>; 428 clock-names = "ahb", "mod", "ram"; 429 resets = <&ccu RST_BUS_VE>; 430 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 431 allwinner,sram = <&ve_sram 1>; 432 }; 433 434 mmc0: mmc@1c0f000 { 435 compatible = "allwinner,sun50i-a64-mmc"; 436 reg = <0x01c0f000 0x1000>; 437 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 438 clock-names = "ahb", "mmc"; 439 resets = <&ccu RST_BUS_MMC0>; 440 reset-names = "ahb"; 441 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 442 max-frequency = <150000000>; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 mmc1: mmc@1c10000 { 449 compatible = "allwinner,sun50i-a64-mmc"; 450 reg = <0x01c10000 0x1000>; 451 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 452 clock-names = "ahb", "mmc"; 453 resets = <&ccu RST_BUS_MMC1>; 454 reset-names = "ahb"; 455 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 456 max-frequency = <150000000>; 457 status = "disabled"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 }; 461 462 mmc2: mmc@1c11000 { 463 compatible = "allwinner,sun50i-a64-emmc"; 464 reg = <0x01c11000 0x1000>; 465 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 466 clock-names = "ahb", "mmc"; 467 resets = <&ccu RST_BUS_MMC2>; 468 reset-names = "ahb"; 469 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 470 max-frequency = <200000000>; 471 status = "disabled"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 }; 475 476 sid: eeprom@1c14000 { 477 compatible = "allwinner,sun50i-a64-sid"; 478 reg = <0x1c14000 0x400>; 479 }; 480 481 usb_otg: usb@1c19000 { 482 compatible = "allwinner,sun8i-a33-musb"; 483 reg = <0x01c19000 0x0400>; 484 clocks = <&ccu CLK_BUS_OTG>; 485 resets = <&ccu RST_BUS_OTG>; 486 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "mc"; 488 phys = <&usbphy 0>; 489 phy-names = "usb"; 490 extcon = <&usbphy 0>; 491 dr_mode = "otg"; 492 status = "disabled"; 493 }; 494 495 usbphy: phy@1c19400 { 496 compatible = "allwinner,sun50i-a64-usb-phy"; 497 reg = <0x01c19400 0x14>, 498 <0x01c1a800 0x4>, 499 <0x01c1b800 0x4>; 500 reg-names = "phy_ctrl", 501 "pmu0", 502 "pmu1"; 503 clocks = <&ccu CLK_USB_PHY0>, 504 <&ccu CLK_USB_PHY1>; 505 clock-names = "usb0_phy", 506 "usb1_phy"; 507 resets = <&ccu RST_USB_PHY0>, 508 <&ccu RST_USB_PHY1>; 509 reset-names = "usb0_reset", 510 "usb1_reset"; 511 status = "disabled"; 512 #phy-cells = <1>; 513 }; 514 515 ehci0: usb@1c1a000 { 516 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 517 reg = <0x01c1a000 0x100>; 518 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&ccu CLK_BUS_OHCI0>, 520 <&ccu CLK_BUS_EHCI0>, 521 <&ccu CLK_USB_OHCI0>; 522 resets = <&ccu RST_BUS_OHCI0>, 523 <&ccu RST_BUS_EHCI0>; 524 status = "disabled"; 525 }; 526 527 ohci0: usb@1c1a400 { 528 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 529 reg = <0x01c1a400 0x100>; 530 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&ccu CLK_BUS_OHCI0>, 532 <&ccu CLK_USB_OHCI0>; 533 resets = <&ccu RST_BUS_OHCI0>; 534 status = "disabled"; 535 }; 536 537 ehci1: usb@1c1b000 { 538 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 539 reg = <0x01c1b000 0x100>; 540 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&ccu CLK_BUS_OHCI1>, 542 <&ccu CLK_BUS_EHCI1>, 543 <&ccu CLK_USB_OHCI1>; 544 resets = <&ccu RST_BUS_OHCI1>, 545 <&ccu RST_BUS_EHCI1>; 546 phys = <&usbphy 1>; 547 phy-names = "usb"; 548 status = "disabled"; 549 }; 550 551 ohci1: usb@1c1b400 { 552 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 553 reg = <0x01c1b400 0x100>; 554 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&ccu CLK_BUS_OHCI1>, 556 <&ccu CLK_USB_OHCI1>; 557 resets = <&ccu RST_BUS_OHCI1>; 558 phys = <&usbphy 1>; 559 phy-names = "usb"; 560 status = "disabled"; 561 }; 562 563 ccu: clock@1c20000 { 564 compatible = "allwinner,sun50i-a64-ccu"; 565 reg = <0x01c20000 0x400>; 566 clocks = <&osc24M>, <&rtc 0>; 567 clock-names = "hosc", "losc"; 568 #clock-cells = <1>; 569 #reset-cells = <1>; 570 }; 571 572 pio: pinctrl@1c20800 { 573 compatible = "allwinner,sun50i-a64-pinctrl"; 574 reg = <0x01c20800 0x400>; 575 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 579 clock-names = "apb", "hosc", "losc"; 580 gpio-controller; 581 #gpio-cells = <3>; 582 interrupt-controller; 583 #interrupt-cells = <3>; 584 585 csi_pins: csi-pins { 586 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 587 "PE7", "PE8", "PE9", "PE10", "PE11"; 588 function = "csi"; 589 }; 590 591 /omit-if-no-ref/ 592 csi_mclk_pin: csi-mclk-pin { 593 pins = "PE1"; 594 function = "csi"; 595 }; 596 597 i2c0_pins: i2c0-pins { 598 pins = "PH0", "PH1"; 599 function = "i2c0"; 600 }; 601 602 i2c1_pins: i2c1-pins { 603 pins = "PH2", "PH3"; 604 function = "i2c1"; 605 }; 606 607 /omit-if-no-ref/ 608 lcd_rgb666_pins: lcd-rgb666-pins { 609 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 610 "PD5", "PD6", "PD7", "PD8", "PD9", 611 "PD10", "PD11", "PD12", "PD13", 612 "PD14", "PD15", "PD16", "PD17", 613 "PD18", "PD19", "PD20", "PD21"; 614 function = "lcd0"; 615 }; 616 617 mmc0_pins: mmc0-pins { 618 pins = "PF0", "PF1", "PF2", "PF3", 619 "PF4", "PF5"; 620 function = "mmc0"; 621 drive-strength = <30>; 622 bias-pull-up; 623 }; 624 625 mmc1_pins: mmc1-pins { 626 pins = "PG0", "PG1", "PG2", "PG3", 627 "PG4", "PG5"; 628 function = "mmc1"; 629 drive-strength = <30>; 630 bias-pull-up; 631 }; 632 633 mmc2_pins: mmc2-pins { 634 pins = "PC5", "PC6", "PC8", "PC9", 635 "PC10","PC11", "PC12", "PC13", 636 "PC14", "PC15", "PC16"; 637 function = "mmc2"; 638 drive-strength = <30>; 639 bias-pull-up; 640 }; 641 642 mmc2_ds_pin: mmc2-ds-pin { 643 pins = "PC1"; 644 function = "mmc2"; 645 drive-strength = <30>; 646 bias-pull-up; 647 }; 648 649 pwm_pin: pwm-pin { 650 pins = "PD22"; 651 function = "pwm"; 652 }; 653 654 rmii_pins: rmii-pins { 655 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 656 "PD18", "PD19", "PD20", "PD22", "PD23"; 657 function = "emac"; 658 drive-strength = <40>; 659 }; 660 661 rgmii_pins: rgmii-pins { 662 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 663 "PD13", "PD15", "PD16", "PD17", "PD18", 664 "PD19", "PD20", "PD21", "PD22", "PD23"; 665 function = "emac"; 666 drive-strength = <40>; 667 }; 668 669 spdif_tx_pin: spdif-tx-pin { 670 pins = "PH8"; 671 function = "spdif"; 672 }; 673 674 spi0_pins: spi0-pins { 675 pins = "PC0", "PC1", "PC2", "PC3"; 676 function = "spi0"; 677 }; 678 679 spi1_pins: spi1-pins { 680 pins = "PD0", "PD1", "PD2", "PD3"; 681 function = "spi1"; 682 }; 683 684 uart0_pb_pins: uart0-pb-pins { 685 pins = "PB8", "PB9"; 686 function = "uart0"; 687 }; 688 689 uart1_pins: uart1-pins { 690 pins = "PG6", "PG7"; 691 function = "uart1"; 692 }; 693 694 uart1_rts_cts_pins: uart1-rts-cts-pins { 695 pins = "PG8", "PG9"; 696 function = "uart1"; 697 }; 698 699 uart2_pins: uart2-pins { 700 pins = "PB0", "PB1"; 701 function = "uart2"; 702 }; 703 704 uart3_pins: uart3-pins { 705 pins = "PD0", "PD1"; 706 function = "uart3"; 707 }; 708 709 uart4_pins: uart4-pins { 710 pins = "PD2", "PD3"; 711 function = "uart4"; 712 }; 713 714 uart4_rts_cts_pins: uart4-rts-cts-pins { 715 pins = "PD4", "PD5"; 716 function = "uart4"; 717 }; 718 }; 719 720 spdif: spdif@1c21000 { 721 #sound-dai-cells = <0>; 722 compatible = "allwinner,sun50i-a64-spdif", 723 "allwinner,sun8i-h3-spdif"; 724 reg = <0x01c21000 0x400>; 725 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 727 resets = <&ccu RST_BUS_SPDIF>; 728 clock-names = "apb", "spdif"; 729 dmas = <&dma 2>; 730 dma-names = "tx"; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&spdif_tx_pin>; 733 status = "disabled"; 734 }; 735 736 lradc: lradc@1c21800 { 737 compatible = "allwinner,sun50i-a64-lradc", 738 "allwinner,sun8i-a83t-r-lradc"; 739 reg = <0x01c21800 0x400>; 740 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 741 status = "disabled"; 742 }; 743 744 i2s0: i2s@1c22000 { 745 #sound-dai-cells = <0>; 746 compatible = "allwinner,sun50i-a64-i2s", 747 "allwinner,sun8i-h3-i2s"; 748 reg = <0x01c22000 0x400>; 749 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 751 clock-names = "apb", "mod"; 752 resets = <&ccu RST_BUS_I2S0>; 753 dma-names = "rx", "tx"; 754 dmas = <&dma 3>, <&dma 3>; 755 status = "disabled"; 756 }; 757 758 i2s1: i2s@1c22400 { 759 #sound-dai-cells = <0>; 760 compatible = "allwinner,sun50i-a64-i2s", 761 "allwinner,sun8i-h3-i2s"; 762 reg = <0x01c22400 0x400>; 763 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 765 clock-names = "apb", "mod"; 766 resets = <&ccu RST_BUS_I2S1>; 767 dma-names = "rx", "tx"; 768 dmas = <&dma 4>, <&dma 4>; 769 status = "disabled"; 770 }; 771 772 dai: dai@1c22c00 { 773 #sound-dai-cells = <0>; 774 compatible = "allwinner,sun50i-a64-codec-i2s"; 775 reg = <0x01c22c00 0x200>; 776 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 778 clock-names = "apb", "mod"; 779 resets = <&ccu RST_BUS_CODEC>; 780 dmas = <&dma 15>, <&dma 15>; 781 dma-names = "rx", "tx"; 782 status = "disabled"; 783 }; 784 785 codec: codec@1c22e00 { 786 #sound-dai-cells = <0>; 787 compatible = "allwinner,sun8i-a33-codec"; 788 reg = <0x01c22e00 0x600>; 789 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 791 clock-names = "bus", "mod"; 792 status = "disabled"; 793 }; 794 795 uart0: serial@1c28000 { 796 compatible = "snps,dw-apb-uart"; 797 reg = <0x01c28000 0x400>; 798 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 799 reg-shift = <2>; 800 reg-io-width = <4>; 801 clocks = <&ccu CLK_BUS_UART0>; 802 resets = <&ccu RST_BUS_UART0>; 803 status = "disabled"; 804 }; 805 806 uart1: serial@1c28400 { 807 compatible = "snps,dw-apb-uart"; 808 reg = <0x01c28400 0x400>; 809 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 810 reg-shift = <2>; 811 reg-io-width = <4>; 812 clocks = <&ccu CLK_BUS_UART1>; 813 resets = <&ccu RST_BUS_UART1>; 814 status = "disabled"; 815 }; 816 817 uart2: serial@1c28800 { 818 compatible = "snps,dw-apb-uart"; 819 reg = <0x01c28800 0x400>; 820 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 821 reg-shift = <2>; 822 reg-io-width = <4>; 823 clocks = <&ccu CLK_BUS_UART2>; 824 resets = <&ccu RST_BUS_UART2>; 825 status = "disabled"; 826 }; 827 828 uart3: serial@1c28c00 { 829 compatible = "snps,dw-apb-uart"; 830 reg = <0x01c28c00 0x400>; 831 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 832 reg-shift = <2>; 833 reg-io-width = <4>; 834 clocks = <&ccu CLK_BUS_UART3>; 835 resets = <&ccu RST_BUS_UART3>; 836 status = "disabled"; 837 }; 838 839 uart4: serial@1c29000 { 840 compatible = "snps,dw-apb-uart"; 841 reg = <0x01c29000 0x400>; 842 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 843 reg-shift = <2>; 844 reg-io-width = <4>; 845 clocks = <&ccu CLK_BUS_UART4>; 846 resets = <&ccu RST_BUS_UART4>; 847 status = "disabled"; 848 }; 849 850 i2c0: i2c@1c2ac00 { 851 compatible = "allwinner,sun6i-a31-i2c"; 852 reg = <0x01c2ac00 0x400>; 853 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&ccu CLK_BUS_I2C0>; 855 resets = <&ccu RST_BUS_I2C0>; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&i2c0_pins>; 858 status = "disabled"; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 }; 862 863 i2c1: i2c@1c2b000 { 864 compatible = "allwinner,sun6i-a31-i2c"; 865 reg = <0x01c2b000 0x400>; 866 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&ccu CLK_BUS_I2C1>; 868 resets = <&ccu RST_BUS_I2C1>; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&i2c1_pins>; 871 status = "disabled"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 }; 875 876 i2c2: i2c@1c2b400 { 877 compatible = "allwinner,sun6i-a31-i2c"; 878 reg = <0x01c2b400 0x400>; 879 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&ccu CLK_BUS_I2C2>; 881 resets = <&ccu RST_BUS_I2C2>; 882 status = "disabled"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 }; 886 887 888 spi0: spi@1c68000 { 889 compatible = "allwinner,sun8i-h3-spi"; 890 reg = <0x01c68000 0x1000>; 891 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 893 clock-names = "ahb", "mod"; 894 dmas = <&dma 23>, <&dma 23>; 895 dma-names = "rx", "tx"; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&spi0_pins>; 898 resets = <&ccu RST_BUS_SPI0>; 899 status = "disabled"; 900 num-cs = <1>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 }; 904 905 spi1: spi@1c69000 { 906 compatible = "allwinner,sun8i-h3-spi"; 907 reg = <0x01c69000 0x1000>; 908 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 910 clock-names = "ahb", "mod"; 911 dmas = <&dma 24>, <&dma 24>; 912 dma-names = "rx", "tx"; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&spi1_pins>; 915 resets = <&ccu RST_BUS_SPI1>; 916 status = "disabled"; 917 num-cs = <1>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 }; 921 922 emac: ethernet@1c30000 { 923 compatible = "allwinner,sun50i-a64-emac"; 924 syscon = <&syscon>; 925 reg = <0x01c30000 0x10000>; 926 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-names = "macirq"; 928 resets = <&ccu RST_BUS_EMAC>; 929 reset-names = "stmmaceth"; 930 clocks = <&ccu CLK_BUS_EMAC>; 931 clock-names = "stmmaceth"; 932 status = "disabled"; 933 934 mdio: mdio { 935 compatible = "snps,dwmac-mdio"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 }; 939 }; 940 941 mali: gpu@1c40000 { 942 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 943 reg = <0x01c40000 0x10000>; 944 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "gp", 952 "gpmmu", 953 "pp0", 954 "ppmmu0", 955 "pp1", 956 "ppmmu1", 957 "pmu"; 958 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 959 clock-names = "bus", "core"; 960 resets = <&ccu RST_BUS_GPU>; 961 }; 962 963 gic: interrupt-controller@1c81000 { 964 compatible = "arm,gic-400"; 965 reg = <0x01c81000 0x1000>, 966 <0x01c82000 0x2000>, 967 <0x01c84000 0x2000>, 968 <0x01c86000 0x2000>; 969 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 970 interrupt-controller; 971 #interrupt-cells = <3>; 972 }; 973 974 pwm: pwm@1c21400 { 975 compatible = "allwinner,sun50i-a64-pwm", 976 "allwinner,sun5i-a13-pwm"; 977 reg = <0x01c21400 0x400>; 978 clocks = <&osc24M>; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&pwm_pin>; 981 #pwm-cells = <3>; 982 status = "disabled"; 983 }; 984 985 csi: csi@1cb0000 { 986 compatible = "allwinner,sun50i-a64-csi"; 987 reg = <0x01cb0000 0x1000>; 988 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&ccu CLK_BUS_CSI>, 990 <&ccu CLK_CSI_SCLK>, 991 <&ccu CLK_DRAM_CSI>; 992 clock-names = "bus", "mod", "ram"; 993 resets = <&ccu RST_BUS_CSI>; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&csi_pins>; 996 status = "disabled"; 997 }; 998 999 hdmi: hdmi@1ee0000 { 1000 compatible = "allwinner,sun50i-a64-dw-hdmi", 1001 "allwinner,sun8i-a83t-dw-hdmi"; 1002 reg = <0x01ee0000 0x10000>; 1003 reg-io-width = <1>; 1004 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1006 <&ccu CLK_HDMI>; 1007 clock-names = "iahb", "isfr", "tmds"; 1008 resets = <&ccu RST_BUS_HDMI1>; 1009 reset-names = "ctrl"; 1010 phys = <&hdmi_phy>; 1011 phy-names = "phy"; 1012 status = "disabled"; 1013 1014 ports { 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 1018 hdmi_in: port@0 { 1019 reg = <0>; 1020 1021 hdmi_in_tcon1: endpoint { 1022 remote-endpoint = <&tcon1_out_hdmi>; 1023 }; 1024 }; 1025 1026 hdmi_out: port@1 { 1027 reg = <1>; 1028 }; 1029 }; 1030 }; 1031 1032 hdmi_phy: hdmi-phy@1ef0000 { 1033 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1034 reg = <0x01ef0000 0x10000>; 1035 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1036 <&ccu 7>; 1037 clock-names = "bus", "mod", "pll-0"; 1038 resets = <&ccu RST_BUS_HDMI0>; 1039 reset-names = "phy"; 1040 #phy-cells = <0>; 1041 }; 1042 1043 rtc: rtc@1f00000 { 1044 compatible = "allwinner,sun50i-a64-rtc", 1045 "allwinner,sun8i-h3-rtc"; 1046 reg = <0x01f00000 0x400>; 1047 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1049 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1050 clocks = <&osc32k>; 1051 #clock-cells = <1>; 1052 }; 1053 1054 r_intc: interrupt-controller@1f00c00 { 1055 compatible = "allwinner,sun50i-a64-r-intc", 1056 "allwinner,sun6i-a31-r-intc"; 1057 interrupt-controller; 1058 #interrupt-cells = <2>; 1059 reg = <0x01f00c00 0x400>; 1060 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1061 }; 1062 1063 r_ccu: clock@1f01400 { 1064 compatible = "allwinner,sun50i-a64-r-ccu"; 1065 reg = <0x01f01400 0x100>; 1066 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; 1067 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1068 #clock-cells = <1>; 1069 #reset-cells = <1>; 1070 }; 1071 1072 codec_analog: codec-analog@1f015c0 { 1073 compatible = "allwinner,sun50i-a64-codec-analog"; 1074 reg = <0x01f015c0 0x4>; 1075 status = "disabled"; 1076 }; 1077 1078 r_i2c: i2c@1f02400 { 1079 compatible = "allwinner,sun50i-a64-i2c", 1080 "allwinner,sun6i-a31-i2c"; 1081 reg = <0x01f02400 0x400>; 1082 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&r_ccu CLK_APB0_I2C>; 1084 resets = <&r_ccu RST_APB0_I2C>; 1085 status = "disabled"; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 }; 1089 1090 r_ir: ir@1f02000 { 1091 compatible = "allwinner,sun50i-a64-ir", 1092 "allwinner,sun6i-a31-ir"; 1093 reg = <0x01f02000 0x400>; 1094 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1095 clock-names = "apb", "ir"; 1096 resets = <&r_ccu RST_APB0_IR>; 1097 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&r_ir_rx_pin>; 1100 status = "disabled"; 1101 }; 1102 1103 r_pwm: pwm@1f03800 { 1104 compatible = "allwinner,sun50i-a64-pwm", 1105 "allwinner,sun5i-a13-pwm"; 1106 reg = <0x01f03800 0x400>; 1107 clocks = <&osc24M>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&r_pwm_pin>; 1110 #pwm-cells = <3>; 1111 status = "disabled"; 1112 }; 1113 1114 r_pio: pinctrl@1f02c00 { 1115 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1116 reg = <0x01f02c00 0x400>; 1117 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1119 clock-names = "apb", "hosc", "losc"; 1120 gpio-controller; 1121 #gpio-cells = <3>; 1122 interrupt-controller; 1123 #interrupt-cells = <3>; 1124 1125 r_i2c_pl89_pins: r-i2c-pl89-pins { 1126 pins = "PL8", "PL9"; 1127 function = "s_i2c"; 1128 }; 1129 1130 r_ir_rx_pin: r-ir-rx-pin { 1131 pins = "PL11"; 1132 function = "s_cir_rx"; 1133 }; 1134 1135 r_pwm_pin: r-pwm-pin { 1136 pins = "PL10"; 1137 function = "s_pwm"; 1138 }; 1139 1140 r_rsb_pins: r-rsb-pins { 1141 pins = "PL0", "PL1"; 1142 function = "s_rsb"; 1143 }; 1144 }; 1145 1146 r_rsb: rsb@1f03400 { 1147 compatible = "allwinner,sun8i-a23-rsb"; 1148 reg = <0x01f03400 0x400>; 1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&r_ccu 6>; 1151 clock-frequency = <3000000>; 1152 resets = <&r_ccu 2>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&r_rsb_pins>; 1155 status = "disabled"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 }; 1159 1160 wdt0: watchdog@1c20ca0 { 1161 compatible = "allwinner,sun50i-a64-wdt", 1162 "allwinner,sun6i-a31-wdt"; 1163 reg = <0x01c20ca0 0x20>; 1164 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&osc24M>; 1166 }; 1167 }; 1168}; 1169
