1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4 // Copyright 2008 Openmoko, Inc.
5 // Copyright 2008 Simtec Electronics
6 // Ben Dooks <ben@simtec.co.uk>
7 // http://armlinux.simtec.co.uk/
8
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/fb.h>
12 #include <linux/gpio.h>
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/dm9000.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/serial_core.h>
19 #include <linux/serial_s3c.h>
20 #include <linux/types.h>
21
22 #include <asm/mach-types.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach/map.h>
25
26 #include <mach/map.h>
27 #include <mach/regs-gpio.h>
28 #include <mach/gpio-samsung.h>
29
30 #include <plat/adc.h>
31 #include <plat/cpu.h>
32 #include <plat/devs.h>
33 #include <plat/fb.h>
34 #include <linux/platform_data/mtd-nand-s3c2410.h>
35 #include <linux/platform_data/mmc-sdhci-s3c.h>
36 #include <plat/sdhci.h>
37 #include <linux/platform_data/touchscreen-s3c2410.h>
38 #include <mach/irqs.h>
39
40 #include <video/platform_lcd.h>
41 #include <video/samsung_fimd.h>
42 #include <plat/samsung-time.h>
43
44 #include "common.h"
45 #include "regs-modem.h"
46 #include "regs-srom.h"
47
48 #define UCON S3C2410_UCON_DEFAULT
49 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
50 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
51
52 static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
53 [0] = {
54 .hwport = 0,
55 .flags = 0,
56 .ucon = UCON,
57 .ulcon = ULCON,
58 .ufcon = UFCON,
59 },
60 [1] = {
61 .hwport = 1,
62 .flags = 0,
63 .ucon = UCON,
64 .ulcon = ULCON,
65 .ufcon = UFCON,
66 },
67 [2] = {
68 .hwport = 2,
69 .flags = 0,
70 .ucon = UCON,
71 .ulcon = ULCON,
72 .ufcon = UFCON,
73 },
74 [3] = {
75 .hwport = 3,
76 .flags = 0,
77 .ucon = UCON,
78 .ulcon = ULCON,
79 .ufcon = UFCON,
80 },
81 };
82
83 /* DM9000AEP 10/100 ethernet controller */
84
85 static struct resource mini6410_dm9k_resource[] = {
86 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
87 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
88 [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
89 | IORESOURCE_IRQ_HIGHLEVEL),
90 };
91
92 static struct dm9000_plat_data mini6410_dm9k_pdata = {
93 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
94 };
95
96 static struct platform_device mini6410_device_eth = {
97 .name = "dm9000",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
100 .resource = mini6410_dm9k_resource,
101 .dev = {
102 .platform_data = &mini6410_dm9k_pdata,
103 },
104 };
105
106 static struct mtd_partition mini6410_nand_part[] = {
107 [0] = {
108 .name = "uboot",
109 .size = SZ_1M,
110 .offset = 0,
111 },
112 [1] = {
113 .name = "kernel",
114 .size = SZ_2M,
115 .offset = SZ_1M,
116 },
117 [2] = {
118 .name = "rootfs",
119 .size = MTDPART_SIZ_FULL,
120 .offset = SZ_1M + SZ_2M,
121 },
122 };
123
124 static struct s3c2410_nand_set mini6410_nand_sets[] = {
125 [0] = {
126 .name = "nand",
127 .nr_chips = 1,
128 .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
129 .partitions = mini6410_nand_part,
130 },
131 };
132
133 static struct s3c2410_platform_nand mini6410_nand_info = {
134 .tacls = 25,
135 .twrph0 = 55,
136 .twrph1 = 40,
137 .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
138 .sets = mini6410_nand_sets,
139 .ecc_mode = NAND_ECC_SOFT,
140 };
141
142 static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
143 .max_bpp = 32,
144 .default_bpp = 16,
145 .xres = 480,
146 .yres = 272,
147 };
148
149 static struct fb_videomode mini6410_lcd_type0_timing = {
150 /* 4.3" 480x272 */
151 .left_margin = 3,
152 .right_margin = 2,
153 .upper_margin = 1,
154 .lower_margin = 1,
155 .hsync_len = 40,
156 .vsync_len = 1,
157 .xres = 480,
158 .yres = 272,
159 };
160
161 static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
162 .max_bpp = 32,
163 .default_bpp = 16,
164 .xres = 800,
165 .yres = 480,
166 };
167
168 static struct fb_videomode mini6410_lcd_type1_timing = {
169 /* 7.0" 800x480 */
170 .left_margin = 8,
171 .right_margin = 13,
172 .upper_margin = 7,
173 .lower_margin = 5,
174 .hsync_len = 3,
175 .vsync_len = 1,
176 .xres = 800,
177 .yres = 480,
178 };
179
180 static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
181 {
182 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
183 .vtiming = &mini6410_lcd_type0_timing,
184 .win[0] = &mini6410_lcd_type0_fb_win,
185 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
186 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
187 }, {
188 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
189 .vtiming = &mini6410_lcd_type1_timing,
190 .win[0] = &mini6410_lcd_type1_fb_win,
191 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
192 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
193 },
194 { },
195 };
196
mini6410_lcd_power_set(struct plat_lcd_data * pd,unsigned int power)197 static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
198 unsigned int power)
199 {
200 if (power)
201 gpio_direction_output(S3C64XX_GPE(0), 1);
202 else
203 gpio_direction_output(S3C64XX_GPE(0), 0);
204 }
205
206 static struct plat_lcd_data mini6410_lcd_power_data = {
207 .set_power = mini6410_lcd_power_set,
208 };
209
210 static struct platform_device mini6410_lcd_powerdev = {
211 .name = "platform-lcd",
212 .dev.parent = &s3c_device_fb.dev,
213 .dev.platform_data = &mini6410_lcd_power_data,
214 };
215
216 static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
217 .max_width = 4,
218 .cd_type = S3C_SDHCI_CD_GPIO,
219 .ext_cd_gpio = S3C64XX_GPN(10),
220 .ext_cd_gpio_invert = true,
221 };
222
223 static struct platform_device *mini6410_devices[] __initdata = {
224 &mini6410_device_eth,
225 &s3c_device_hsmmc0,
226 &s3c_device_hsmmc1,
227 &s3c_device_ohci,
228 &s3c_device_nand,
229 &s3c_device_fb,
230 &mini6410_lcd_powerdev,
231 &s3c_device_adc,
232 };
233
mini6410_map_io(void)234 static void __init mini6410_map_io(void)
235 {
236 u32 tmp;
237
238 s3c64xx_init_io(NULL, 0);
239 s3c64xx_set_xtal_freq(12000000);
240 s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
241 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
242
243 /* set the LCD type */
244 tmp = __raw_readl(S3C64XX_SPCON);
245 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
246 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
247 __raw_writel(tmp, S3C64XX_SPCON);
248
249 /* remove the LCD bypass */
250 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
251 tmp &= ~MIFPCON_LCD_BYPASS;
252 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
253 }
254
255 /*
256 * mini6410_features string
257 *
258 * 0-9 LCD configuration
259 *
260 */
261 static char mini6410_features_str[12] __initdata = "0";
262
mini6410_features_setup(char * str)263 static int __init mini6410_features_setup(char *str)
264 {
265 if (str)
266 strlcpy(mini6410_features_str, str,
267 sizeof(mini6410_features_str));
268 return 1;
269 }
270
271 __setup("mini6410=", mini6410_features_setup);
272
273 #define FEATURE_SCREEN (1 << 0)
274
275 struct mini6410_features_t {
276 int done;
277 int lcd_index;
278 };
279
mini6410_parse_features(struct mini6410_features_t * features,const char * features_str)280 static void mini6410_parse_features(
281 struct mini6410_features_t *features,
282 const char *features_str)
283 {
284 const char *fp = features_str;
285
286 features->done = 0;
287 features->lcd_index = 0;
288
289 while (*fp) {
290 char f = *fp++;
291
292 switch (f) {
293 case '0'...'9': /* tft screen */
294 if (features->done & FEATURE_SCREEN) {
295 printk(KERN_INFO "MINI6410: '%c' ignored, "
296 "screen type already set\n", f);
297 } else {
298 int li = f - '0';
299 if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
300 printk(KERN_INFO "MINI6410: '%c' out "
301 "of range LCD mode\n", f);
302 else {
303 features->lcd_index = li;
304 }
305 }
306 features->done |= FEATURE_SCREEN;
307 break;
308 }
309 }
310 }
311
mini6410_machine_init(void)312 static void __init mini6410_machine_init(void)
313 {
314 u32 cs1;
315 struct mini6410_features_t features = { 0 };
316
317 printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
318 mini6410_features_str);
319
320 /* Parse the feature string */
321 mini6410_parse_features(&features, mini6410_features_str);
322
323 printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
324 mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
325 mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
326
327 s3c_nand_set_platdata(&mini6410_nand_info);
328 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
329 s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
330 s3c64xx_ts_set_platdata(NULL);
331
332 /* configure nCS1 width to 16 bits */
333
334 cs1 = __raw_readl(S3C64XX_SROM_BW) &
335 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
336 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
337 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
338 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
339 S3C64XX_SROM_BW__NCS1__SHIFT;
340 __raw_writel(cs1, S3C64XX_SROM_BW);
341
342 /* set timing for nCS1 suitable for ethernet chip */
343
344 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
345 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
346 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
347 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
348 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
349 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
350 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
351
352 gpio_request(S3C64XX_GPF(15), "LCD power");
353 gpio_request(S3C64XX_GPE(0), "LCD power");
354
355 platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
356 }
357
358 MACHINE_START(MINI6410, "MINI6410")
359 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
360 .atag_offset = 0x100,
361 .nr_irqs = S3C64XX_NR_IRQS,
362 .init_irq = s3c6410_init_irq,
363 .map_io = mini6410_map_io,
364 .init_machine = mini6410_machine_init,
365 .init_time = samsung_timer_init,
366 .restart = s3c64xx_restart,
367 MACHINE_END
368
