1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
7 */
8
9 #include <linux/types.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/memory.h>
13 #include <linux/platform_device.h>
14 #include <linux/gpio.h>
15 #include <linux/moduleparam.h>
16 #include <linux/smsc911x.h>
17 #include <linux/mfd/mc13783.h>
18 #include <linux/spi/spi.h>
19 #include <linux/usb/otg.h>
20 #include <linux/usb/ulpi.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/delay.h>
23 #include <linux/regulator/machine.h>
24 #include <linux/regulator/fixed.h>
25
26 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/time.h>
29 #include <asm/mach/map.h>
30 #include <asm/page.h>
31 #include <asm/setup.h>
32
33 #include "board-mx31lite.h"
34 #include "common.h"
35 #include "devices-imx31.h"
36 #include "ehci.h"
37 #include "hardware.h"
38 #include "iomux-mx3.h"
39 #include "ulpi.h"
40
41 /*
42 * This file contains the module-specific initialization routines.
43 */
44
45 static unsigned int mx31lite_pins[] = {
46 /* UART1 */
47 MX31_PIN_CTS1__CTS1,
48 MX31_PIN_RTS1__RTS1,
49 MX31_PIN_TXD1__TXD1,
50 MX31_PIN_RXD1__RXD1,
51 /* SPI 0 */
52 MX31_PIN_CSPI1_SCLK__SCLK,
53 MX31_PIN_CSPI1_MOSI__MOSI,
54 MX31_PIN_CSPI1_MISO__MISO,
55 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
56 MX31_PIN_CSPI1_SS0__SS0,
57 MX31_PIN_CSPI1_SS1__SS1,
58 MX31_PIN_CSPI1_SS2__SS2,
59 /* LAN9117 IRQ pin */
60 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
61 /* SPI 1 */
62 MX31_PIN_CSPI2_SCLK__SCLK,
63 MX31_PIN_CSPI2_MOSI__MOSI,
64 MX31_PIN_CSPI2_MISO__MISO,
65 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
66 MX31_PIN_CSPI2_SS0__SS0,
67 MX31_PIN_CSPI2_SS1__SS1,
68 MX31_PIN_CSPI2_SS2__SS2,
69 };
70
71 /* UART */
72 static const struct imxuart_platform_data uart_pdata __initconst = {
73 .flags = IMXUART_HAVE_RTSCTS,
74 };
75
76 /* SPI */
77 static const struct spi_imx_master spi0_pdata __initconst = {
78 .num_chipselect = 3,
79 };
80
81 static const struct mxc_nand_platform_data
82 mx31lite_nand_board_info __initconst = {
83 .width = 1,
84 .hw_ecc = 1,
85 };
86
87 static struct smsc911x_platform_config smsc911x_config = {
88 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
89 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
90 .flags = SMSC911X_USE_16BIT,
91 };
92
93 static struct resource smsc911x_resources[] = {
94 {
95 .start = MX31_CS4_BASE_ADDR,
96 .end = MX31_CS4_BASE_ADDR + 0x100,
97 .flags = IORESOURCE_MEM,
98 }, {
99 /* irq number is run-time assigned */
100 .flags = IORESOURCE_IRQ,
101 },
102 };
103
104 static struct platform_device smsc911x_device = {
105 .name = "smsc911x",
106 .id = -1,
107 .num_resources = ARRAY_SIZE(smsc911x_resources),
108 .resource = smsc911x_resources,
109 .dev = {
110 .platform_data = &smsc911x_config,
111 },
112 };
113
114 /*
115 * SPI
116 *
117 * The MC13783 is the only hard-wired SPI device on the module.
118 */
119
120 static const struct spi_imx_master spi1_pdata __initconst = {
121 .num_chipselect = 1,
122 };
123
124 static struct mc13xxx_platform_data mc13783_pdata __initdata = {
125 .flags = MC13XXX_USE_RTC,
126 };
127
128 static struct spi_board_info mc13783_spi_dev __initdata = {
129 .modalias = "mc13783",
130 .max_speed_hz = 1000000,
131 .bus_num = 1,
132 .chip_select = 0,
133 .platform_data = &mc13783_pdata,
134 /* irq number is run-time assigned */
135 };
136
137 /*
138 * USB
139 */
140
141 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
142 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
143
usbh2_init(struct platform_device * pdev)144 static int usbh2_init(struct platform_device *pdev)
145 {
146 int pins[] = {
147 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
148 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
149 MX31_PIN_USBH2_CLK__USBH2_CLK,
150 MX31_PIN_USBH2_DIR__USBH2_DIR,
151 MX31_PIN_USBH2_NXT__USBH2_NXT,
152 MX31_PIN_USBH2_STP__USBH2_STP,
153 };
154
155 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
156
157 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
161 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
162 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
163 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
164 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
165 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
166 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
167 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
168 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
169
170 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
171
172 /* chip select */
173 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
174 "USBH2_CS");
175 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
176 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
177
178 mdelay(10);
179
180 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
181 }
182
183 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
184 .init = usbh2_init,
185 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
186 };
187
188 /*
189 * NOR flash
190 */
191
192 static struct physmap_flash_data nor_flash_data = {
193 .width = 2,
194 };
195
196 static struct resource nor_flash_resource = {
197 .start = 0xa0000000,
198 .end = 0xa1ffffff,
199 .flags = IORESOURCE_MEM,
200 };
201
202 static struct platform_device physmap_flash_device = {
203 .name = "physmap-flash",
204 .id = 0,
205 .dev = {
206 .platform_data = &nor_flash_data,
207 },
208 .resource = &nor_flash_resource,
209 .num_resources = 1,
210 };
211
212 /*
213 * This structure defines the MX31 memory map.
214 */
215 static struct map_desc mx31lite_io_desc[] __initdata = {
216 {
217 .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
218 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
219 .length = MX31_CS4_SIZE,
220 .type = MT_DEVICE
221 }
222 };
223
224 /*
225 * Set up static virtual mappings.
226 */
mx31lite_map_io(void)227 static void __init mx31lite_map_io(void)
228 {
229 mx31_map_io();
230 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
231 }
232
233 static int mx31lite_baseboard;
234 core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
235
236 static struct regulator_consumer_supply dummy_supplies[] = {
237 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
238 REGULATOR_SUPPLY("vddvario", "smsc911x"),
239 };
240
mx31lite_init(void)241 static void __init mx31lite_init(void)
242 {
243 imx31_soc_init();
244
245 mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
246 "mx31lite");
247
248 imx31_add_imx_uart0(&uart_pdata);
249 imx31_add_spi_imx0(&spi0_pdata);
250
251 /* NOR and NAND flash */
252 platform_device_register(&physmap_flash_device);
253 imx31_add_mxc_nand(&mx31lite_nand_board_info);
254
255 imx31_add_spi_imx1(&spi1_pdata);
256
257 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
258 }
259
mx31lite_late(void)260 static void __init mx31lite_late(void)
261 {
262 int ret;
263
264 if (mx31lite_baseboard == MX31LITE_DB)
265 mx31lite_db_init();
266
267 mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
268 spi_register_board_info(&mc13783_spi_dev, 1);
269
270 /* USB */
271 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
272 ULPI_OTG_DRVVBUS_EXT);
273 if (usbh2_pdata.otg)
274 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
275
276 /* SMSC9117 IRQ pin */
277 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
278 if (ret)
279 pr_warn("could not get LAN irq gpio\n");
280 else {
281 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
282 smsc911x_resources[1].start =
283 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
284 smsc911x_resources[1].end =
285 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
286 platform_device_register(&smsc911x_device);
287 }
288 }
289
mx31lite_timer_init(void)290 static void __init mx31lite_timer_init(void)
291 {
292 mx31_clocks_init(26000000);
293 }
294
295 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
296 /* Maintainer: Freescale Semiconductor, Inc. */
297 .atag_offset = 0x100,
298 .map_io = mx31lite_map_io,
299 .init_early = imx31_init_early,
300 .init_irq = mx31_init_irq,
301 .init_time = mx31lite_timer_init,
302 .init_machine = mx31lite_init,
303 .init_late = mx31lite_late,
304 .restart = mxc_restart,
305 MACHINE_END
306
