1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 */
7
8 #include <linux/types.h>
9 #include <linux/init.h>
10 #include <linux/clk.h>
11 #include <linux/serial_8250.h>
12 #include <linux/gpio.h>
13 #include <linux/i2c.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16
17 #include <asm/mach-types.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/time.h>
20 #include <asm/memory.h>
21 #include <asm/mach/map.h>
22
23 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
24 #include <linux/mfd/wm8350/audio.h>
25 #include <linux/mfd/wm8350/core.h>
26 #include <linux/mfd/wm8350/pmic.h>
27 #endif
28
29 #include "common.h"
30 #include "devices-imx31.h"
31 #include "hardware.h"
32 #include "iomux-mx3.h"
33
34 /* Base address of PBC controller */
35 #define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
36
37 /* PBC Board interrupt status register */
38 #define PBC_INTSTATUS 0x000016
39
40 /* PBC Board interrupt current status register */
41 #define PBC_INTCURR_STATUS 0x000018
42
43 /* PBC Interrupt mask register set address */
44 #define PBC_INTMASK_SET 0x00001A
45
46 /* PBC Interrupt mask register clear address */
47 #define PBC_INTMASK_CLEAR 0x00001C
48
49 /* External UART A */
50 #define PBC_SC16C652_UARTA 0x010000
51
52 /* External UART B */
53 #define PBC_SC16C652_UARTB 0x010010
54
55 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
56 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
57 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
58
59 #define EXPIO_INT_XUART_INTA 10
60 #define EXPIO_INT_XUART_INTB 11
61
62 #define MXC_MAX_EXP_IO_LINES 16
63
64 /* CS8900 */
65 #define EXPIO_INT_ENET_INT 8
66 #define CS4_CS8900_MMIO_START 0x20000
67
68 static struct irq_domain *domain;
69
70 /*
71 * The serial port definition structure.
72 */
73 static struct plat_serial8250_port serial_platform_data[] = {
74 {
75 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
76 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
77 .uartclk = 14745600,
78 .regshift = 0,
79 .iotype = UPIO_MEM,
80 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
81 }, {
82 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
83 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
84 .uartclk = 14745600,
85 .regshift = 0,
86 .iotype = UPIO_MEM,
87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
88 },
89 {},
90 };
91
92 static struct platform_device serial_device = {
93 .name = "serial8250",
94 .id = 0,
95 .dev = {
96 .platform_data = serial_platform_data,
97 },
98 };
99
100 static struct resource mx31ads_cs8900_resources[] __initdata = {
101 DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
102 DEFINE_RES_IRQ(-1),
103 };
104
105 static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
106 .name = "cs89x0",
107 .id = 0,
108 .res = mx31ads_cs8900_resources,
109 .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
110 };
111
mxc_init_extuart(void)112 static int __init mxc_init_extuart(void)
113 {
114 serial_platform_data[0].irq = irq_find_mapping(domain,
115 EXPIO_INT_XUART_INTA);
116 serial_platform_data[1].irq = irq_find_mapping(domain,
117 EXPIO_INT_XUART_INTB);
118 return platform_device_register(&serial_device);
119 }
120
mxc_init_ext_ethernet(void)121 static void __init mxc_init_ext_ethernet(void)
122 {
123 mx31ads_cs8900_resources[1].start =
124 irq_find_mapping(domain, EXPIO_INT_ENET_INT);
125 mx31ads_cs8900_resources[1].end =
126 irq_find_mapping(domain, EXPIO_INT_ENET_INT);
127 platform_device_register_full(
128 (struct platform_device_info *)&mx31ads_cs8900_devinfo);
129 }
130
131 static const struct imxuart_platform_data uart_pdata __initconst = {
132 .flags = IMXUART_HAVE_RTSCTS,
133 };
134
135 static unsigned int uart_pins[] = {
136 MX31_PIN_CTS1__CTS1,
137 MX31_PIN_RTS1__RTS1,
138 MX31_PIN_TXD1__TXD1,
139 MX31_PIN_RXD1__RXD1
140 };
141
mxc_init_imx_uart(void)142 static inline void mxc_init_imx_uart(void)
143 {
144 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
145 imx31_add_imx_uart0(&uart_pdata);
146 }
147
mx31ads_expio_irq_handler(struct irq_desc * desc)148 static void mx31ads_expio_irq_handler(struct irq_desc *desc)
149 {
150 u32 imr_val;
151 u32 int_valid;
152 u32 expio_irq;
153
154 imr_val = imx_readw(PBC_INTMASK_SET_REG);
155 int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val;
156
157 expio_irq = 0;
158 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
159 if ((int_valid & 1) == 0)
160 continue;
161
162 generic_handle_irq(irq_find_mapping(domain, expio_irq));
163 }
164 }
165
166 /*
167 * Disable an expio pin's interrupt by setting the bit in the imr.
168 * @param d an expio virtual irq description
169 */
expio_mask_irq(struct irq_data * d)170 static void expio_mask_irq(struct irq_data *d)
171 {
172 u32 expio = d->hwirq;
173 /* mask the interrupt */
174 imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
175 imx_readw(PBC_INTMASK_CLEAR_REG);
176 }
177
178 /*
179 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
180 * @param d an expio virtual irq description
181 */
expio_ack_irq(struct irq_data * d)182 static void expio_ack_irq(struct irq_data *d)
183 {
184 u32 expio = d->hwirq;
185 /* clear the interrupt status */
186 imx_writew(1 << expio, PBC_INTSTATUS_REG);
187 }
188
189 /*
190 * Enable a expio pin's interrupt by clearing the bit in the imr.
191 * @param d an expio virtual irq description
192 */
expio_unmask_irq(struct irq_data * d)193 static void expio_unmask_irq(struct irq_data *d)
194 {
195 u32 expio = d->hwirq;
196 /* unmask the interrupt */
197 imx_writew(1 << expio, PBC_INTMASK_SET_REG);
198 }
199
200 static struct irq_chip expio_irq_chip = {
201 .name = "EXPIO(CPLD)",
202 .irq_ack = expio_ack_irq,
203 .irq_mask = expio_mask_irq,
204 .irq_unmask = expio_unmask_irq,
205 };
206
mx31ads_init_expio(void)207 static void __init mx31ads_init_expio(void)
208 {
209 int irq_base;
210 int i, irq;
211
212 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
213
214 /*
215 * Configure INT line as GPIO input
216 */
217 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
218
219 /* disable the interrupt and clear the status */
220 imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
221 imx_writew(0xFFFF, PBC_INTSTATUS_REG);
222
223 irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
224 WARN_ON(irq_base < 0);
225
226 domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
227 &irq_domain_simple_ops, NULL);
228 WARN_ON(!domain);
229
230 for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
231 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
232 irq_clear_status_flags(i, IRQ_NOREQUEST);
233 }
234 irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
235 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
236 irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
237 }
238
239 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
240 /* This section defines setup for the Wolfson Microelectronics
241 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
242 * regulator definitions may be shared with them, but for now they can
243 * only be used with this board so would generate warnings about
244 * unused statics and some of the configuration is specific to this
245 * module.
246 */
247
248 /* CPU */
249 static struct regulator_consumer_supply sw1a_consumers[] = {
250 {
251 .supply = "cpu_vcc",
252 }
253 };
254
255 static struct regulator_init_data sw1a_data = {
256 .constraints = {
257 .name = "SW1A",
258 .min_uV = 1275000,
259 .max_uV = 1600000,
260 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
261 REGULATOR_CHANGE_MODE,
262 .valid_modes_mask = REGULATOR_MODE_NORMAL |
263 REGULATOR_MODE_FAST,
264 .state_mem = {
265 .uV = 1400000,
266 .mode = REGULATOR_MODE_NORMAL,
267 .enabled = 1,
268 },
269 .initial_state = PM_SUSPEND_MEM,
270 .always_on = 1,
271 .boot_on = 1,
272 },
273 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
274 .consumer_supplies = sw1a_consumers,
275 };
276
277 /* System IO - High */
278 static struct regulator_init_data viohi_data = {
279 .constraints = {
280 .name = "VIOHO",
281 .min_uV = 2800000,
282 .max_uV = 2800000,
283 .state_mem = {
284 .uV = 2800000,
285 .mode = REGULATOR_MODE_NORMAL,
286 .enabled = 1,
287 },
288 .initial_state = PM_SUSPEND_MEM,
289 .always_on = 1,
290 .boot_on = 1,
291 },
292 };
293
294 /* System IO - Low */
295 static struct regulator_init_data violo_data = {
296 .constraints = {
297 .name = "VIOLO",
298 .min_uV = 1800000,
299 .max_uV = 1800000,
300 .state_mem = {
301 .uV = 1800000,
302 .mode = REGULATOR_MODE_NORMAL,
303 .enabled = 1,
304 },
305 .initial_state = PM_SUSPEND_MEM,
306 .always_on = 1,
307 .boot_on = 1,
308 },
309 };
310
311 /* DDR RAM */
312 static struct regulator_init_data sw2a_data = {
313 .constraints = {
314 .name = "SW2A",
315 .min_uV = 1800000,
316 .max_uV = 1800000,
317 .valid_modes_mask = REGULATOR_MODE_NORMAL,
318 .state_mem = {
319 .uV = 1800000,
320 .mode = REGULATOR_MODE_NORMAL,
321 .enabled = 1,
322 },
323 .state_disk = {
324 .mode = REGULATOR_MODE_NORMAL,
325 .enabled = 0,
326 },
327 .always_on = 1,
328 .boot_on = 1,
329 .initial_state = PM_SUSPEND_MEM,
330 },
331 };
332
333 static struct regulator_init_data ldo1_data = {
334 .constraints = {
335 .name = "VCAM/VMMC1/VMMC2",
336 .min_uV = 2800000,
337 .max_uV = 2800000,
338 .valid_modes_mask = REGULATOR_MODE_NORMAL,
339 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
340 .apply_uV = 1,
341 },
342 };
343
344 static struct regulator_consumer_supply ldo2_consumers[] = {
345 { .supply = "AVDD", .dev_name = "1-001a" },
346 { .supply = "HPVDD", .dev_name = "1-001a" },
347 };
348
349 /* CODEC and SIM */
350 static struct regulator_init_data ldo2_data = {
351 .constraints = {
352 .name = "VESIM/VSIM/AVDD",
353 .min_uV = 3300000,
354 .max_uV = 3300000,
355 .valid_modes_mask = REGULATOR_MODE_NORMAL,
356 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
357 .apply_uV = 1,
358 },
359 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
360 .consumer_supplies = ldo2_consumers,
361 };
362
363 /* General */
364 static struct regulator_init_data vdig_data = {
365 .constraints = {
366 .name = "VDIG",
367 .min_uV = 1500000,
368 .max_uV = 1500000,
369 .valid_modes_mask = REGULATOR_MODE_NORMAL,
370 .apply_uV = 1,
371 .always_on = 1,
372 .boot_on = 1,
373 },
374 };
375
376 /* Tranceivers */
377 static struct regulator_init_data ldo4_data = {
378 .constraints = {
379 .name = "VRF1/CVDD_2.775",
380 .min_uV = 2500000,
381 .max_uV = 2500000,
382 .valid_modes_mask = REGULATOR_MODE_NORMAL,
383 .apply_uV = 1,
384 .always_on = 1,
385 .boot_on = 1,
386 },
387 };
388
389 static struct wm8350_led_platform_data wm8350_led_data = {
390 .name = "wm8350:white",
391 .default_trigger = "heartbeat",
392 .max_uA = 27899,
393 };
394
395 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
396 .vmid_discharge_msecs = 1000,
397 .drain_msecs = 30,
398 .cap_discharge_msecs = 700,
399 .vmid_charge_msecs = 700,
400 .vmid_s_curve = WM8350_S_CURVE_SLOW,
401 .dis_out4 = WM8350_DISCHARGE_SLOW,
402 .dis_out3 = WM8350_DISCHARGE_SLOW,
403 .dis_out2 = WM8350_DISCHARGE_SLOW,
404 .dis_out1 = WM8350_DISCHARGE_SLOW,
405 .vroi_out4 = WM8350_TIE_OFF_500R,
406 .vroi_out3 = WM8350_TIE_OFF_500R,
407 .vroi_out2 = WM8350_TIE_OFF_500R,
408 .vroi_out1 = WM8350_TIE_OFF_500R,
409 .vroi_enable = 0,
410 .codec_current_on = WM8350_CODEC_ISEL_1_0,
411 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
412 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
413 };
414
mx31_wm8350_init(struct wm8350 * wm8350)415 static int mx31_wm8350_init(struct wm8350 *wm8350)
416 {
417 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
418 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
419 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
420 WM8350_GPIO_DEBOUNCE_ON);
421
422 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
423 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
424 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
425 WM8350_GPIO_DEBOUNCE_ON);
426
427 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
428 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
429 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
430 WM8350_GPIO_DEBOUNCE_OFF);
431
432 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
433 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
434 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
435 WM8350_GPIO_DEBOUNCE_OFF);
436
437 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
438 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
439 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
440 WM8350_GPIO_DEBOUNCE_OFF);
441
442 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
443 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
444 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
445 WM8350_GPIO_DEBOUNCE_OFF);
446
447 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
448 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
449 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
450 WM8350_GPIO_DEBOUNCE_OFF);
451
452 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
453 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
454 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
455 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
456 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
457 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
458 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
459 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
460
461 /* LEDs */
462 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
463 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
464 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
465 WM8350_ISINK_FLASH_DISABLE,
466 WM8350_ISINK_FLASH_TRIG_BIT,
467 WM8350_ISINK_FLASH_DUR_32MS,
468 WM8350_ISINK_FLASH_ON_INSTANT,
469 WM8350_ISINK_FLASH_OFF_INSTANT,
470 WM8350_ISINK_FLASH_MODE_EN);
471 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
472 WM8350_ISINK_MODE_BOOST,
473 WM8350_ISINK_ILIM_NORMAL,
474 WM8350_DC5_RMP_20V,
475 WM8350_DC5_FBSRC_ISINKA);
476 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
477 &wm8350_led_data);
478
479 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
480
481 regulator_has_full_constraints();
482
483 return 0;
484 }
485
486 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
487 .init = mx31_wm8350_init,
488 };
489 #endif
490
491 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
492 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
493 {
494 I2C_BOARD_INFO("wm8350", 0x1a),
495 .platform_data = &mx31_wm8350_pdata,
496 /* irq number is run-time assigned */
497 },
498 #endif
499 };
500
mxc_init_i2c(void)501 static void __init mxc_init_i2c(void)
502 {
503 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
504 mx31ads_i2c1_devices[0].irq =
505 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
506 #endif
507 i2c_register_board_info(1, mx31ads_i2c1_devices,
508 ARRAY_SIZE(mx31ads_i2c1_devices));
509
510 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
511 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
512
513 imx31_add_imx_i2c1(NULL);
514 }
515
516 static unsigned int ssi_pins[] = {
517 MX31_PIN_SFS5__SFS5,
518 MX31_PIN_SCK5__SCK5,
519 MX31_PIN_SRXD5__SRXD5,
520 MX31_PIN_STXD5__STXD5,
521 };
522
mxc_init_audio(void)523 static void __init mxc_init_audio(void)
524 {
525 imx31_add_imx_ssi(0, NULL);
526 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
527 }
528
529 /*
530 * Static mappings, starting from the CS4 start address up to the start address
531 * of the CS8900.
532 */
533 static struct map_desc mx31ads_io_desc[] __initdata = {
534 {
535 .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
536 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
537 .length = CS4_CS8900_MMIO_START,
538 .type = MT_DEVICE
539 },
540 };
541
mx31ads_map_io(void)542 static void __init mx31ads_map_io(void)
543 {
544 mx31_map_io();
545 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
546 }
547
mx31ads_init(void)548 static void __init mx31ads_init(void)
549 {
550 imx31_soc_init();
551
552 mxc_init_imx_uart();
553 mxc_init_audio();
554 }
555
mx31ads_late(void)556 static void __init mx31ads_late(void)
557 {
558 mx31ads_init_expio();
559 mxc_init_extuart();
560 mxc_init_i2c();
561 mxc_init_ext_ethernet();
562 }
563
mx31ads_timer_init(void)564 static void __init mx31ads_timer_init(void)
565 {
566 mx31_clocks_init(26000000);
567 }
568
569 MACHINE_START(MX31ADS, "Freescale MX31ADS")
570 /* Maintainer: Freescale Semiconductor, Inc. */
571 .atag_offset = 0x100,
572 .map_io = mx31ads_map_io,
573 .init_early = imx31_init_early,
574 .init_irq = mx31_init_irq,
575 .init_time = mx31ads_timer_init,
576 .init_machine = mx31ads_init,
577 .init_late = mx31ads_late,
578 .restart = mxc_restart,
579 MACHINE_END
580
