1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
4 *
5 * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
6 */
7
8#include "omap36xx.dtsi"
9
10/ {
11	cpus {
12		cpu@0 {
13			cpu0-supply = <&vcc>;
14			operating-points = <
15				/* kHz    uV */
16				300000  1012500
17				600000  1200000
18				800000  1325000
19				1000000	1375000
20			>;
21		};
22	};
23
24	memory@80000000 {
25		device_type = "memory";
26		reg = <0x80000000 0x40000000>; /* 1 GB */
27	};
28
29	vemmc: fixedregulator0 {
30		compatible = "regulator-fixed";
31		regulator-name = "VEMMC";
32		regulator-min-microvolt = <2900000>;
33		regulator-max-microvolt = <2900000>;
34		gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */
35		startup-delay-us = <150>;
36		enable-active-high;
37	};
38
39	vwlan_fixed: fixedregulator2 {
40		compatible = "regulator-fixed";
41		regulator-name = "VWLAN";
42		gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */
43		enable-active-high;
44	};
45
46	leds {
47		compatible = "gpio-leds";
48
49		heartbeat {
50			label = "debug::sleep";
51			gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;  /* gpio92 */
52			linux,default-trigger = "default-on";
53			pinctrl-names = "default";
54			pinctrl-0 = <&debug_leds>;
55		};
56	};
57
58	/* controlled (enabled/disabled) directly by wl1271 */
59	vctcxo: vctcxo {
60		compatible = "fixed-clock";
61		#clock-cells = <0>;
62		clock-frequency = <38400000>;
63	};
64};
65
66&omap3_pmx_core {
67	accelerator_pins: pinmux_accelerator_pins {
68		pinctrl-single,pins = <
69			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4)	/* mcspi2_somi.gpio_180 -> LIS302 INT1 */
70			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4)	/* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
71		>;
72	};
73
74	debug_leds: pinmux_debug_led_pins {
75		pinctrl-single,pins = <
76			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4)       /* dss_data22.gpio_92 */
77		>;
78	};
79
80	mmc2_pins: pinmux_mmc2_pins {
81		pinctrl-single,pins = <
82			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
83			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
84			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
85			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
86			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
87			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
88		>;
89	};
90
91	wlan_pins: pinmux_wlan_pins {
92		pinctrl-single,pins = <
93			OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */
94			OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */
95		>;
96	};
97
98	ssi_pins: pinmux_ssi_pins {
99		pinctrl-single,pins = <
100			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1)            /* ssi1_dat_tx */
101			OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1)            /* ssi1_flag_tx */
102			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1)      /* ssi1_rdy_tx */
103			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4)	/* ssi1_wake_tx (cawake) */
104			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1)             /* ssi1_dat_rx */
105			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1)             /* ssi1_flag_rx */
106			OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1)            /* ssi1_rdy_rx */
107			OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1)            /* ssi1_wake */
108		>;
109	};
110
111	ssi_pins_idle: pinmux_ssi_pins_idle {
112		pinctrl-single,pins = <
113			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7)            /* ssi1_dat_tx */
114			OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7)            /* ssi1_flag_tx */
115			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7)    /* ssi1_rdy_tx */
116			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4)	/* ssi1_wake_tx (cawake) */
117			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7)             /* ssi1_dat_rx */
118			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7)             /* ssi1_flag_rx */
119			OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4)            /* ssi1_rdy_rx */
120			OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7)            /* ssi1_wake */
121		>;
122	};
123
124	modem_pins1: pinmux_modem_core1_pins {
125		pinctrl-single,pins = <
126			OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4)	/* gpio_34 (ape_rst_rq) */
127			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4)            /* gpio_88 (cmt_rst_rq) */
128			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4)            /* gpio_93 (cmt_apeslpx) */
129		>;
130	};
131
132	uart2_pins: pinmux_uart2_pins {
133		pinctrl-single,pins = <
134			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0)		/* uart2_cts */
135			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)		/* uart2_rts */
136			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)		/* uart2_tx */
137			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)		/* uart2_rx */
138		>;
139	};
140};
141
142&omap3_pmx_core2 {
143	modem_pins2: pinmux_modem_core2_pins {
144		pinctrl-single,pins = <
145			OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)         /* gpio_23 (cmt_en) */
146		>;
147	};
148};
149
150&i2c1 {
151	clock-frequency = <2900000>;
152
153	twl: twl@48 {
154		reg = <0x48>;
155		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
156		interrupt-parent = <&intc>;
157	};
158};
159
160/include/ "twl4030.dtsi"
161
162&twl {
163	compatible = "ti,twl5031";
164
165	twl_power: power {
166		compatible = "ti,twl4030-power";
167		ti,use_poweroff;
168	};
169};
170
171&twl_gpio {
172	ti,pullups	= <0x000001>; /* BIT(0) */
173	ti,pulldowns	= <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
174};
175
176&vdac {
177	regulator-name = "vdac";
178	regulator-min-microvolt = <1800000>;
179	regulator-max-microvolt = <1800000>;
180};
181
182&vpll1 {
183	regulator-name = "vpll1";
184	regulator-min-microvolt = <1800000>;
185	regulator-max-microvolt = <1800000>;
186};
187
188&vpll2 {
189	regulator-name = "vpll2";
190	regulator-min-microvolt = <1800000>;
191	regulator-max-microvolt = <1800000>;
192};
193
194&vaux1 {
195	regulator-name = "vaux1";
196	regulator-min-microvolt = <2800000>;
197	regulator-max-microvolt = <2800000>;
198};
199
200/* CSI-2 receiver */
201&vaux2 {
202	regulator-name = "vaux2";
203	regulator-min-microvolt = <1800000>;
204	regulator-max-microvolt = <1800000>;
205};
206
207/* Cameras */
208&vaux3 {
209	regulator-name = "vaux3";
210	regulator-min-microvolt = <2800000>;
211	regulator-max-microvolt = <2800000>;
212};
213
214&vaux4 {
215	regulator-name = "vaux4";
216	regulator-min-microvolt = <2800000>;
217	regulator-max-microvolt = <2800000>;
218};
219
220&vmmc1 {
221	regulator-name = "vmmc1";
222	regulator-min-microvolt = <1850000>;
223	regulator-max-microvolt = <3150000>;
224};
225
226&vmmc2 {
227	regulator-name = "vmmc2";
228	regulator-min-microvolt = <3000000>;
229	regulator-max-microvolt = <3000000>;
230};
231
232&vintana1 {
233	regulator-name = "vintana1";
234	regulator-min-microvolt = <1500000>;
235	regulator-max-microvolt = <1500000>;
236};
237
238&vintana2 {
239	regulator-name = "vintana2";
240	regulator-min-microvolt = <2750000>;
241	regulator-max-microvolt = <2750000>;
242};
243
244&vintdig {
245	regulator-name = "vintdig";
246	regulator-min-microvolt = <1500000>;
247	regulator-max-microvolt = <1500000>;
248};
249
250&vsim {
251	regulator-name = "vsim";
252	regulator-min-microvolt = <1800000>;
253	regulator-max-microvolt = <1800000>;
254};
255
256&vio {
257	regulator-name = "vio";
258	regulator-min-microvolt = <1800000>;
259	regulator-max-microvolt = <1800000>;
260};
261
262&i2c2 {
263	clock-frequency = <400000>;
264
265	as3645a@30 {
266		#address-cells = <1>;
267		#size-cells = <0>;
268		reg = <0x30>;
269		compatible = "ams,as3645a";
270		as3645a_flash: flash@0 {
271			reg = <0x0>;
272			flash-timeout-us = <150000>;
273			flash-max-microamp = <320000>;
274			led-max-microamp = <60000>;
275			ams,input-max-microamp = <1750000>;
276		};
277		as3645a_indicator: indicator@1 {
278			reg = <0x1>;
279			led-max-microamp = <10000>;
280		};
281	};
282};
283
284&i2c3 {
285	clock-frequency = <400000>;
286
287	lis302: lis302@1d {
288		compatible = "st,lis3lv02d";
289		reg = <0x1d>;
290
291		Vdd-supply = <&vaux1>;
292		Vdd_IO-supply = <&vio>;
293
294		pinctrl-names = "default";
295		pinctrl-0 = <&accelerator_pins>;
296
297                interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */
298
299		/* click flags */
300		st,click-single-x;
301		st,click-single-y;
302		st,click-single-z;
303
304		/* Limits are 0.5g * value */
305		st,click-threshold-x = <8>;
306		st,click-threshold-y = <8>;
307		st,click-threshold-z = <10>;
308
309		/* Click must be longer than time limit */
310		st,click-time-limit = <9>;
311
312		/* Kind of debounce filter */
313		st,click-latency = <50>;
314
315		st,wakeup-x-hi;
316		st,wakeup-y-hi;
317		st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
318
319		st,wakeup2-z-hi;
320		st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */
321
322		st,highpass-cutoff-hz = <2>;
323
324		/* Interrupt line 1 for thresholds */
325		st,irq1-ff-wu-1;
326		st,irq1-ff-wu-2;
327		/* Interrupt line 2 for click detection */
328		st,irq2-click;
329
330		st,wu-duration-1 = <8>;
331		st,wu-duration-2 = <8>;
332	};
333};
334
335&mmc1 {
336	status = "disabled";
337};
338
339&mmc2 {
340	pinctrl-names = "default";
341	pinctrl-0 = <&mmc2_pins>;
342	vmmc-supply = <&vemmc>;
343	bus-width = <4>;
344	ti,non-removable;
345};
346
347&mmc3 {
348	status = "disabled";
349};
350
351&usb_otg_hs {
352	interface-type = <0>;
353	usb-phy = <&usb2_phy>;
354	phys = <&usb2_phy>;
355	phy-names = "usb2-phy";
356	mode = <3>;
357	power = <50>;
358};
359
360&gpmc {
361	ranges = <0 0 0x04000000 0x1000000>;	/* CS0: 16MB for OneNAND */
362
363	onenand@0,0 {
364		#address-cells = <1>;
365		#size-cells = <1>;
366		compatible = "ti,omap2-onenand";
367		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
368
369		/*
370		 * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
371		 * bootloader set values when booted with v4.19 using both N950
372		 * and N9 devices (OneNAND Manufacturer: Samsung):
373		 *
374		 *   gpmc cs0 before gpmc_cs_program_settings:
375		 *   cs0 GPMC_CS_CONFIG1: 0xfd001202
376		 *   cs0 GPMC_CS_CONFIG2: 0x00181800
377		 *   cs0 GPMC_CS_CONFIG3: 0x00030300
378		 *   cs0 GPMC_CS_CONFIG4: 0x18001804
379		 *   cs0 GPMC_CS_CONFIG5: 0x03171d1d
380		 *   cs0 GPMC_CS_CONFIG6: 0x97080000
381		 */
382		gpmc,sync-read;
383		gpmc,sync-write;
384		gpmc,burst-length = <16>;
385		gpmc,burst-read;
386		gpmc,burst-wrap;
387		gpmc,burst-write;
388		gpmc,device-width = <2>;
389		gpmc,mux-add-data = <2>;
390		gpmc,cs-on-ns = <0>;
391		gpmc,cs-rd-off-ns = <122>;
392		gpmc,cs-wr-off-ns = <122>;
393		gpmc,adv-on-ns = <0>;
394		gpmc,adv-rd-off-ns = <15>;
395		gpmc,adv-wr-off-ns = <15>;
396		gpmc,oe-on-ns = <20>;
397		gpmc,oe-off-ns = <122>;
398		gpmc,we-on-ns = <0>;
399		gpmc,we-off-ns = <122>;
400		gpmc,rd-cycle-ns = <148>;
401		gpmc,wr-cycle-ns = <148>;
402		gpmc,access-ns = <117>;
403		gpmc,page-burst-access-ns = <15>;
404		gpmc,bus-turnaround-ns = <0>;
405		gpmc,cycle2cycle-delay-ns = <0>;
406		gpmc,wait-monitoring-ns = <0>;
407		gpmc,clk-activation-ns = <10>;
408		gpmc,wr-data-mux-bus-ns = <40>;
409		gpmc,wr-access-ns = <117>;
410
411		gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */
412
413		/*
414		 * MTD partition table corresponding to Nokia's MeeGo 1.2
415		 * Harmattan release.
416		 */
417		partition@0 {
418			label = "bootloader";
419			reg = <0x00000000 0x00100000>;
420		};
421		partition@1 {
422			label = "config";
423			reg = <0x00100000 0x002c0000>;
424		};
425		partition@2 {
426			label = "kernel";
427			reg = <0x003c0000 0x01000000>;
428		};
429		partition@3 {
430			label = "log";
431			reg = <0x013c0000 0x00200000>;
432		};
433		partition@4 {
434			label = "var";
435			reg = <0x015c0000 0x1ca40000>;
436		};
437		partition@5 {
438			label = "moslo";
439			reg = <0x1e000000 0x02000000>;
440		};
441		partition@6 {
442			label = "omap2-onenand";
443			reg = <0x00000000 0x20000000>;
444		};
445	};
446};
447
448&ssi_port1 {
449	pinctrl-names = "default", "idle";
450	pinctrl-0 = <&ssi_pins>;
451	pinctrl-1 = <&ssi_pins_idle>;
452
453	ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
454
455	modem: hsi-client {
456		pinctrl-names = "default";
457		pinctrl-0 = <&modem_pins1 &modem_pins2>;
458
459		hsi-channel-ids = <0>, <1>, <2>, <3>;
460		hsi-channel-names = "mcsaab-control",
461				    "speech-control",
462				    "speech-data",
463				    "mcsaab-data";
464		hsi-speed-kbps = <96000>;
465		hsi-mode = "frame";
466		hsi-flow = "synchronized";
467		hsi-arb-mode = "round-robin";
468
469		interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */
470
471		gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */
472			<&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */
473			<&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */
474		gpio-names = "cmt_apeslpx",
475			     "cmt_rst_rq",
476			     "cmt_en";
477	};
478};
479
480&ssi_port2 {
481	status = "disabled";
482};
483
484&uart2 {
485	pinctrl-names = "default";
486	pinctrl-0 = <&uart2_pins>;
487
488	bluetooth {
489		compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth";
490
491		reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */
492		host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
493		bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
494
495		clocks = <&vctcxo>;
496		clock-names = "sysclk";
497	};
498};
499