1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
4 */
5
6#include "meson8.dtsi"
7
8/ {
9	model = "Amlogic Meson8m2 SoC";
10	compatible = "amlogic,meson8m2";
11}; /* end of / */
12
13&clkc {
14	compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
15};
16
17&dmcbus {
18	/* the offset of the canvas registers has changed compared to Meson8 */
19	/delete-node/ video-lut@20;
20
21	canvas: video-lut@48 {
22		compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
23		reg = <0x48 0x14>;
24	};
25};
26
27&ethmac {
28	compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
29	reg = <0xc9410000 0x10000
30		0xc1108140 0x8>;
31	clocks = <&clkc CLKID_ETH>,
32		 <&clkc CLKID_MPLL2>,
33		 <&clkc CLKID_MPLL2>;
34	clock-names = "stmmaceth", "clkin0", "clkin1";
35	resets = <&reset RESET_ETHERNET>;
36	reset-names = "stmmaceth";
37};
38
39&pinctrl_aobus {
40	compatible = "amlogic,meson8m2-aobus-pinctrl",
41		     "amlogic,meson8-aobus-pinctrl";
42};
43
44&pinctrl_cbus {
45	compatible = "amlogic,meson8m2-cbus-pinctrl",
46		     "amlogic,meson8-cbus-pinctrl";
47
48	eth_rgmii_pins: ethernet {
49		mux {
50			groups = "eth_tx_clk_50m", "eth_tx_en",
51				 "eth_txd3", "eth_txd2",
52				 "eth_txd1", "eth_txd0",
53				 "eth_rx_clk_in", "eth_rx_dv",
54				 "eth_rxd3", "eth_rxd2",
55				 "eth_rxd1", "eth_rxd0",
56				 "eth_mdio", "eth_mdc";
57			function = "ethernet";
58			bias-disable;
59		};
60	};
61};
62
63&saradc {
64	compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
65};
66
67&wdt {
68	compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
69};
70