1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2013 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/interrupt-controller/irq.h> 6#include "imx6sl-pinfunc.h" 7#include <dt-bindings/clock/imx6sl-clock.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 /* 13 * The decompressor and also some bootloaders rely on a 14 * pre-existing /chosen node to be available to insert the 15 * command line and merge other ATAGS info. 16 */ 17 chosen {}; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 mmc0 = &usdhc1; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc3; 32 mmc3 = &usdhc4; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 serial4 = &uart5; 38 spi0 = &ecspi1; 39 spi1 = &ecspi2; 40 spi2 = &ecspi3; 41 spi3 = &ecspi4; 42 usbphy0 = &usbphy1; 43 usbphy1 = &usbphy2; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu@0 { 51 compatible = "arm,cortex-a9"; 52 device_type = "cpu"; 53 reg = <0x0>; 54 next-level-cache = <&L2>; 55 operating-points = < 56 /* kHz uV */ 57 996000 1275000 58 792000 1175000 59 396000 975000 60 >; 61 fsl,soc-operating-points = < 62 /* ARM kHz SOC-PU uV */ 63 996000 1225000 64 792000 1175000 65 396000 1175000 66 >; 67 clock-latency = <61036>; /* two CLK32 periods */ 68 #cooling-cells = <2>; 69 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, 70 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, 71 <&clks IMX6SL_CLK_PLL1_SYS>; 72 clock-names = "arm", "pll2_pfd2_396m", "step", 73 "pll1_sw", "pll1_sys"; 74 arm-supply = <®_arm>; 75 pu-supply = <®_pu>; 76 soc-supply = <®_soc>; 77 }; 78 }; 79 80 clocks { 81 ckil { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <32768>; 85 }; 86 87 osc { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <24000000>; 91 }; 92 }; 93 94 tempmon: tempmon { 95 compatible = "fsl,imx6q-tempmon"; 96 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-parent = <&gpc>; 98 fsl,tempmon = <&anatop>; 99 fsl,tempmon-data = <&ocotp>; 100 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; 101 }; 102 103 pmu { 104 compatible = "arm,cortex-a9-pmu"; 105 interrupt-parent = <&gpc>; 106 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 107 }; 108 109 usbphynop1: usbphynop1 { 110 compatible = "usb-nop-xceiv"; 111 #phy-cells = <0>; 112 }; 113 114 soc { 115 #address-cells = <1>; 116 #size-cells = <1>; 117 compatible = "simple-bus"; 118 interrupt-parent = <&gpc>; 119 ranges; 120 121 ocram: sram@900000 { 122 compatible = "mmio-sram"; 123 reg = <0x00900000 0x20000>; 124 clocks = <&clks IMX6SL_CLK_OCRAM>; 125 }; 126 127 intc: interrupt-controller@a01000 { 128 compatible = "arm,cortex-a9-gic"; 129 #interrupt-cells = <3>; 130 interrupt-controller; 131 reg = <0x00a01000 0x1000>, 132 <0x00a00100 0x100>; 133 interrupt-parent = <&intc>; 134 }; 135 136 L2: l2-cache@a02000 { 137 compatible = "arm,pl310-cache"; 138 reg = <0x00a02000 0x1000>; 139 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 140 cache-unified; 141 cache-level = <2>; 142 arm,tag-latency = <4 2 3>; 143 arm,data-latency = <4 2 3>; 144 }; 145 146 aips1: aips-bus@2000000 { 147 compatible = "fsl,aips-bus", "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 reg = <0x02000000 0x100000>; 151 ranges; 152 153 spba: spba-bus@2000000 { 154 compatible = "fsl,spba-bus", "simple-bus"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 reg = <0x02000000 0x40000>; 158 ranges; 159 160 spdif: spdif@2004000 { 161 compatible = "fsl,imx6sl-spdif", 162 "fsl,imx35-spdif"; 163 reg = <0x02004000 0x4000>; 164 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 165 dmas = <&sdma 14 18 0>, 166 <&sdma 15 18 0>; 167 dma-names = "rx", "tx"; 168 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, 169 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, 170 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, 171 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, 172 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; 173 clock-names = "core", "rxtx0", 174 "rxtx1", "rxtx2", 175 "rxtx3", "rxtx4", 176 "rxtx5", "rxtx6", 177 "rxtx7", "spba"; 178 status = "disabled"; 179 }; 180 181 ecspi1: spi@2008000 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 185 reg = <0x02008000 0x4000>; 186 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clks IMX6SL_CLK_ECSPI1>, 188 <&clks IMX6SL_CLK_ECSPI1>; 189 clock-names = "ipg", "per"; 190 status = "disabled"; 191 }; 192 193 ecspi2: spi@200c000 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 197 reg = <0x0200c000 0x4000>; 198 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&clks IMX6SL_CLK_ECSPI2>, 200 <&clks IMX6SL_CLK_ECSPI2>; 201 clock-names = "ipg", "per"; 202 status = "disabled"; 203 }; 204 205 ecspi3: spi@2010000 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 209 reg = <0x02010000 0x4000>; 210 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&clks IMX6SL_CLK_ECSPI3>, 212 <&clks IMX6SL_CLK_ECSPI3>; 213 clock-names = "ipg", "per"; 214 status = "disabled"; 215 }; 216 217 ecspi4: spi@2014000 { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 221 reg = <0x02014000 0x4000>; 222 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&clks IMX6SL_CLK_ECSPI4>, 224 <&clks IMX6SL_CLK_ECSPI4>; 225 clock-names = "ipg", "per"; 226 status = "disabled"; 227 }; 228 229 uart5: serial@2018000 { 230 compatible = "fsl,imx6sl-uart", 231 "fsl,imx6q-uart", "fsl,imx21-uart"; 232 reg = <0x02018000 0x4000>; 233 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clks IMX6SL_CLK_UART>, 235 <&clks IMX6SL_CLK_UART_SERIAL>; 236 clock-names = "ipg", "per"; 237 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 238 dma-names = "rx", "tx"; 239 status = "disabled"; 240 }; 241 242 uart1: serial@2020000 { 243 compatible = "fsl,imx6sl-uart", 244 "fsl,imx6q-uart", "fsl,imx21-uart"; 245 reg = <0x02020000 0x4000>; 246 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clks IMX6SL_CLK_UART>, 248 <&clks IMX6SL_CLK_UART_SERIAL>; 249 clock-names = "ipg", "per"; 250 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 251 dma-names = "rx", "tx"; 252 status = "disabled"; 253 }; 254 255 uart2: serial@2024000 { 256 compatible = "fsl,imx6sl-uart", 257 "fsl,imx6q-uart", "fsl,imx21-uart"; 258 reg = <0x02024000 0x4000>; 259 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clks IMX6SL_CLK_UART>, 261 <&clks IMX6SL_CLK_UART_SERIAL>; 262 clock-names = "ipg", "per"; 263 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 264 dma-names = "rx", "tx"; 265 status = "disabled"; 266 }; 267 268 ssi1: ssi@2028000 { 269 #sound-dai-cells = <0>; 270 compatible = "fsl,imx6sl-ssi", 271 "fsl,imx51-ssi"; 272 reg = <0x02028000 0x4000>; 273 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&clks IMX6SL_CLK_SSI1_IPG>, 275 <&clks IMX6SL_CLK_SSI1>; 276 clock-names = "ipg", "baud"; 277 dmas = <&sdma 37 1 0>, 278 <&sdma 38 1 0>; 279 dma-names = "rx", "tx"; 280 fsl,fifo-depth = <15>; 281 status = "disabled"; 282 }; 283 284 ssi2: ssi@202c000 { 285 #sound-dai-cells = <0>; 286 compatible = "fsl,imx6sl-ssi", 287 "fsl,imx51-ssi"; 288 reg = <0x0202c000 0x4000>; 289 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clks IMX6SL_CLK_SSI2_IPG>, 291 <&clks IMX6SL_CLK_SSI2>; 292 clock-names = "ipg", "baud"; 293 dmas = <&sdma 41 1 0>, 294 <&sdma 42 1 0>; 295 dma-names = "rx", "tx"; 296 fsl,fifo-depth = <15>; 297 status = "disabled"; 298 }; 299 300 ssi3: ssi@2030000 { 301 #sound-dai-cells = <0>; 302 compatible = "fsl,imx6sl-ssi", 303 "fsl,imx51-ssi"; 304 reg = <0x02030000 0x4000>; 305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clks IMX6SL_CLK_SSI3_IPG>, 307 <&clks IMX6SL_CLK_SSI3>; 308 clock-names = "ipg", "baud"; 309 dmas = <&sdma 45 1 0>, 310 <&sdma 46 1 0>; 311 dma-names = "rx", "tx"; 312 fsl,fifo-depth = <15>; 313 status = "disabled"; 314 }; 315 316 uart3: serial@2034000 { 317 compatible = "fsl,imx6sl-uart", 318 "fsl,imx6q-uart", "fsl,imx21-uart"; 319 reg = <0x02034000 0x4000>; 320 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clks IMX6SL_CLK_UART>, 322 <&clks IMX6SL_CLK_UART_SERIAL>; 323 clock-names = "ipg", "per"; 324 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 325 dma-names = "rx", "tx"; 326 status = "disabled"; 327 }; 328 329 uart4: serial@2038000 { 330 compatible = "fsl,imx6sl-uart", 331 "fsl,imx6q-uart", "fsl,imx21-uart"; 332 reg = <0x02038000 0x4000>; 333 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&clks IMX6SL_CLK_UART>, 335 <&clks IMX6SL_CLK_UART_SERIAL>; 336 clock-names = "ipg", "per"; 337 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 }; 342 343 pwm1: pwm@2080000 { 344 #pwm-cells = <2>; 345 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 346 reg = <0x02080000 0x4000>; 347 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clks IMX6SL_CLK_PERCLK>, 349 <&clks IMX6SL_CLK_PWM1>; 350 clock-names = "ipg", "per"; 351 }; 352 353 pwm2: pwm@2084000 { 354 #pwm-cells = <2>; 355 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 356 reg = <0x02084000 0x4000>; 357 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clks IMX6SL_CLK_PERCLK>, 359 <&clks IMX6SL_CLK_PWM2>; 360 clock-names = "ipg", "per"; 361 }; 362 363 pwm3: pwm@2088000 { 364 #pwm-cells = <2>; 365 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 366 reg = <0x02088000 0x4000>; 367 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&clks IMX6SL_CLK_PERCLK>, 369 <&clks IMX6SL_CLK_PWM3>; 370 clock-names = "ipg", "per"; 371 }; 372 373 pwm4: pwm@208c000 { 374 #pwm-cells = <2>; 375 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 376 reg = <0x0208c000 0x4000>; 377 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clks IMX6SL_CLK_PERCLK>, 379 <&clks IMX6SL_CLK_PWM4>; 380 clock-names = "ipg", "per"; 381 }; 382 383 gpt: gpt@2098000 { 384 compatible = "fsl,imx6sl-gpt"; 385 reg = <0x02098000 0x4000>; 386 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clks IMX6SL_CLK_GPT>, 388 <&clks IMX6SL_CLK_GPT_SERIAL>; 389 clock-names = "ipg", "per"; 390 }; 391 392 gpio1: gpio@209c000 { 393 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 394 reg = <0x0209c000 0x4000>; 395 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 396 <0 67 IRQ_TYPE_LEVEL_HIGH>; 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, 402 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, 403 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, 404 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, 405 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, 406 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; 407 }; 408 409 gpio2: gpio@20a0000 { 410 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 411 reg = <0x020a0000 0x4000>; 412 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 413 <0 69 IRQ_TYPE_LEVEL_HIGH>; 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, 419 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, 420 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, 421 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, 422 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, 423 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, 424 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; 425 }; 426 427 gpio3: gpio@20a4000 { 428 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 429 reg = <0x020a4000 0x4000>; 430 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 431 <0 71 IRQ_TYPE_LEVEL_HIGH>; 432 gpio-controller; 433 #gpio-cells = <2>; 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, 437 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, 438 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, 439 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, 440 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, 441 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, 442 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, 443 <&iomuxc 31 102 1>; 444 }; 445 446 gpio4: gpio@20a8000 { 447 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 448 reg = <0x020a8000 0x4000>; 449 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 450 <0 73 IRQ_TYPE_LEVEL_HIGH>; 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, 456 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, 457 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, 458 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, 459 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, 460 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, 461 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, 462 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, 463 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, 464 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, 465 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, 466 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, 467 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, 468 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, 469 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; 470 }; 471 472 gpio5: gpio@20ac000 { 473 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 474 reg = <0x020ac000 0x4000>; 475 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 476 <0 75 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, 482 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, 483 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, 484 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, 485 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, 486 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, 487 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, 488 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, 489 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, 490 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, 491 <&iomuxc 21 161 1>; 492 }; 493 494 kpp: kpp@20b8000 { 495 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; 496 reg = <0x020b8000 0x4000>; 497 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clks IMX6SL_CLK_IPG>; 499 status = "disabled"; 500 }; 501 502 wdog1: wdog@20bc000 { 503 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 504 reg = <0x020bc000 0x4000>; 505 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clks IMX6SL_CLK_IPG>; 507 }; 508 509 wdog2: wdog@20c0000 { 510 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 511 reg = <0x020c0000 0x4000>; 512 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clks IMX6SL_CLK_IPG>; 514 status = "disabled"; 515 }; 516 517 clks: ccm@20c4000 { 518 compatible = "fsl,imx6sl-ccm"; 519 reg = <0x020c4000 0x4000>; 520 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 521 <0 88 IRQ_TYPE_LEVEL_HIGH>; 522 #clock-cells = <1>; 523 }; 524 525 anatop: anatop@20c8000 { 526 compatible = "fsl,imx6sl-anatop", 527 "fsl,imx6q-anatop", 528 "syscon", "simple-bus"; 529 reg = <0x020c8000 0x1000>; 530 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 531 <0 54 IRQ_TYPE_LEVEL_HIGH>, 532 <0 127 IRQ_TYPE_LEVEL_HIGH>; 533 534 reg_vdd1p1: regulator-1p1 { 535 compatible = "fsl,anatop-regulator"; 536 regulator-name = "vdd1p1"; 537 regulator-min-microvolt = <1000000>; 538 regulator-max-microvolt = <1200000>; 539 regulator-always-on; 540 anatop-reg-offset = <0x110>; 541 anatop-vol-bit-shift = <8>; 542 anatop-vol-bit-width = <5>; 543 anatop-min-bit-val = <4>; 544 anatop-min-voltage = <800000>; 545 anatop-max-voltage = <1375000>; 546 anatop-enable-bit = <0>; 547 }; 548 549 reg_vdd3p0: regulator-3p0 { 550 compatible = "fsl,anatop-regulator"; 551 regulator-name = "vdd3p0"; 552 regulator-min-microvolt = <2800000>; 553 regulator-max-microvolt = <3150000>; 554 regulator-always-on; 555 anatop-reg-offset = <0x120>; 556 anatop-vol-bit-shift = <8>; 557 anatop-vol-bit-width = <5>; 558 anatop-min-bit-val = <0>; 559 anatop-min-voltage = <2625000>; 560 anatop-max-voltage = <3400000>; 561 anatop-enable-bit = <0>; 562 }; 563 564 reg_vdd2p5: regulator-2p5 { 565 compatible = "fsl,anatop-regulator"; 566 regulator-name = "vdd2p5"; 567 regulator-min-microvolt = <2250000>; 568 regulator-max-microvolt = <2750000>; 569 regulator-always-on; 570 anatop-reg-offset = <0x130>; 571 anatop-vol-bit-shift = <8>; 572 anatop-vol-bit-width = <5>; 573 anatop-min-bit-val = <0>; 574 anatop-min-voltage = <2100000>; 575 anatop-max-voltage = <2850000>; 576 anatop-enable-bit = <0>; 577 }; 578 579 reg_arm: regulator-vddcore { 580 compatible = "fsl,anatop-regulator"; 581 regulator-name = "vddarm"; 582 regulator-min-microvolt = <725000>; 583 regulator-max-microvolt = <1450000>; 584 regulator-always-on; 585 anatop-reg-offset = <0x140>; 586 anatop-vol-bit-shift = <0>; 587 anatop-vol-bit-width = <5>; 588 anatop-delay-reg-offset = <0x170>; 589 anatop-delay-bit-shift = <24>; 590 anatop-delay-bit-width = <2>; 591 anatop-min-bit-val = <1>; 592 anatop-min-voltage = <725000>; 593 anatop-max-voltage = <1450000>; 594 }; 595 596 reg_pu: regulator-vddpu { 597 compatible = "fsl,anatop-regulator"; 598 regulator-name = "vddpu"; 599 regulator-min-microvolt = <725000>; 600 regulator-max-microvolt = <1450000>; 601 anatop-reg-offset = <0x140>; 602 anatop-vol-bit-shift = <9>; 603 anatop-vol-bit-width = <5>; 604 anatop-delay-reg-offset = <0x170>; 605 anatop-delay-bit-shift = <26>; 606 anatop-delay-bit-width = <2>; 607 anatop-min-bit-val = <1>; 608 anatop-min-voltage = <725000>; 609 anatop-max-voltage = <1450000>; 610 }; 611 612 reg_soc: regulator-vddsoc { 613 compatible = "fsl,anatop-regulator"; 614 regulator-name = "vddsoc"; 615 regulator-min-microvolt = <725000>; 616 regulator-max-microvolt = <1450000>; 617 regulator-always-on; 618 anatop-reg-offset = <0x140>; 619 anatop-vol-bit-shift = <18>; 620 anatop-vol-bit-width = <5>; 621 anatop-delay-reg-offset = <0x170>; 622 anatop-delay-bit-shift = <28>; 623 anatop-delay-bit-width = <2>; 624 anatop-min-bit-val = <1>; 625 anatop-min-voltage = <725000>; 626 anatop-max-voltage = <1450000>; 627 }; 628 }; 629 630 usbphy1: usbphy@20c9000 { 631 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 632 reg = <0x020c9000 0x1000>; 633 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clks IMX6SL_CLK_USBPHY1>; 635 fsl,anatop = <&anatop>; 636 }; 637 638 usbphy2: usbphy@20ca000 { 639 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 640 reg = <0x020ca000 0x1000>; 641 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clks IMX6SL_CLK_USBPHY2>; 643 fsl,anatop = <&anatop>; 644 }; 645 646 snvs: snvs@20cc000 { 647 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 648 reg = <0x020cc000 0x4000>; 649 650 snvs_rtc: snvs-rtc-lp { 651 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 652 regmap = <&snvs>; 653 offset = <0x34>; 654 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 655 <0 20 IRQ_TYPE_LEVEL_HIGH>; 656 }; 657 658 snvs_poweroff: snvs-poweroff { 659 compatible = "syscon-poweroff"; 660 regmap = <&snvs>; 661 offset = <0x38>; 662 value = <0x60>; 663 mask = <0x60>; 664 status = "disabled"; 665 }; 666 }; 667 668 epit1: epit@20d0000 { 669 reg = <0x020d0000 0x4000>; 670 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 671 }; 672 673 epit2: epit@20d4000 { 674 reg = <0x020d4000 0x4000>; 675 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 676 }; 677 678 src: src@20d8000 { 679 compatible = "fsl,imx6sl-src", "fsl,imx51-src"; 680 reg = <0x020d8000 0x4000>; 681 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 682 <0 96 IRQ_TYPE_LEVEL_HIGH>; 683 #reset-cells = <1>; 684 }; 685 686 gpc: gpc@20dc000 { 687 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; 688 reg = <0x020dc000 0x4000>; 689 interrupt-controller; 690 #interrupt-cells = <3>; 691 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-parent = <&intc>; 693 clocks = <&clks IMX6SL_CLK_IPG>; 694 clock-names = "ipg"; 695 696 pgc { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 700 power-domain@0 { 701 reg = <0>; 702 #power-domain-cells = <0>; 703 }; 704 705 pd_pu: power-domain@1 { 706 reg = <1>; 707 #power-domain-cells = <0>; 708 power-supply = <®_pu>; 709 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, 710 <&clks IMX6SL_CLK_GPU2D_PODF>; 711 }; 712 713 pd_disp: power-domain@2 { 714 reg = <2>; 715 #power-domain-cells = <0>; 716 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, 717 <&clks IMX6SL_CLK_LCDIF_PIX>, 718 <&clks IMX6SL_CLK_EPDC_AXI>, 719 <&clks IMX6SL_CLK_EPDC_PIX>, 720 <&clks IMX6SL_CLK_PXP_AXI>; 721 }; 722 }; 723 }; 724 725 gpr: iomuxc-gpr@20e0000 { 726 compatible = "fsl,imx6sl-iomuxc-gpr", 727 "fsl,imx6q-iomuxc-gpr", "syscon"; 728 reg = <0x020e0000 0x38>; 729 }; 730 731 iomuxc: iomuxc@20e0000 { 732 compatible = "fsl,imx6sl-iomuxc"; 733 reg = <0x020e0000 0x4000>; 734 }; 735 736 csi: csi@20e4000 { 737 reg = <0x020e4000 0x4000>; 738 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 739 }; 740 741 spdc: spdc@20e8000 { 742 reg = <0x020e8000 0x4000>; 743 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 744 }; 745 746 sdma: sdma@20ec000 { 747 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; 748 reg = <0x020ec000 0x4000>; 749 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&clks IMX6SL_CLK_SDMA>, 751 <&clks IMX6SL_CLK_AHB>; 752 clock-names = "ipg", "ahb"; 753 #dma-cells = <3>; 754 /* imx6sl reuses imx6q sdma firmware */ 755 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 756 }; 757 758 pxp: pxp@20f0000 { 759 reg = <0x020f0000 0x4000>; 760 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 epdc: epdc@20f4000 { 764 reg = <0x020f4000 0x4000>; 765 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 766 }; 767 768 lcdif: lcdif@20f8000 { 769 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; 770 reg = <0x020f8000 0x4000>; 771 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, 773 <&clks IMX6SL_CLK_LCDIF_AXI>, 774 <&clks IMX6SL_CLK_DUMMY>; 775 clock-names = "pix", "axi", "disp_axi"; 776 status = "disabled"; 777 power-domains = <&pd_disp>; 778 }; 779 780 dcp: dcp@20fc000 { 781 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; 782 reg = <0x020fc000 0x4000>; 783 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, 784 <0 100 IRQ_TYPE_LEVEL_HIGH>, 785 <0 101 IRQ_TYPE_LEVEL_HIGH>; 786 }; 787 }; 788 789 aips2: aips-bus@2100000 { 790 compatible = "fsl,aips-bus", "simple-bus"; 791 #address-cells = <1>; 792 #size-cells = <1>; 793 reg = <0x02100000 0x100000>; 794 ranges; 795 796 usbotg1: usb@2184000 { 797 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 798 reg = <0x02184000 0x200>; 799 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clks IMX6SL_CLK_USBOH3>; 801 fsl,usbphy = <&usbphy1>; 802 fsl,usbmisc = <&usbmisc 0>; 803 ahb-burst-config = <0x0>; 804 tx-burst-size-dword = <0x10>; 805 rx-burst-size-dword = <0x10>; 806 status = "disabled"; 807 }; 808 809 usbotg2: usb@2184200 { 810 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 811 reg = <0x02184200 0x200>; 812 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clks IMX6SL_CLK_USBOH3>; 814 fsl,usbphy = <&usbphy2>; 815 fsl,usbmisc = <&usbmisc 1>; 816 ahb-burst-config = <0x0>; 817 tx-burst-size-dword = <0x10>; 818 rx-burst-size-dword = <0x10>; 819 status = "disabled"; 820 }; 821 822 usbh: usb@2184400 { 823 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 824 reg = <0x02184400 0x200>; 825 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&clks IMX6SL_CLK_USBOH3>; 827 fsl,usbphy = <&usbphynop1>; 828 phy_type = "hsic"; 829 fsl,usbmisc = <&usbmisc 2>; 830 dr_mode = "host"; 831 ahb-burst-config = <0x0>; 832 tx-burst-size-dword = <0x10>; 833 rx-burst-size-dword = <0x10>; 834 status = "disabled"; 835 }; 836 837 usbmisc: usbmisc@2184800 { 838 #index-cells = <1>; 839 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; 840 reg = <0x02184800 0x200>; 841 clocks = <&clks IMX6SL_CLK_USBOH3>; 842 }; 843 844 fec: ethernet@2188000 { 845 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; 846 reg = <0x02188000 0x4000>; 847 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clks IMX6SL_CLK_ENET>, 849 <&clks IMX6SL_CLK_ENET_REF>; 850 clock-names = "ipg", "ahb"; 851 status = "disabled"; 852 }; 853 854 usdhc1: usdhc@2190000 { 855 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 856 reg = <0x02190000 0x4000>; 857 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&clks IMX6SL_CLK_USDHC1>, 859 <&clks IMX6SL_CLK_USDHC1>, 860 <&clks IMX6SL_CLK_USDHC1>; 861 clock-names = "ipg", "ahb", "per"; 862 bus-width = <4>; 863 status = "disabled"; 864 }; 865 866 usdhc2: usdhc@2194000 { 867 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 868 reg = <0x02194000 0x4000>; 869 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clks IMX6SL_CLK_USDHC2>, 871 <&clks IMX6SL_CLK_USDHC2>, 872 <&clks IMX6SL_CLK_USDHC2>; 873 clock-names = "ipg", "ahb", "per"; 874 bus-width = <4>; 875 status = "disabled"; 876 }; 877 878 usdhc3: usdhc@2198000 { 879 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 880 reg = <0x02198000 0x4000>; 881 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clks IMX6SL_CLK_USDHC3>, 883 <&clks IMX6SL_CLK_USDHC3>, 884 <&clks IMX6SL_CLK_USDHC3>; 885 clock-names = "ipg", "ahb", "per"; 886 bus-width = <4>; 887 status = "disabled"; 888 }; 889 890 usdhc4: usdhc@219c000 { 891 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 892 reg = <0x0219c000 0x4000>; 893 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&clks IMX6SL_CLK_USDHC4>, 895 <&clks IMX6SL_CLK_USDHC4>, 896 <&clks IMX6SL_CLK_USDHC4>; 897 clock-names = "ipg", "ahb", "per"; 898 bus-width = <4>; 899 status = "disabled"; 900 }; 901 902 i2c1: i2c@21a0000 { 903 #address-cells = <1>; 904 #size-cells = <0>; 905 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 906 reg = <0x021a0000 0x4000>; 907 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clks IMX6SL_CLK_I2C1>; 909 status = "disabled"; 910 }; 911 912 i2c2: i2c@21a4000 { 913 #address-cells = <1>; 914 #size-cells = <0>; 915 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 916 reg = <0x021a4000 0x4000>; 917 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clks IMX6SL_CLK_I2C2>; 919 status = "disabled"; 920 }; 921 922 i2c3: i2c@21a8000 { 923 #address-cells = <1>; 924 #size-cells = <0>; 925 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 926 reg = <0x021a8000 0x4000>; 927 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clks IMX6SL_CLK_I2C3>; 929 status = "disabled"; 930 }; 931 932 memory-controller@21b0000 { 933 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; 934 reg = <0x021b0000 0x4000>; 935 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; 936 }; 937 938 rngb: rngb@21b4000 { 939 reg = <0x021b4000 0x4000>; 940 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 941 }; 942 943 weim: weim@21b8000 { 944 #address-cells = <2>; 945 #size-cells = <1>; 946 reg = <0x021b8000 0x4000>; 947 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 948 fsl,weim-cs-gpr = <&gpr>; 949 status = "disabled"; 950 }; 951 952 ocotp: ocotp@21bc000 { 953 compatible = "fsl,imx6sl-ocotp", "syscon"; 954 reg = <0x021bc000 0x4000>; 955 clocks = <&clks IMX6SL_CLK_OCOTP>; 956 }; 957 958 audmux: audmux@21d8000 { 959 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; 960 reg = <0x021d8000 0x4000>; 961 status = "disabled"; 962 }; 963 }; 964 965 gpu_2d: gpu@2200000 { 966 compatible = "vivante,gc"; 967 reg = <0x02200000 0x4000>; 968 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, 970 <&clks IMX6SL_CLK_GPU2D_OVG>; 971 clock-names = "bus", "core"; 972 power-domains = <&pd_pu>; 973 }; 974 975 gpu_vg: gpu@2204000 { 976 compatible = "vivante,gc"; 977 reg = <0x02204000 0x4000>; 978 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, 980 <&clks IMX6SL_CLK_GPU2D_OVG>; 981 clock-names = "bus", "core"; 982 power-domains = <&pd_pu>; 983 }; 984 }; 985}; 986
