1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	/* these are used by bootloader for disabling nodes */
10	aliases {
11		led0 = &led0;
12		led1 = &led1;
13		nand = &gpmi;
14		usb0 = &usbh1;
15		usb1 = &usbotg;
16	};
17
18	chosen {
19		bootargs = "console=ttymxc1,115200";
20	};
21
22	leds {
23		compatible = "gpio-leds";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_gpio_leds>;
26
27		led0: user1 {
28			label = "user1";
29			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
30			default-state = "on";
31			linux,default-trigger = "heartbeat";
32		};
33
34		led1: user2 {
35			label = "user2";
36			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
37			default-state = "off";
38		};
39	};
40
41	memory@10000000 {
42		device_type = "memory";
43		reg = <0x10000000 0x20000000>;
44	};
45
46	pps {
47		compatible = "pps-gpio";
48		pinctrl-names = "default";
49		pinctrl-0 = <&pinctrl_pps>;
50		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
51		status = "okay";
52	};
53
54	reg_3p3v: regulator-3p3v {
55		compatible = "regulator-fixed";
56		regulator-name = "3P3V";
57		regulator-min-microvolt = <3300000>;
58		regulator-max-microvolt = <3300000>;
59		regulator-always-on;
60	};
61
62	reg_5p0v: regulator-5p0v {
63		compatible = "regulator-fixed";
64		regulator-name = "5P0V";
65		regulator-min-microvolt = <5000000>;
66		regulator-max-microvolt = <5000000>;
67		regulator-always-on;
68	};
69
70	reg_usb_otg_vbus: regulator-usb-otg-vbus {
71		compatible = "regulator-fixed";
72		regulator-name = "usb_otg_vbus";
73		regulator-min-microvolt = <5000000>;
74		regulator-max-microvolt = <5000000>;
75		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
76		enable-active-high;
77	};
78};
79
80&fec {
81	pinctrl-names = "default";
82	pinctrl-0 = <&pinctrl_enet>;
83	phy-mode = "rgmii-id";
84	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
85	status = "okay";
86};
87
88&gpmi {
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_gpmi_nand>;
91	status = "okay";
92};
93
94&hdmi {
95	ddc-i2c-bus = <&i2c3>;
96	status = "okay";
97};
98
99&i2c1 {
100	clock-frequency = <100000>;
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_i2c1>;
103	status = "okay";
104
105	eeprom1: eeprom@50 {
106		compatible = "atmel,24c02";
107		reg = <0x50>;
108		pagesize = <16>;
109	};
110
111	eeprom2: eeprom@51 {
112		compatible = "atmel,24c02";
113		reg = <0x51>;
114		pagesize = <16>;
115	};
116
117	eeprom3: eeprom@52 {
118		compatible = "atmel,24c02";
119		reg = <0x52>;
120		pagesize = <16>;
121	};
122
123	eeprom4: eeprom@53 {
124		compatible = "atmel,24c02";
125		reg = <0x53>;
126		pagesize = <16>;
127	};
128
129	gpio: pca9555@23 {
130		compatible = "nxp,pca9555";
131		reg = <0x23>;
132		gpio-controller;
133		#gpio-cells = <2>;
134	};
135
136	rtc: ds1672@68 {
137		compatible = "dallas,ds1672";
138		reg = <0x68>;
139	};
140};
141
142&i2c2 {
143	clock-frequency = <100000>;
144	pinctrl-names = "default";
145	pinctrl-0 = <&pinctrl_i2c2>;
146	status = "okay";
147
148	ltc3676: pmic@3c {
149		compatible = "lltc,ltc3676";
150		reg = <0x3c>;
151		pinctrl-names = "default";
152		pinctrl-0 = <&pinctrl_pmic>;
153		interrupt-parent = <&gpio1>;
154		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
155
156		regulators {
157			/* VDD_SOC (1+R1/R2 = 1.635) */
158			reg_vdd_soc: sw1 {
159				regulator-name = "vddsoc";
160				regulator-min-microvolt = <674400>;
161				regulator-max-microvolt = <1308000>;
162				lltc,fb-voltage-divider = <127000 200000>;
163				regulator-ramp-delay = <7000>;
164				regulator-boot-on;
165				regulator-always-on;
166			};
167
168			/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
169			reg_1p8v: sw2 {
170				regulator-name = "vdd1p8";
171				regulator-min-microvolt = <1033310>;
172				regulator-max-microvolt = <2004000>;
173				lltc,fb-voltage-divider = <301000 200000>;
174				regulator-ramp-delay = <7000>;
175				regulator-boot-on;
176				regulator-always-on;
177			};
178
179			/* VDD_ARM (1+R1/R2 = 1.635) */
180			reg_vdd_arm: sw3 {
181				regulator-name = "vddarm";
182				regulator-min-microvolt = <674400>;
183				regulator-max-microvolt = <1308000>;
184				lltc,fb-voltage-divider = <127000 200000>;
185				regulator-ramp-delay = <7000>;
186				regulator-boot-on;
187				regulator-always-on;
188			};
189
190			/* VDD_DDR (1+R1/R2 = 2.105) */
191			reg_vdd_ddr: sw4 {
192				regulator-name = "vddddr";
193				regulator-min-microvolt = <868310>;
194				regulator-max-microvolt = <1684000>;
195				lltc,fb-voltage-divider = <221000 200000>;
196				regulator-ramp-delay = <7000>;
197				regulator-boot-on;
198				regulator-always-on;
199			};
200
201			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
202			reg_2p5v: ldo2 {
203				regulator-name = "vdd2p5";
204				regulator-min-microvolt = <2490375>;
205				regulator-max-microvolt = <2490375>;
206				lltc,fb-voltage-divider = <487000 200000>;
207				regulator-boot-on;
208				regulator-always-on;
209			};
210
211			/* VDD_HIGH (1+R1/R2 = 4.17) */
212			reg_3p0v: ldo4 {
213				regulator-name = "vdd3p0";
214				regulator-min-microvolt = <3023250>;
215				regulator-max-microvolt = <3023250>;
216				lltc,fb-voltage-divider = <634000 200000>;
217				regulator-boot-on;
218				regulator-always-on;
219			};
220		};
221	};
222};
223
224&i2c3 {
225	clock-frequency = <100000>;
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_i2c3>;
228	status = "okay";
229
230	adv7180: camera@20 {
231		compatible = "adi,adv7180";
232		pinctrl-names = "default";
233		pinctrl-0 = <&pinctrl_adv7180>;
234		reg = <0x20>;
235		powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
236		interrupt-parent = <&gpio5>;
237		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
238
239		port {
240			adv7180_to_ipu1_csi0_mux: endpoint {
241				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
242				bus-width = <8>;
243			};
244		};
245	};
246};
247
248&ipu1_csi0_from_ipu1_csi0_mux {
249	bus-width = <8>;
250};
251
252&ipu1_csi0_mux_from_parallel_sensor {
253	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
254	bus-width = <8>;
255};
256
257&ipu1_csi0 {
258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_ipu1_csi0>;
260};
261
262&pcie {
263	pinctrl-names = "default";
264	pinctrl-0 = <&pinctrl_pcie>;
265	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
266	status = "okay";
267};
268
269&pwm2 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
272	status = "disabled";
273};
274
275&pwm3 {
276	pinctrl-names = "default";
277	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
278	status = "disabled";
279};
280
281&pwm4 {
282	pinctrl-names = "default";
283	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
284	status = "disabled";
285};
286
287&uart1 {
288	pinctrl-names = "default";
289	pinctrl-0 = <&pinctrl_uart1>;
290	status = "okay";
291};
292
293&uart2 {
294	pinctrl-names = "default";
295	pinctrl-0 = <&pinctrl_uart2>;
296	status = "okay";
297};
298
299&uart3 {
300	pinctrl-names = "default";
301	pinctrl-0 = <&pinctrl_uart3>;
302	status = "okay";
303};
304
305&uart5 {
306	pinctrl-names = "default";
307	pinctrl-0 = <&pinctrl_uart5>;
308	status = "okay";
309};
310
311&usbotg {
312	vbus-supply = <&reg_usb_otg_vbus>;
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_usbotg>;
315	disable-over-current;
316	status = "okay";
317};
318
319&usbh1 {
320	status = "okay";
321};
322
323&wdog1 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pinctrl_wdog>;
326	fsl,ext-reset-output;
327};
328
329&iomuxc {
330	pinctrl_adv7180: adv7180grp {
331		fsl,pins = <
332			MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x0001b0b0
333			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b0
334		>;
335	};
336
337	pinctrl_enet: enetgrp {
338		fsl,pins = <
339			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
340			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
341			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
342			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
343			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
344			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
345			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
346			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
347			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
348			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
349			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
350			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
351			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
352			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
353			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
354			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
355			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0 /* PHY Reset */
356		>;
357	};
358
359	pinctrl_gpio_leds: gpioledsgrp {
360		fsl,pins = <
361			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
362			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
363		>;
364	};
365
366	pinctrl_gpmi_nand: gpminandgrp {
367		fsl,pins = <
368			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
369			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
370			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
371			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
372			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
373			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
374			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
375			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
376			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
377			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
378			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
379			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
380			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
381			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
382			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
383		>;
384	};
385
386	pinctrl_i2c1: i2c1grp {
387		fsl,pins = <
388			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
389			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
390		>;
391	};
392
393	pinctrl_i2c2: i2c2grp {
394		fsl,pins = <
395			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
396			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
397		>;
398	};
399
400	pinctrl_i2c3: i2c3grp {
401		fsl,pins = <
402			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
403			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
404		>;
405	};
406
407	pinctrl_ipu1_csi0: ipu1csi0grp {
408		fsl,pins = <
409			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
410			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
411			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
412			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
413			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
414			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
415			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
416			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
417			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
418			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
419			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
420		>;
421	};
422
423	pinctrl_pcie: pciegrp {
424		fsl,pins = <
425			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0
426		>;
427	};
428
429	pinctrl_pmic: pmicgrp {
430		fsl,pins = <
431			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x0001b0b0 /* PMIC_IRQ# */
432		>;
433	};
434
435	pinctrl_pps: ppsgrp {
436		fsl,pins = <
437			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
438		>;
439	};
440
441	pinctrl_pwm2: pwm2grp {
442		fsl,pins = <
443			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
444		>;
445	};
446
447	pinctrl_pwm3: pwm3grp {
448		fsl,pins = <
449			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
450		>;
451	};
452
453	pinctrl_pwm4: pwm4grp {
454		fsl,pins = <
455			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
456		>;
457	};
458
459	pinctrl_uart1: uart1grp {
460		fsl,pins = <
461			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
462			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
463		>;
464	};
465
466	pinctrl_uart2: uart2grp {
467		fsl,pins = <
468			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
469			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
470		>;
471	};
472
473	pinctrl_uart3: uart3grp {
474		fsl,pins = <
475			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
476			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
477		>;
478	};
479
480	pinctrl_uart5: uart5grp {
481		fsl,pins = <
482			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
483			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
484		>;
485	};
486
487	pinctrl_usbotg: usbotggrp {
488		fsl,pins = <
489			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
490			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* OTG_PWR_EN */
491		>;
492	};
493
494	pinctrl_wdog: wdoggrp {
495		fsl,pins = <
496			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
497		>;
498	};
499};
500