1/* 2 * Copyright 2016 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include "arm-realview-pbx.dtsi" 25 26/ { 27 /* 28 * This is the RealView Platform Baseboard Explore for Cortex-A9 29 * (HBI0182 + HBI0183) as described in ARM DUI 0440B 30 */ 31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 32 arm,hbi = <0x182>; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 enable-method = "arm,realview-smp"; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&CPU0>; 43 }; 44 core1 { 45 cpu = <&CPU1>; 46 }; 47 }; 48 }; 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a9"; 52 reg = <0x0>; 53 next-level-cache = <&L2>; 54 }; 55 CPU1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a9"; 58 reg = <0x1>; 59 next-level-cache = <&L2>; 60 }; 61 }; 62 63 L2: l2-cache { 64 compatible = "arm,pl310-cache"; 65 reg = <0x1f002000 0x1000>; 66 cache-unified; 67 cache-level = <2>; 68 /* 69 * Override default cache size, sets and 70 * associativity as these may be erroneously set 71 * up by boot loader(s). 72 */ 73 cache-size = <131072>; // 128KB 74 cache-sets = <512>; 75 cache-line-size = <32>; 76 arm,parity-disable; 77 arm,tag-latency = <1 1 1>; 78 arm,data-latency = <1 1 1>; 79 }; 80 81 scu: scu@1f000000 { 82 compatible = "arm,cortex-a9-scu"; 83 reg = <0x1f000000 0x100>; 84 }; 85 86 twd_timer: timer@1f000600 { 87 compatible = "arm,cortex-a9-twd-timer"; 88 reg = <0x1f000600 0x20>; 89 interrupt-parent = <&intc>; 90 interrupts = <1 13 0xf04>; 91 }; 92 93 twd_wdog: watchdog@1f000620 { 94 compatible = "arm,cortex-a9-twd-wdt"; 95 reg = <0x1f000620 0x20>; 96 interrupt-parent = <&intc>; 97 interrupts = <1 14 0xf04>; 98 }; 99 100 pmu: pmu@0 { 101 compatible = "arm,cortex-a9-pmu"; 102 interrupt-parent = <&intc>; 103 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, 104 <0 45 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-affinity = <&CPU0>, <&CPU1>; 106 }; 107 108 /* Primary GIC PL390 interrupt controller in the test chip */ 109 intc: interrupt-controller@1f000000 { 110 compatible = "arm,cortex-a9-gic"; 111 #interrupt-cells = <3>; 112 #address-cells = <1>; 113 interrupt-controller; 114 reg = <0x1f001000 0x1000>, 115 <0x1f000100 0x100>; 116 }; 117}; 118 119ðernet { 120 interrupt-parent = <&intc>; 121 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 122}; 123 124&usb { 125 interrupt-parent = <&intc>; 126 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 127}; 128 129&serial0 { 130 interrupt-parent = <&intc>; 131 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; 132}; 133 134&serial1 { 135 interrupt-parent = <&intc>; 136 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 137}; 138 139&serial2 { 140 interrupt-parent = <&intc>; 141 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 142}; 143 144&serial3 { 145 interrupt-parent = <&intc>; 146 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 147}; 148 149&ssp { 150 interrupt-parent = <&intc>; 151 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 152}; 153 154&wdog0 { 155 interrupt-parent = <&intc>; 156 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 157}; 158 159&wdog1 { 160 interrupt-parent = <&intc>; 161 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 162}; 163 164&timer01 { 165 interrupt-parent = <&intc>; 166 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 167}; 168 169&timer23 { 170 interrupt-parent = <&intc>; 171 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 172}; 173 174&gpio0 { 175 interrupt-parent = <&intc>; 176 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 177}; 178 179&gpio1 { 180 interrupt-parent = <&intc>; 181 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 182}; 183 184&gpio2 { 185 interrupt-parent = <&intc>; 186 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 187}; 188 189&rtc { 190 interrupt-parent = <&intc>; 191 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 192}; 193 194&timer45 { 195 interrupt-parent = <&intc>; 196 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 197}; 198 199&timer67 { 200 interrupt-parent = <&intc>; 201 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 202}; 203 204&aaci { 205 interrupt-parent = <&intc>; 206 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 207}; 208 209&mmc { 210 interrupt-parent = <&intc>; 211 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 212 <0 18 IRQ_TYPE_LEVEL_HIGH>; 213}; 214 215&kmi0 { 216 interrupt-parent = <&intc>; 217 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 218}; 219 220&kmi1 { 221 interrupt-parent = <&intc>; 222 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 223}; 224 225&clcd { 226 interrupt-parent = <&intc>; 227 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 228}; 229
