1============================== 2PXA2xx SPI on SSP driver HOWTO 3============================== 4 5This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx 6synchronous serial port into a SPI master controller 7(see Documentation/spi/spi-summary.rst). The driver has the following features 8 9- Support for any PXA2xx SSP 10- SSP PIO and SSP DMA data transfers. 11- External and Internal (SSPFRM) chip selects. 12- Per slave device (chip) configuration. 13- Full suspend, freeze, resume support. 14 15The driver is built around a "spi_message" fifo serviced by workqueue and a 16tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet 17(pump_transfer) is responsible for queuing SPI transactions and setting up and 18launching the dma/interrupt driven transfers. 19 20Declaring PXA2xx Master Controllers 21----------------------------------- 22Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a 23"platform device". The master configuration is passed to the driver via a table 24found in include/linux/spi/pxa2xx_spi.h:: 25 26 struct pxa2xx_spi_controller { 27 u16 num_chipselect; 28 u8 enable_dma; 29 }; 30 31The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of 32slave device (chips) attached to this SPI master. 33 34The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should 35be used. This caused the driver to acquire two DMA channels: rx_channel and 36tx_channel. The rx_channel has a higher DMA service priority the tx_channel. 37See the "PXA2xx Developer Manual" section "DMA Controller". 38 39NSSP MASTER SAMPLE 40------------------ 41Below is a sample configuration using the PXA255 NSSP:: 42 43 static struct resource pxa_spi_nssp_resources[] = { 44 [0] = { 45 .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */ 46 .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */ 47 .flags = IORESOURCE_MEM, 48 }, 49 [1] = { 50 .start = IRQ_NSSP, /* NSSP IRQ */ 51 .end = IRQ_NSSP, 52 .flags = IORESOURCE_IRQ, 53 }, 54 }; 55 56 static struct pxa2xx_spi_controller pxa_nssp_master_info = { 57 .num_chipselect = 1, /* Matches the number of chips attached to NSSP */ 58 .enable_dma = 1, /* Enables NSSP DMA */ 59 }; 60 61 static struct platform_device pxa_spi_nssp = { 62 .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */ 63 .id = 2, /* Bus number, MUST MATCH SSP number 1..n */ 64 .resource = pxa_spi_nssp_resources, 65 .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources), 66 .dev = { 67 .platform_data = &pxa_nssp_master_info, /* Passed to driver */ 68 }, 69 }; 70 71 static struct platform_device *devices[] __initdata = { 72 &pxa_spi_nssp, 73 }; 74 75 static void __init board_init(void) 76 { 77 (void)platform_add_device(devices, ARRAY_SIZE(devices)); 78 } 79 80Declaring Slave Devices 81----------------------- 82Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c 83using the "spi_board_info" structure found in "linux/spi/spi.h". See 84"Documentation/spi/spi-summary.rst" for additional information. 85 86Each slave device attached to the PXA must provide slave specific configuration 87information via the structure "pxa2xx_spi_chip" found in 88"include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver 89will uses the configuration whenever the driver communicates with the slave 90device. All fields are optional. 91 92:: 93 94 struct pxa2xx_spi_chip { 95 u8 tx_threshold; 96 u8 rx_threshold; 97 u8 dma_burst_size; 98 u32 timeout; 99 u8 enable_loopback; 100 void (*cs_control)(u32 command); 101 }; 102 103The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are 104used to configure the SSP hardware fifo. These fields are critical to the 105performance of pxa2xx_spi driver and misconfiguration will result in rx 106fifo overruns (especially in PIO mode transfers). Good default values are:: 107 108 .tx_threshold = 8, 109 .rx_threshold = 8, 110 111The range is 1 to 16 where zero indicates "use default". 112 113The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA 114engine and is related the "spi_device.bits_per_word" field. Read and understand 115the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers 116to determine the correct value. An SSP configured for byte-wide transfers would 117use a value of 8. The driver will determine a reasonable default if 118dma_burst_size == 0. 119 120The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle 121trailing bytes in the SSP receiver fifo. The correct value for this field is 122dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific 123slave device. Please note that the PXA2xx SSP 1 does not support trailing byte 124timeouts and must busy-wait any trailing bytes. 125 126The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting 127into internal loopback mode. In this mode the SSP controller internally 128connects the SSPTX pin to the SSPRX pin. This is useful for initial setup 129testing. 130 131The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific 132function for asserting/deasserting a slave device chip select. If the field is 133NULL, the pxa2xx_spi master controller driver assumes that the SSP port is 134configured to use SSPFRM instead. 135 136NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the 137chipselect is dropped after each spi_transfer. Most devices need chip select 138asserted around the complete message. Use SSPFRM as a GPIO (through cs_control) 139to accommodate these chips. 140 141 142NSSP SLAVE SAMPLE 143----------------- 144The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the 145"spi_board_info.controller_data" field. Below is a sample configuration using 146the PXA255 NSSP. 147 148:: 149 150 /* Chip Select control for the CS8415A SPI slave device */ 151 static void cs8415a_cs_control(u32 command) 152 { 153 if (command & PXA2XX_CS_ASSERT) 154 GPCR(2) = GPIO_bit(2); 155 else 156 GPSR(2) = GPIO_bit(2); 157 } 158 159 /* Chip Select control for the CS8405A SPI slave device */ 160 static void cs8405a_cs_control(u32 command) 161 { 162 if (command & PXA2XX_CS_ASSERT) 163 GPCR(3) = GPIO_bit(3); 164 else 165 GPSR(3) = GPIO_bit(3); 166 } 167 168 static struct pxa2xx_spi_chip cs8415a_chip_info = { 169 .tx_threshold = 8, /* SSP hardward FIFO threshold */ 170 .rx_threshold = 8, /* SSP hardward FIFO threshold */ 171 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ 172 .timeout = 235, /* See Intel documentation */ 173 .cs_control = cs8415a_cs_control, /* Use external chip select */ 174 }; 175 176 static struct pxa2xx_spi_chip cs8405a_chip_info = { 177 .tx_threshold = 8, /* SSP hardward FIFO threshold */ 178 .rx_threshold = 8, /* SSP hardward FIFO threshold */ 179 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ 180 .timeout = 235, /* See Intel documentation */ 181 .cs_control = cs8405a_cs_control, /* Use external chip select */ 182 }; 183 184 static struct spi_board_info streetracer_spi_board_info[] __initdata = { 185 { 186 .modalias = "cs8415a", /* Name of spi_driver for this device */ 187 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ 188 .bus_num = 2, /* Framework bus number */ 189 .chip_select = 0, /* Framework chip select */ 190 .platform_data = NULL; /* No spi_driver specific config */ 191 .controller_data = &cs8415a_chip_info, /* Master chip config */ 192 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ 193 }, 194 { 195 .modalias = "cs8405a", /* Name of spi_driver for this device */ 196 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ 197 .bus_num = 2, /* Framework bus number */ 198 .chip_select = 1, /* Framework chip select */ 199 .controller_data = &cs8405a_chip_info, /* Master chip config */ 200 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ 201 }, 202 }; 203 204 static void __init streetracer_init(void) 205 { 206 spi_register_board_info(streetracer_spi_board_info, 207 ARRAY_SIZE(streetracer_spi_board_info)); 208 } 209 210 211DMA and PIO I/O Support 212----------------------- 213The pxa2xx_spi driver supports both DMA and interrupt driven PIO message 214transfers. The driver defaults to PIO mode and DMA transfers must be enabled 215by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA 216mode supports both coherent and stream based DMA mappings. 217 218The following logic is used to determine the type of I/O to be used on 219a per "spi_transfer" basis:: 220 221 if !enable_dma then 222 always use PIO transfers 223 224 if spi_message.len > 8191 then 225 print "rate limited" warning 226 use PIO transfers 227 228 if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then 229 use coherent DMA mode 230 231 if rx_buf and tx_buf are aligned on 8 byte boundary then 232 use streaming DMA mode 233 234 otherwise 235 use PIO transfer 236 237THANKS TO 238--------- 239 240David Brownell and others for mentoring the development of this driver. 241
