1Amlogic Meson GX DWC3 USB SoC controller
2
3Required properties:
4- compatible:	depending on the SoC this should contain one of:
5			* amlogic,meson-axg-dwc3
6			* amlogic,meson-gxl-dwc3
7- clocks:	a handle for the "USB general" clock
8- clock-names:	must be "usb_general"
9- resets:	a handle for the shared "USB OTG" reset line
10- reset-names:	must be "usb_otg"
11
12Required child node:
13A child node must exist to represent the core DWC3 IP block. The name of
14the node is not important. The content of the node is defined in dwc3.txt.
15
16PHY documentation is provided in the following places:
17- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
18- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
19
20Example device nodes:
21		usb0: usb@ff500000 {
22			compatible = "amlogic,meson-axg-dwc3";
23			#address-cells = <2>;
24			#size-cells = <2>;
25			ranges;
26
27			clocks = <&clkc CLKID_USB>;
28			clock-names = "usb_general";
29			resets = <&reset RESET_USB_OTG>;
30			reset-names = "usb_otg";
31
32			dwc3: dwc3@ff500000 {
33				compatible = "snps,dwc3";
34				reg = <0x0 0xff500000 0x0 0x100000>;
35				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
36				dr_mode = "host";
37				maximum-speed = "high-speed";
38				snps,dis_u2_susphy_quirk;
39				phys = <&usb3_phy>, <&usb2_phy0>;
40				phy-names = "usb2-phy", "usb3-phy";
41			};
42		};
43
44Amlogic Meson G12A DWC3 USB SoC Controller Glue
45
46The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
47in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
48only.
49
50A glue connects the DWC3 core to USB2 PHYs and optionnaly to an USB3 PHY.
51
52One of the USB2 PHY can be re-routed in peripheral mode to a DWC2 USB IP.
53
54The DWC3 Glue controls the PHY routing and power, an interrupt line is
55connected to the Glue to serve as OTG ID change detection.
56
57Required properties:
58- compatible:	Should be "amlogic,meson-g12a-usb-ctrl"
59- clocks:	a handle for the "USB" clock
60- resets:	a handle for the shared "USB" reset line
61- reg:		The base address and length of the registers
62- interrupts:	the interrupt specifier for the OTG detection
63- phys: 	handle to used PHYs on the system
64	- a <0> phandle can be used if a PHY is not used
65- phy-names:	names of the used PHYs on the system :
66	- "usb2-phy0" for USB2 PHY0 if USBHOST_A port is used
67	- "usb2-phy1" for USB2 PHY1 if USBOTG_B port is used
68	- "usb3-phy0" for USB3 PHY if USB3_0 is used
69- dr_mode:	should be "host", "peripheral", or "otg" depending on
70	the usage and configuration of the OTG Capable port.
71	- "host" and "peripheral" means a fixed Host or Device only connection
72	- "otg" means the port can be used as both Host or Device and
73	  be switched automatically using the OTG ID pin.
74
75Optional properties:
76- vbus-supply:	should be a phandle to the regulator controlling the VBUS
77		power supply when used in OTG switchable mode
78
79Required child nodes:
80
81A child node must exist to represent the core DWC3 IP block. The name of
82the node is not important. The content of the node is defined in dwc3.txt.
83
84A child node must exist to represent the core DWC2 IP block. The name of
85the node is not important. The content of the node is defined in dwc2.txt.
86
87PHY documentation is provided in the following places:
88- Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
89- Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
90
91Example device nodes:
92	usb: usb@ffe09000 {
93			compatible = "amlogic,meson-g12a-usb-ctrl";
94			reg = <0x0 0xffe09000 0x0 0xa0>;
95			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
96			#address-cells = <2>;
97			#size-cells = <2>;
98			ranges;
99
100			clocks = <&clkc CLKID_USB>;
101			resets = <&reset RESET_USB>;
102
103			dr_mode = "otg";
104
105			phys = <&usb2_phy0>, <&usb2_phy1>,
106			       <&usb3_pcie_phy PHY_TYPE_USB3>;
107			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
108
109			dwc2: usb@ff400000 {
110				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
111				reg = <0x0 0xff400000 0x0 0x40000>;
112				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
113				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
114				clock-names = "ddr";
115				phys = <&usb2_phy1>;
116				dr_mode = "peripheral";
117				g-rx-fifo-size = <192>;
118				g-np-tx-fifo-size = <128>;
119				g-tx-fifo-size = <128 128 16 16 16>;
120			};
121
122			dwc3: usb@ff500000 {
123				compatible = "snps,dwc3";
124				reg = <0x0 0xff500000 0x0 0x100000>;
125				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
126				dr_mode = "host";
127				snps,dis_u2_susphy_quirk;
128				snps,quirk-frame-length-adjustment;
129			};
130	};
131