1UniPhier reset controller
2
3
4System reset
5------------
6
7Required properties:
8- compatible: should be one of the following:
9    "socionext,uniphier-ld4-reset"  - for LD4 SoC
10    "socionext,uniphier-pro4-reset" - for Pro4 SoC
11    "socionext,uniphier-sld8-reset" - for sLD8 SoC
12    "socionext,uniphier-pro5-reset" - for Pro5 SoC
13    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14    "socionext,uniphier-ld11-reset" - for LD11 SoC
15    "socionext,uniphier-ld20-reset" - for LD20 SoC
16    "socionext,uniphier-pxs3-reset" - for PXs3 SoC
17- #reset-cells: should be 1.
18
19Example:
20
21	sysctrl@61840000 {
22		compatible = "socionext,uniphier-ld11-sysctrl",
23			     "simple-mfd", "syscon";
24		reg = <0x61840000 0x4000>;
25
26		reset {
27			compatible = "socionext,uniphier-ld11-reset";
28			#reset-cells = <1>;
29		};
30
31		other nodes ...
32	};
33
34
35Media I/O (MIO) reset, SD reset
36-------------------------------
37
38Required properties:
39- compatible: should be one of the following:
40    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC
41    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
42    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
43    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC
44    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC
45    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
46    "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)
47    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC
48    "socionext,uniphier-pxs3-sd-reset"  - for PXs3 SoC
49- #reset-cells: should be 1.
50
51Example:
52
53	mioctrl@59810000 {
54		compatible = "socionext,uniphier-ld11-mioctrl",
55			     "simple-mfd", "syscon";
56		reg = <0x59810000 0x800>;
57
58		reset {
59			compatible = "socionext,uniphier-ld11-mio-reset";
60			#reset-cells = <1>;
61		};
62
63		other nodes ...
64	};
65
66
67Peripheral reset
68----------------
69
70Required properties:
71- compatible: should be one of the following:
72    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC
73    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC
74    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC
75    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC
76    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
77    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
78    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
79    "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
80- #reset-cells: should be 1.
81
82Example:
83
84	perictrl@59820000 {
85		compatible = "socionext,uniphier-ld11-perictrl",
86			     "simple-mfd", "syscon";
87		reg = <0x59820000 0x200>;
88
89		reset {
90			compatible = "socionext,uniphier-ld11-peri-reset";
91			#reset-cells = <1>;
92		};
93
94		other nodes ...
95	};
96
97
98Analog signal amplifier reset
99-----------------------------
100
101Required properties:
102- compatible: should be one of the following:
103    "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
104    "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
105- #reset-cells: should be 1.
106
107Example:
108
109	adamv@57920000 {
110		compatible = "socionext,uniphier-ld11-adamv",
111			     "simple-mfd", "syscon";
112		reg = <0x57920000 0x1000>;
113
114		adamv_rst: reset {
115			compatible = "socionext,uniphier-ld11-adamv-reset";
116			#reset-cells = <1>;
117		};
118
119		other nodes ...
120	};
121
122
123Peripheral core reset in glue layer
124-----------------------------------
125
126Some peripheral core reset belongs to its own glue layer. Before using
127this core reset, it is necessary to control the clocks and resets to enable
128this layer. These clocks and resets should be described in each property.
129
130Required properties:
131- compatible: Should be
132    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
133    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
134    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
135    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
136    "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
137    "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
138    "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
139- #reset-cells: Should be 1.
140- reg: Specifies offset and length of the register set for the device.
141- clocks: A list of phandles to the clock gate for the glue layer.
142	According to the clock-names, appropriate clocks are required.
143- clock-names: Should contain
144    "gio", "link" - for Pro4 SoC
145    "link"        - for others
146- resets: A list of phandles to the reset control for the glue layer.
147	According to the reset-names, appropriate resets are required.
148- reset-names: Should contain
149    "gio", "link" - for Pro4 SoC
150    "link"        - for others
151
152Example:
153
154	usb-glue@65b00000 {
155		compatible = "socionext,uniphier-ld20-dwc3-glue",
156			     "simple-mfd";
157		#address-cells = <1>;
158		#size-cells = <1>;
159		ranges = <0 0x65b00000 0x400>;
160
161		usb_rst: reset@0 {
162			compatible = "socionext,uniphier-ld20-usb3-reset";
163			reg = <0x0 0x4>;
164			#reset-cells = <1>;
165			clock-names = "link";
166			clocks = <&sys_clk 14>;
167			reset-names = "link";
168			resets = <&sys_rst 14>;
169		};
170
171		regulator {
172			...
173		};
174
175		phy {
176			...
177		};
178		...
179	};
180