1NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) 2 3This PCIe host controller is based on the Synopsis Designware PCIe IP 4and thus inherits all the common properties defined in designware-pcie.txt. 5 6Required properties: 7- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie". 8- device_type: Must be "pci" 9- power-domains: A phandle to the node that controls power to the respective 10 PCIe controller and a specifier name for the PCIe controller. Following are 11 the specifiers for the different PCIe controllers 12 TEGRA194_POWER_DOMAIN_PCIEX8B: C0 13 TEGRA194_POWER_DOMAIN_PCIEX1A: C1 14 TEGRA194_POWER_DOMAIN_PCIEX1A: C2 15 TEGRA194_POWER_DOMAIN_PCIEX1A: C3 16 TEGRA194_POWER_DOMAIN_PCIEX4A: C4 17 TEGRA194_POWER_DOMAIN_PCIEX8A: C5 18 these specifiers are defined in 19 "include/dt-bindings/power/tegra194-powergate.h" file. 20- reg: A list of physical base address and length pairs for each set of 21 controller registers. Must contain an entry for each entry in the reg-names 22 property. 23- reg-names: Must include the following entries: 24 "appl": Controller's application logic registers 25 "config": As per the definition in designware-pcie.txt 26 "atu_dma": iATU and DMA registers. This is where the iATU (internal Address 27 Translation Unit) registers of the PCIe core are made available 28 for SW access. 29 "dbi": The aperture where root port's own configuration registers are 30 available 31- interrupts: A list of interrupt outputs of the controller. Must contain an 32 entry for each entry in the interrupt-names property. 33- interrupt-names: Must include the following entries: 34 "intr": The Tegra interrupt that is asserted for controller interrupts 35 "msi": The Tegra interrupt that is asserted when an MSI is received 36- bus-range: Range of bus numbers associated with this controller 37- #address-cells: Address representation for root ports (must be 3) 38 - cell 0 specifies the bus and device numbers of the root port: 39 [23:16]: bus number 40 [15:11]: device number 41 - cell 1 denotes the upper 32 address bits and should be 0 42 - cell 2 contains the lower 32 address bits and is used to translate to the 43 CPU address space 44- #size-cells: Size representation for root ports (must be 2) 45- ranges: Describes the translation of addresses for root ports and standard 46 PCI regions. The entries must be 7 cells each, where the first three cells 47 correspond to the address as described for the #address-cells property 48 above, the fourth and fifth cells are for the physical CPU address to 49 translate to and the sixth and seventh cells are as described for the 50 #size-cells property above. 51 - Entries setup the mapping for the standard I/O, memory and 52 prefetchable PCI regions. The first cell determines the type of region 53 that is setup: 54 - 0x81000000: I/O memory region 55 - 0x82000000: non-prefetchable memory region 56 - 0xc2000000: prefetchable memory region 57 Please refer to the standard PCI bus binding document for a more detailed 58 explanation. 59- #interrupt-cells: Size representation for interrupts (must be 1) 60- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 61 Please refer to the standard PCI bus binding document for a more detailed 62 explanation. 63- clocks: Must contain an entry for each entry in clock-names. 64 See ../clocks/clock-bindings.txt for details. 65- clock-names: Must include the following entries: 66 - core 67- resets: Must contain an entry for each entry in reset-names. 68 See ../reset/reset.txt for details. 69- reset-names: Must include the following entries: 70 - apb 71 - core 72- phys: Must contain a phandle to P2U PHY for each entry in phy-names. 73- phy-names: Must include an entry for each active lane. 74 "p2u-N": where N ranges from 0 to one less than the total number of lanes 75- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed 76 by controller-id. Following are the controller ids for each controller. 77 0: C0 78 1: C1 79 2: C2 80 3: C3 81 4: C4 82 5: C5 83- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals 84 85Optional properties: 86- pinctrl-names: A list of pinctrl state names. 87 It is mandatory for C5 controller and optional for other controllers. 88 - "default": Configures PCIe I/O for proper operation. 89- pinctrl-0: phandle for the 'default' state of pin configuration. 90 It is mandatory for C5 controller and optional for other controllers. 91- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt 92- nvidia,update-fc-fixup: This is a boolean property and needs to be present to 93 improve performance when a platform is designed in such a way that it 94 satisfies at least one of the following conditions thereby enabling root 95 port to exchange optimum number of FC (Flow Control) credits with 96 downstream devices 97 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 98 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 99 a) speed is Gen-2 and MPS is 256B 100 b) speed is >= Gen-3 with any MPS 101- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM 102 to be specified in microseconds 103- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be 104 specified in microseconds 105- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be 106 specified in microseconds 107- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot 108 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 109 in p2972-0000 platform). 110- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot 111 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 112 in p2972-0000 platform). 113 114Examples: 115========= 116 117Tegra194: 118-------- 119 120 pcie@14180000 { 121 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 122 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 123 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 124 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 125 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */ 126 reg-names = "appl", "config", "atu_dma"; 127 128 #address-cells = <3>; 129 #size-cells = <2>; 130 device_type = "pci"; 131 num-lanes = <8>; 132 linux,pci-domain = <0>; 133 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 136 137 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 138 clock-names = "core"; 139 140 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 141 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 142 reset-names = "apb", "core"; 143 144 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 145 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 146 interrupt-names = "intr", "msi"; 147 148 #interrupt-cells = <1>; 149 interrupt-map-mask = <0 0 0 0>; 150 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 151 152 nvidia,bpmp = <&bpmp 0>; 153 154 supports-clkreq; 155 nvidia,aspm-cmrt-us = <60>; 156 nvidia,aspm-pwr-on-t-us = <20>; 157 nvidia,aspm-l0s-entrance-latency-us = <3>; 158 159 bus-range = <0x0 0xff>; 160 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 161 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */ 162 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ 163 164 vddio-pex-ctl-supply = <&vdd_1v8ao>; 165 vpcie3v3-supply = <&vdd_3v3_pcie>; 166 vpcie12v-supply = <&vdd_12v_pcie>; 167 168 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 169 <&p2u_hsio_5>; 170 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 171 }; 172
