1Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
2
3This binding represents the on-chip eFuse OTP controller found on
4i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
5i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM and i.MX8MN SoCs.
6
7Required properties:
8- compatible: should be one of
9	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
10	"fsl,imx6sl-ocotp" (i.MX6SL), or
11	"fsl,imx6sx-ocotp" (i.MX6SX),
12	"fsl,imx6ul-ocotp" (i.MX6UL),
13	"fsl,imx6ull-ocotp" (i.MX6ULL/ULZ),
14	"fsl,imx7d-ocotp" (i.MX7D/S),
15	"fsl,imx6sll-ocotp" (i.MX6SLL),
16	"fsl,imx7ulp-ocotp" (i.MX7ULP),
17	"fsl,imx8mq-ocotp" (i.MX8MQ),
18	"fsl,imx8mm-ocotp" (i.MX8MM),
19	"fsl,imx8mn-ocotp" (i.MX8MN),
20	followed by "syscon".
21- #address-cells : Should be 1
22- #size-cells : Should be 1
23- reg: Should contain the register base and length.
24- clocks: Should contain a phandle pointing to the gated peripheral clock.
25
26Optional properties:
27- read-only: disable write access
28
29Optional Child nodes:
30
31- Data cells of ocotp:
32  Detailed bindings are described in bindings/nvmem/nvmem.txt
33
34Example:
35	ocotp: ocotp@21bc000 {
36		#address-cells = <1>;
37		#size-cells = <1>;
38		compatible = "fsl,imx6sx-ocotp", "syscon";
39		reg = <0x021bc000 0x4000>;
40		clocks = <&clks IMX6SX_CLK_OCOTP>;
41
42		tempmon_calib: calib@38 {
43			reg = <0x38 4>;
44		};
45
46		tempmon_temp_grade: temp-grade@20 {
47			reg = <0x20 4>;
48		};
49	};
50