1* Renesas Electronics Ethernet AVB
2
3This file provides information on what the device node for the Ethernet AVB
4interface contains.
5
6Required properties:
7- compatible: Must contain one or more of the following:
8      - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
9      - "renesas,etheravb-r8a7744" for the R8A7744 SoC.
10      - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
11      - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
12      - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
13      - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
14      - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
15      - "renesas,etheravb-r8a7793" for the R8A7793 SoC.
16      - "renesas,etheravb-r8a7794" for the R8A7794 SoC.
17      - "renesas,etheravb-rcar-gen2" as a fallback for the above
18		R-Car Gen2 and RZ/G1 devices.
19
20      - "renesas,etheravb-r8a774a1" for the R8A774A1 SoC.
21      - "renesas,etheravb-r8a774b1" for the R8A774B1 SoC.
22      - "renesas,etheravb-r8a774c0" for the R8A774C0 SoC.
23      - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
24      - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
25      - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
26      - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
27      - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
28      - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
29      - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
30      - "renesas,etheravb-rcar-gen3" as a fallback for the above
31		R-Car Gen3 and RZ/G2 devices.
32
33	When compatible with the generic version, nodes must list the
34	SoC-specific version corresponding to the platform first followed by
35	the generic version.
36
37- reg: Offset and length of (1) the register block and (2) the stream buffer.
38       The region for the register block is mandatory.
39       The region for the stream buffer is optional, as it is only present on
40       R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796),
41       and M3-N (R8A77965).
42- interrupts: A list of interrupt-specifiers, one for each entry in
43	      interrupt-names.
44	      If interrupt-names is not present, an interrupt specifier
45	      for a single muxed interrupt.
46- phy-mode: see ethernet.txt file in the same directory.
47- phy-handle: see ethernet.txt file in the same directory.
48- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
49- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
50- clocks: clock phandle and specifier pair.
51- pinctrl-0: phandle, referring to a default pin configuration node.
52
53Optional properties:
54- interrupt-names: A list of interrupt names.
55		   For the R-Car Gen 3 SoCs this property is mandatory;
56		   it should include one entry per channel, named "ch%u",
57		   where %u is the channel number ranging from 0 to 24.
58		   For other SoCs this property is optional; if present
59		   it should contain "mux" for a single muxed interrupt.
60- pinctrl-names: pin configuration state name ("default").
61- renesas,no-ether-link: boolean, specify when a board does not provide a proper
62			 AVB_LINK signal.
63- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
64				 active-low instead of normal active-high.
65
66Example:
67
68	ethernet@e6800000 {
69		compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3";
70		reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
71		interrupt-parent = <&gic>;
72		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
73			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
74			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
75			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
76			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
77			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
78			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
79			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
80			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
81			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
86			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
87			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
88			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
89			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
90			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
91			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
92			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
93			     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
94			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
95			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
96			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
97		interrupt-names = "ch0", "ch1", "ch2", "ch3",
98				  "ch4", "ch5", "ch6", "ch7",
99				  "ch8", "ch9", "ch10", "ch11",
100				  "ch12", "ch13", "ch14", "ch15",
101				  "ch16", "ch17", "ch18", "ch19",
102				  "ch20", "ch21", "ch22", "ch23",
103				  "ch24";
104		clocks = <&cpg CPG_MOD 812>;
105		power-domains = <&cpg>;
106		phy-mode = "rgmii-id";
107		phy-handle = <&phy0>;
108
109		pinctrl-0 = <&ether_pins>;
110		pinctrl-names = "default";
111		renesas,no-ether-link;
112		#address-cells = <1>;
113		#size-cells = <0>;
114
115		phy0: ethernet-phy@0 {
116			rxc-skew-ps = <900>;
117			rxdv-skew-ps = <0>;
118			rxd0-skew-ps = <0>;
119			rxd1-skew-ps = <0>;
120			rxd2-skew-ps = <0>;
121			rxd3-skew-ps = <0>;
122			txc-skew-ps = <900>;
123			txen-skew-ps = <0>;
124			txd0-skew-ps = <0>;
125			txd1-skew-ps = <0>;
126			txd2-skew-ps = <0>;
127			txd3-skew-ps = <0>;
128			reg = <0>;
129			interrupt-parent = <&gpio2>;
130			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
131		};
132	};
133