1MediaTek DWMAC glue layer controller
2
3This file documents platform glue layer for stmmac.
4Please see stmmac.txt for the other unchanged properties.
5
6The device node has following properties.
7
8Required properties:
9- compatible:  Should be "mediatek,mt2712-gmac" for MT2712 SoC
10- reg:  Address and length of the register set for the device
11- interrupts:  Should contain the MAC interrupts
12- interrupt-names: Should contain a list of interrupt names corresponding to
13	the interrupts in the interrupts property, if available.
14	Should be "macirq" for the main MAC IRQ
15- clocks: Must contain a phandle for each entry in clock-names.
16- clock-names: The name of the clock listed in the clocks property. These are
17	"axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC
18- mac-address: See ethernet.txt in the same directory
19- phy-mode: See ethernet.txt in the same directory
20- mediatek,pericfg: A phandle to the syscon node that control ethernet
21	interface and timing delay.
22
23Optional properties:
24- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
25	It should be defined for RGMII/MII interface.
26- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
27	It should be defined for RGMII/MII/RMII interface.
28Both delay properties need to be a multiple of 170 for RGMII interface,
29or will round down. Range 0~31*170.
30Both delay properties need to be a multiple of 550 for MII/RMII interface,
31or will round down. Range 0~31*550.
32
33- mediatek,rmii-rxc: boolean property, if present indicates that the RMII
34	reference clock, which is from external PHYs, is connected to RXC pin
35	on MT2712 SoC.
36	Otherwise, is connected to TXC pin.
37- mediatek,txc-inverse: boolean property, if present indicates that
38	1. tx clock will be inversed in MII/RGMII case,
39	2. tx clock inside MAC will be inversed relative to reference clock
40	   which is from external PHYs in RMII case, and it rarely happen.
41- mediatek,rxc-inverse: boolean property, if present indicates that
42	1. rx clock will be inversed in MII/RGMII case.
43	2. reference clock will be inversed when arrived at MAC in RMII case.
44- assigned-clocks: mac_main and ptp_ref clocks
45- assigned-clock-parents: parent clocks of the assigned clocks
46
47Example:
48	eth: ethernet@1101c000 {
49		compatible = "mediatek,mt2712-gmac";
50		reg = <0 0x1101c000 0 0x1300>;
51		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
52		interrupt-names = "macirq";
53		phy-mode ="rgmii";
54		mac-address = [00 55 7b b5 7d f7];
55		clock-names = "axi",
56			      "apb",
57			      "mac_main",
58			      "ptp_ref",
59			      "ptp_top";
60		clocks = <&pericfg CLK_PERI_GMAC>,
61			 <&pericfg CLK_PERI_GMAC_PCLK>,
62			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
63			 <&topckgen CLK_TOP_ETHER_50M_SEL>;
64		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
65				  <&topckgen CLK_TOP_ETHER_50M_SEL>;
66		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
67					 <&topckgen CLK_TOP_APLL1_D3>;
68		mediatek,pericfg = <&pericfg>;
69		mediatek,tx-delay-ps = <1530>;
70		mediatek,rx-delay-ps = <1530>;
71		mediatek,rmii-rxc;
72		mediatek,txc-inverse;
73		mediatek,rxc-inverse;
74		snps,txpbl = <32>;
75		snps,rxpbl = <32>;
76		snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
77		snps,reset-active-low;
78	};
79