1NXP i.MX Messaging Unit (MU)
2--------------------------------------------------------------------
3
4The Messaging Unit module enables two processors within the SoC to
5communicate and coordinate by passing messages (e.g. data, status
6and control) through the MU interface. The MU also provides the ability
7for one processor to signal the other processor using interrupts.
8
9Because the MU manages the messaging between processors, the MU uses
10different clocks (from each side of the different peripheral buses).
11Therefore, the MU must synchronize the accesses from one side to the
12other. The MU accomplishes synchronization using two sets of matching
13registers (Processor A-facing, Processor B-facing).
14
15Messaging Unit Device Node:
16=============================
17
18Required properties:
19-------------------
20- compatible :	should be "fsl,<chip>-mu", the supported chips include
21		imx6sx, imx7s, imx8qxp, imx8qm.
22		The "fsl,imx6sx-mu" compatible is seen as generic and should
23		be included together with SoC specific compatible.
24- reg :		Should contain the registers location and length
25- interrupts :	Interrupt number. The interrupt specifier format depends
26		on the interrupt controller parent.
27- #mbox-cells:  Must be 2.
28			  <&phandle type channel>
29			    phandle   : Label name of controller
30			    type      : Channel type
31			    channel   : Channel number
32
33		This MU support 4 type of unidirectional channels, each type
34		has 4 channels. A total of 16 channels. Following types are
35		supported:
36		0 - TX channel with 32bit transmit register and IRQ transmit
37		acknowledgment support.
38		1 - RX channel with 32bit receive register and IRQ support
39		2 - TX doorbell channel. Without own register and no ACK support.
40		3 - RX doorbell channel.
41
42Optional properties:
43-------------------
44- clocks :	phandle to the input clock.
45- fsl,mu-side-b : Should be set for side B MU.
46
47Examples:
48--------
49lsio_mu0: mailbox@5d1b0000 {
50	compatible = "fsl,imx8qxp-mu";
51	reg = <0x0 0x5d1b0000 0x0 0x10000>;
52	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
53	#mbox-cells = <2>;
54};
55