1STM32 DMA MUX (DMA request router) 2 3Required properties: 4- compatible: "st,stm32h7-dmamux" 5- reg: Memory map for accessing module 6- #dma-cells: Should be set to <3>. 7 First parameter is request line number. 8 Second is DMA channel configuration 9 Third is Fifo threshold 10 For more details about the three cells, please see 11 stm32-dma.txt documentation binding file 12- dma-masters: Phandle pointing to the DMA controllers. 13 Several controllers are allowed. Only "st,stm32-dma" DMA 14 compatible are supported. 15 16Optional properties: 17- dma-channels : Number of DMA requests supported. 18- dma-requests : Number of DMAMUX requests supported. 19- resets: Reference to a reset controller asserting the DMA controller 20- clocks: Input clock of the DMAMUX instance. 21 22Example: 23 24/* DMA controller 1 */ 25dma1: dma-controller@40020000 { 26 compatible = "st,stm32-dma"; 27 reg = <0x40020000 0x400>; 28 interrupts = <11>, 29 <12>, 30 <13>, 31 <14>, 32 <15>, 33 <16>, 34 <17>, 35 <47>; 36 clocks = <&timer_clk>; 37 #dma-cells = <4>; 38 st,mem2mem; 39 resets = <&rcc 150>; 40 dma-channels = <8>; 41 dma-requests = <8>; 42}; 43 44/* DMA controller 1 */ 45dma2: dma@40020400 { 46 compatible = "st,stm32-dma"; 47 reg = <0x40020400 0x400>; 48 interrupts = <56>, 49 <57>, 50 <58>, 51 <59>, 52 <60>, 53 <68>, 54 <69>, 55 <70>; 56 clocks = <&timer_clk>; 57 #dma-cells = <4>; 58 st,mem2mem; 59 resets = <&rcc 150>; 60 dma-channels = <8>; 61 dma-requests = <8>; 62}; 63 64/* DMA mux */ 65dmamux1: dma-router@40020800 { 66 compatible = "st,stm32h7-dmamux"; 67 reg = <0x40020800 0x3c>; 68 #dma-cells = <3>; 69 dma-requests = <128>; 70 dma-channels = <16>; 71 dma-masters = <&dma1 &dma2>; 72 clocks = <&timer_clk>; 73}; 74 75/* DMA client */ 76usart1: serial@40011000 { 77 compatible = "st,stm32-usart", "st,stm32-uart"; 78 reg = <0x40011000 0x400>; 79 interrupts = <37>; 80 clocks = <&timer_clk>; 81 dmas = <&dmamux1 41 0x414 0>, 82 <&dmamux1 42 0x414 0>; 83 dma-names = "rx", "tx"; 84}; 85