1* Synopsys Designware DMA Controller
2
3Required properties:
4- compatible: "snps,dma-spear1340"
5- reg: Address range of the DMAC registers
6- interrupt: Should contain the DMAC interrupt number
7- dma-channels: Number of channels supported by hardware
8- dma-requests: Number of DMA request lines supported, up to 16
9- dma-masters: Number of AHB masters supported by the controller
10- #dma-cells: must be <3>
11- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
12  1: descending
13- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14  increase from chan n->0
15- block_size: Maximum block size supported by the controller
16- data-width: Maximum data width supported by hardware per AHB master
17  (in bytes, power of 2)
18
19
20Deprecated properties:
21- data_width: Maximum data width supported by hardware per AHB master
22  (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
23
24
25Optional properties:
26- multi-block: Multi block transfers supported by hardware. Array property with
27  one cell per channel. 0: not supported, 1 (default): supported.
28- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
29  The default value is 0 (for non-cacheable, non-buffered,
30  unprivileged data access).
31  Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
32
33Example:
34
35	dmahost: dma@fc000000 {
36		compatible = "snps,dma-spear1340";
37		reg = <0xfc000000 0x1000>;
38		interrupt-parent = <&vic1>;
39		interrupts = <12>;
40
41		dma-channels = <8>;
42		dma-requests = <16>;
43		dma-masters = <2>;
44		#dma-cells = <3>;
45		chan_allocation_order = <1>;
46		chan_priority = <1>;
47		block_size = <0xfff>;
48		data-width = <8 8>;
49	};
50
51DMA clients connected to the Designware DMA controller must use the format
52described in the dma.txt file, using a four-cell specifier for each channel.
53The four cells in order are:
54
551. A phandle pointing to the DMA controller
562. The DMA request line number
573. Memory master for transfers on allocated channel
584. Peripheral master for transfers on allocated channel
59
60Example:
61
62	serial@e0000000 {
63		compatible = "arm,pl011", "arm,primecell";
64		reg = <0xe0000000 0x1000>;
65		interrupts = <0 35 0x4>;
66		dmas = <&dmahost 12 0 1>,
67			<&dmahost 13 1 0>;
68		dma-names = "rx", "rx";
69	};
70