1Allwinner A10 Display Pipeline 2============================== 3 4The Allwinner A10 Display pipeline is composed of several components 5that are going to be documented below: 6 7For all connections between components up to the TCONs in the display 8pipeline, when there are multiple components of the same type at the 9same depth, the local endpoint ID must be the same as the remote 10component's index. For example, if the remote endpoint is Frontend 1, 11then the local endpoint ID must be 1. 12 13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 14 [1] -- -- [1] [1] -- -- [1] 15 \ / \ / 16 X X 17 / \ / \ 18 [0] -- -- [0] [0] -- -- [0] 19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 20 21For a two pipeline system such as the one depicted above, the lines 22represent the connections between the components, while the numbers 23within the square brackets corresponds to the ID of the local endpoint. 24 25The same rule also applies to DE 2.0 mixer-TCON connections: 26 27 Mixer 0 [0] ----------- [0] TCON 0 28 [1] ---- ---- [1] 29 \ / 30 X 31 / \ 32 [0] ---- ---- [0] 33 Mixer 1 [1] ----------- [1] TCON 1 34 35HDMI Encoder 36------------ 37 38The HDMI Encoder supports the HDMI video and audio outputs, and does 39CEC. It is one end of the pipeline. 40 41Required properties: 42 - compatible: value must be one of: 43 * allwinner,sun4i-a10-hdmi 44 * allwinner,sun5i-a10s-hdmi 45 * allwinner,sun6i-a31-hdmi 46 - reg: base address and size of memory-mapped region 47 - interrupts: interrupt associated to this IP 48 - clocks: phandles to the clocks feeding the HDMI encoder 49 * ahb: the HDMI interface clock 50 * mod: the HDMI module clock 51 * ddc: the HDMI ddc clock (A31 only) 52 * pll-0: the first video PLL 53 * pll-1: the second video PLL 54 - clock-names: the clock names mentioned above 55 - resets: phandle to the reset control for the HDMI encoder (A31 only) 56 - dmas: phandles to the DMA channels used by the HDMI encoder 57 * ddc-tx: The channel for DDC transmission 58 * ddc-rx: The channel for DDC reception 59 * audio-tx: The channel used for audio transmission 60 - dma-names: the channel names mentioned above 61 62 - ports: A ports node with endpoint definitions as defined in 63 Documentation/devicetree/bindings/media/video-interfaces.txt. The 64 first port should be the input endpoint. The second should be the 65 output, usually to an HDMI connector. 66 67DWC HDMI TX Encoder 68------------------- 69 70The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP 71with Allwinner's own PHY IP. It supports audio and video outputs and CEC. 72 73These DT bindings follow the Synopsys DWC HDMI TX bindings defined in 74Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the 75following device-specific properties. 76 77Required properties: 78 79 - compatible: value must be one of: 80 * "allwinner,sun8i-a83t-dw-hdmi" 81 * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi" 82 * "allwinner,sun50i-h6-dw-hdmi" 83 - reg: base address and size of memory-mapped region 84 - reg-io-width: See dw_hdmi.txt. Shall be 1. 85 - interrupts: HDMI interrupt number 86 - clocks: phandles to the clocks feeding the HDMI encoder 87 * iahb: the HDMI bus clock 88 * isfr: the HDMI register clock 89 * tmds: TMDS clock 90 * cec: HDMI CEC clock (H6 only) 91 * hdcp: HDCP clock (H6 only) 92 * hdcp-bus: HDCP bus clock (H6 only) 93 - clock-names: the clock names mentioned above 94 - resets: 95 * ctrl: HDMI controller reset 96 * hdcp: HDCP reset (H6 only) 97 - reset-names: reset names mentioned above 98 - phys: phandle to the DWC HDMI PHY 99 - phy-names: must be "phy" 100 101 - ports: A ports node with endpoint definitions as defined in 102 Documentation/devicetree/bindings/media/video-interfaces.txt. The 103 first port should be the input endpoint. The second should be the 104 output, usually to an HDMI connector. 105 106Optional properties: 107 - hvcc-supply: the VCC power supply of the controller 108 109DWC HDMI PHY 110------------ 111 112Required properties: 113 - compatible: value must be one of: 114 * allwinner,sun8i-a83t-hdmi-phy 115 * allwinner,sun8i-h3-hdmi-phy 116 * allwinner,sun8i-r40-hdmi-phy 117 * allwinner,sun50i-a64-hdmi-phy 118 * allwinner,sun50i-h6-hdmi-phy 119 - reg: base address and size of memory-mapped region 120 - clocks: phandles to the clocks feeding the HDMI PHY 121 * bus: the HDMI PHY interface clock 122 * mod: the HDMI PHY module clock 123 - clock-names: the clock names mentioned above 124 - resets: phandle to the reset controller driving the PHY 125 - reset-names: must be "phy" 126 127H3, A64 and R40 HDMI PHY require additional clocks: 128 - pll-0: parent of phy clock 129 - pll-1: second possible phy clock parent (A64/R40 only) 130 131TV Encoder 132---------- 133 134The TV Encoder supports the composite and VGA output. It is one end of 135the pipeline. 136 137Required properties: 138 - compatible: value should be "allwinner,sun4i-a10-tv-encoder". 139 - reg: base address and size of memory-mapped region 140 - clocks: the clocks driving the TV encoder 141 - resets: phandle to the reset controller driving the encoder 142 143- ports: A ports node with endpoint definitions as defined in 144 Documentation/devicetree/bindings/media/video-interfaces.txt. The 145 first port should be the input endpoint. 146 147TCON 148---- 149 150The TCON acts as a timing controller for RGB, LVDS and TV interfaces. 151 152Required properties: 153 - compatible: value must be either: 154 * allwinner,sun4i-a10-tcon 155 * allwinner,sun5i-a13-tcon 156 * allwinner,sun6i-a31-tcon 157 * allwinner,sun6i-a31s-tcon 158 * allwinner,sun7i-a20-tcon 159 * allwinner,sun8i-a23-tcon 160 * allwinner,sun8i-a33-tcon 161 * allwinner,sun8i-a83t-tcon-lcd 162 * allwinner,sun8i-a83t-tcon-tv 163 * allwinner,sun8i-r40-tcon-tv 164 * allwinner,sun8i-v3s-tcon 165 * allwinner,sun9i-a80-tcon-lcd 166 * allwinner,sun9i-a80-tcon-tv 167 * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd" 168 * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv" 169 * allwinner,sun50i-h6-tcon-tv, allwinner,sun8i-r40-tcon-tv 170 - reg: base address and size of memory-mapped region 171 - interrupts: interrupt associated to this IP 172 - clocks: phandles to the clocks feeding the TCON. 173 - 'ahb': the interface clocks 174 - 'tcon-ch0': The clock driving the TCON channel 0, if supported 175 - resets: phandles to the reset controllers driving the encoder 176 - "lcd": the reset line for the TCON 177 - "edp": the reset line for the eDP block (A80 only) 178 179 - clock-names: the clock names mentioned above 180 - reset-names: the reset names mentioned above 181 - clock-output-names: Name of the pixel clock created, if TCON supports 182 channel 0. 183 184- ports: A ports node with endpoint definitions as defined in 185 Documentation/devicetree/bindings/media/video-interfaces.txt. The 186 first port should be the input endpoint, the second one the output 187 188 The output may have multiple endpoints. TCON can have 1 or 2 channels, 189 usually with the first channel being used for the panels interfaces 190 (RGB, LVDS, etc.), and the second being used for the outputs that 191 require another controller (TV Encoder, HDMI, etc.). The endpoints 192 will take an extra property, allwinner,tcon-channel, to specify the 193 channel the endpoint is associated to. If that property is not 194 present, the endpoint number will be used as the channel number. 195 196For TCONs with channel 0, there is one more clock required: 197 - 'tcon-ch0': The clock driving the TCON channel 0 198For TCONs with channel 1, there is one more clock required: 199 - 'tcon-ch1': The clock driving the TCON channel 1 200 201When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found 202in A13, H3, H5 and V3s SoCs), you need one more reset line: 203 - 'lvds': The reset line driving the LVDS logic 204 205And on the A23, A31, A31s and A33, you need one more clock line: 206 - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 207 clock, that can be used to drive the LVDS clock 208 209TCON TOP 210-------- 211 212TCON TOPs main purpose is to configure whole display pipeline. It determines 213relationships between mixers and TCONs, selects source TCON for HDMI, muxes 214LCD and TV encoder GPIO output, selects TV encoder clock source and contains 215additional TV TCON and DSI gates. 216 217It allows display pipeline to be configured in very different ways: 218 219 / LCD0/LVDS0 220 / [0] TCON-LCD0 221 | \ MIPI DSI 222 mixer0 | 223 \ / [1] TCON-LCD1 - LCD1/LVDS1 224 TCON-TOP 225 / \ [2] TCON-TV0 [0] - TVE0/RGB 226 mixer1 | \ 227 | TCON-TOP - HDMI 228 | / 229 \ [3] TCON-TV1 [1] - TVE1/RGB 230 231Note that both TCON TOP references same physical unit. Both mixers can be 232connected to any TCON. Not all TCON TOP variants support all features. 233 234Required properties: 235 - compatible: value must be one of: 236 * allwinner,sun8i-r40-tcon-top 237 * allwinner,sun50i-h6-tcon-top 238 - reg: base address and size of the memory-mapped region. 239 - clocks: phandle to the clocks feeding the TCON TOP 240 * bus: TCON TOP interface clock 241 * tcon-tv0: TCON TV0 clock 242 * tve0: TVE0 clock (R40 only) 243 * tcon-tv1: TCON TV1 clock (R40 only) 244 * tve1: TVE0 clock (R40 only) 245 * dsi: MIPI DSI clock (R40 only) 246 - clock-names: clock name mentioned above 247 - resets: phandle to the reset line driving the TCON TOP 248 - #clock-cells : must contain 1 249 - clock-output-names: Names of clocks created for TCON TV0 channel clock, 250 TCON TV1 channel clock (R40 only) and DSI channel clock (R40 only), in 251 that order. 252 253- ports: A ports node with endpoint definitions as defined in 254 Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should 255 be defined: 256 * port 0 is input for mixer0 mux 257 * port 1 is output for mixer0 mux 258 * port 2 is input for mixer1 mux 259 * port 3 is output for mixer1 mux 260 * port 4 is input for HDMI mux 261 * port 5 is output for HDMI mux 262 All output endpoints for mixer muxes and input endpoints for HDMI mux should 263 have reg property with the id of the target TCON, as shown in above graph 264 (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one 265 endpoint connected to remote endpoint. 266 267DRC 268--- 269 270The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs 271(A31, A23, A33, A80), allows to dynamically adjust pixel 272brightness/contrast based on histogram measurements for LCD content 273adaptive backlight control. 274 275 276Required properties: 277 - compatible: value must be one of: 278 * allwinner,sun6i-a31-drc 279 * allwinner,sun6i-a31s-drc 280 * allwinner,sun8i-a23-drc 281 * allwinner,sun8i-a33-drc 282 * allwinner,sun9i-a80-drc 283 - reg: base address and size of the memory-mapped region. 284 - interrupts: interrupt associated to this IP 285 - clocks: phandles to the clocks feeding the DRC 286 * ahb: the DRC interface clock 287 * mod: the DRC module clock 288 * ram: the DRC DRAM clock 289 - clock-names: the clock names mentioned above 290 - resets: phandles to the reset line driving the DRC 291 292- ports: A ports node with endpoint definitions as defined in 293 Documentation/devicetree/bindings/media/video-interfaces.txt. The 294 first port should be the input endpoints, the second one the outputs 295 296Display Engine Backend 297---------------------- 298 299The display engine backend exposes layers and sprites to the 300system. 301 302Required properties: 303 - compatible: value must be one of: 304 * allwinner,sun4i-a10-display-backend 305 * allwinner,sun5i-a13-display-backend 306 * allwinner,sun6i-a31-display-backend 307 * allwinner,sun7i-a20-display-backend 308 * allwinner,sun8i-a23-display-backend 309 * allwinner,sun8i-a33-display-backend 310 * allwinner,sun9i-a80-display-backend 311 - reg: base address and size of the memory-mapped region. 312 - interrupts: interrupt associated to this IP 313 - clocks: phandles to the clocks feeding the frontend and backend 314 * ahb: the backend interface clock 315 * mod: the backend module clock 316 * ram: the backend DRAM clock 317 - clock-names: the clock names mentioned above 318 - resets: phandles to the reset controllers driving the backend 319 320- ports: A ports node with endpoint definitions as defined in 321 Documentation/devicetree/bindings/media/video-interfaces.txt. The 322 first port should be the input endpoints, the second one the output 323 324On the A33, some additional properties are required: 325 - reg needs to have an additional region corresponding to the SAT 326 - reg-names need to be set, with "be" and "sat" 327 - clocks and clock-names need to have a phandle to the SAT bus 328 clocks, whose name will be "sat" 329 - resets and reset-names need to have a phandle to the SAT bus 330 resets, whose name will be "sat" 331 332DEU 333--- 334 335The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, 336can sharpen the display content in both luma and chroma channels. 337 338Required properties: 339 - compatible: value must be one of: 340 * allwinner,sun9i-a80-deu 341 - reg: base address and size of the memory-mapped region. 342 - interrupts: interrupt associated to this IP 343 - clocks: phandles to the clocks feeding the DEU 344 * ahb: the DEU interface clock 345 * mod: the DEU module clock 346 * ram: the DEU DRAM clock 347 - clock-names: the clock names mentioned above 348 - resets: phandles to the reset line driving the DEU 349 350- ports: A ports node with endpoint definitions as defined in 351 Documentation/devicetree/bindings/media/video-interfaces.txt. The 352 first port should be the input endpoints, the second one the outputs 353 354Display Engine Frontend 355----------------------- 356 357The display engine frontend does formats conversion, scaling, 358deinterlacing and color space conversion. 359 360Required properties: 361 - compatible: value must be one of: 362 * allwinner,sun4i-a10-display-frontend 363 * allwinner,sun5i-a13-display-frontend 364 * allwinner,sun6i-a31-display-frontend 365 * allwinner,sun7i-a20-display-frontend 366 * allwinner,sun8i-a23-display-frontend 367 * allwinner,sun8i-a33-display-frontend 368 * allwinner,sun9i-a80-display-frontend 369 - reg: base address and size of the memory-mapped region. 370 - interrupts: interrupt associated to this IP 371 - clocks: phandles to the clocks feeding the frontend and backend 372 * ahb: the backend interface clock 373 * mod: the backend module clock 374 * ram: the backend DRAM clock 375 - clock-names: the clock names mentioned above 376 - resets: phandles to the reset controllers driving the backend 377 378- ports: A ports node with endpoint definitions as defined in 379 Documentation/devicetree/bindings/media/video-interfaces.txt. The 380 first port should be the input endpoints, the second one the outputs 381 382Display Engine 2.0 Mixer 383------------------------ 384 385The DE2 mixer have many functionalities, currently only layer blending is 386supported. 387 388Required properties: 389 - compatible: value must be one of: 390 * allwinner,sun8i-a83t-de2-mixer-0 391 * allwinner,sun8i-a83t-de2-mixer-1 392 * allwinner,sun8i-h3-de2-mixer-0 393 * allwinner,sun8i-r40-de2-mixer-0 394 * allwinner,sun8i-r40-de2-mixer-1 395 * allwinner,sun8i-v3s-de2-mixer 396 * allwinner,sun50i-a64-de2-mixer-0 397 * allwinner,sun50i-a64-de2-mixer-1 398 * allwinner,sun50i-h6-de3-mixer-0 399 - reg: base address and size of the memory-mapped region. 400 - clocks: phandles to the clocks feeding the mixer 401 * bus: the mixer interface clock 402 * mod: the mixer module clock 403 - clock-names: the clock names mentioned above 404 - resets: phandles to the reset controllers driving the mixer 405 406- ports: A ports node with endpoint definitions as defined in 407 Documentation/devicetree/bindings/media/video-interfaces.txt. The 408 first port should be the input endpoints, the second one the output 409 410 411Display Engine Pipeline 412----------------------- 413 414The display engine pipeline (and its entry point, since it can be 415either directly the backend or the frontend) is represented as an 416extra node. 417 418Required properties: 419 - compatible: value must be one of: 420 * allwinner,sun4i-a10-display-engine 421 * allwinner,sun5i-a10s-display-engine 422 * allwinner,sun5i-a13-display-engine 423 * allwinner,sun6i-a31-display-engine 424 * allwinner,sun6i-a31s-display-engine 425 * allwinner,sun7i-a20-display-engine 426 * allwinner,sun8i-a23-display-engine 427 * allwinner,sun8i-a33-display-engine 428 * allwinner,sun8i-a83t-display-engine 429 * allwinner,sun8i-h3-display-engine 430 * allwinner,sun8i-r40-display-engine 431 * allwinner,sun8i-v3s-display-engine 432 * allwinner,sun9i-a80-display-engine 433 * allwinner,sun50i-a64-display-engine 434 * allwinner,sun50i-h6-display-engine 435 436 - allwinner,pipelines: list of phandle to the display engine 437 frontends (DE 1.0) or mixers (DE 2.0/3.0) available. 438 439Example: 440 441panel: panel { 442 compatible = "olimex,lcd-olinuxino-43-ts"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 446 port { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 450 panel_input: endpoint { 451 remote-endpoint = <&tcon0_out_panel>; 452 }; 453 }; 454}; 455 456connector { 457 compatible = "hdmi-connector"; 458 type = "a"; 459 460 port { 461 hdmi_con_in: endpoint { 462 remote-endpoint = <&hdmi_out_con>; 463 }; 464 }; 465}; 466 467hdmi: hdmi@1c16000 { 468 compatible = "allwinner,sun5i-a10s-hdmi"; 469 reg = <0x01c16000 0x1000>; 470 interrupts = <58>; 471 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, 472 <&ccu CLK_PLL_VIDEO0_2X>, 473 <&ccu CLK_PLL_VIDEO1_2X>; 474 clock-names = "ahb", "mod", "pll-0", "pll-1"; 475 dmas = <&dma SUN4I_DMA_NORMAL 16>, 476 <&dma SUN4I_DMA_NORMAL 16>, 477 <&dma SUN4I_DMA_DEDICATED 24>; 478 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 479 480 ports { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 port@0 { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0>; 488 489 hdmi_in_tcon0: endpoint { 490 remote-endpoint = <&tcon0_out_hdmi>; 491 }; 492 }; 493 494 port@1 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <1>; 498 499 hdmi_out_con: endpoint { 500 remote-endpoint = <&hdmi_con_in>; 501 }; 502 }; 503 }; 504}; 505 506tve0: tv-encoder@1c0a000 { 507 compatible = "allwinner,sun4i-a10-tv-encoder"; 508 reg = <0x01c0a000 0x1000>; 509 clocks = <&ahb_gates 34>; 510 resets = <&tcon_ch0_clk 0>; 511 512 port { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 516 tve0_in_tcon0: endpoint@0 { 517 reg = <0>; 518 remote-endpoint = <&tcon0_out_tve0>; 519 }; 520 }; 521}; 522 523tcon0: lcd-controller@1c0c000 { 524 compatible = "allwinner,sun5i-a13-tcon"; 525 reg = <0x01c0c000 0x1000>; 526 interrupts = <44>; 527 resets = <&tcon_ch0_clk 1>; 528 reset-names = "lcd"; 529 clocks = <&ahb_gates 36>, 530 <&tcon_ch0_clk>, 531 <&tcon_ch1_clk>; 532 clock-names = "ahb", 533 "tcon-ch0", 534 "tcon-ch1"; 535 clock-output-names = "tcon-pixel-clock"; 536 537 ports { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 541 tcon0_in: port@0 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <0>; 545 546 tcon0_in_be0: endpoint@0 { 547 reg = <0>; 548 remote-endpoint = <&be0_out_tcon0>; 549 }; 550 }; 551 552 tcon0_out: port@1 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <1>; 556 557 tcon0_out_panel: endpoint@0 { 558 reg = <0>; 559 remote-endpoint = <&panel_input>; 560 }; 561 562 tcon0_out_tve0: endpoint@1 { 563 reg = <1>; 564 remote-endpoint = <&tve0_in_tcon0>; 565 }; 566 }; 567 }; 568}; 569 570fe0: display-frontend@1e00000 { 571 compatible = "allwinner,sun5i-a13-display-frontend"; 572 reg = <0x01e00000 0x20000>; 573 interrupts = <47>; 574 clocks = <&ahb_gates 46>, <&de_fe_clk>, 575 <&dram_gates 25>; 576 clock-names = "ahb", "mod", 577 "ram"; 578 resets = <&de_fe_clk>; 579 580 ports { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 fe0_out: port@1 { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <1>; 588 589 fe0_out_be0: endpoint { 590 remote-endpoint = <&be0_in_fe0>; 591 }; 592 }; 593 }; 594}; 595 596be0: display-backend@1e60000 { 597 compatible = "allwinner,sun5i-a13-display-backend"; 598 reg = <0x01e60000 0x10000>; 599 interrupts = <47>; 600 clocks = <&ahb_gates 44>, <&de_be_clk>, 601 <&dram_gates 26>; 602 clock-names = "ahb", "mod", 603 "ram"; 604 resets = <&de_be_clk>; 605 606 ports { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 610 be0_in: port@0 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 reg = <0>; 614 615 be0_in_fe0: endpoint@0 { 616 reg = <0>; 617 remote-endpoint = <&fe0_out_be0>; 618 }; 619 }; 620 621 be0_out: port@1 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <1>; 625 626 be0_out_tcon0: endpoint@0 { 627 reg = <0>; 628 remote-endpoint = <&tcon0_in_be0>; 629 }; 630 }; 631 }; 632}; 633 634display-engine { 635 compatible = "allwinner,sun5i-a13-display-engine"; 636 allwinner,pipelines = <&fe0>; 637}; 638
