1Qualcomm adreno/snapdragon MDP5 display controller
2
3Description:
4
5This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
6encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
7controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
8
9MDSS:
10Required properties:
11- compatible:
12  * "qcom,mdss" - MDSS
13- reg: Physical base address and length of the controller's registers.
14- reg-names: The names of register regions. The following regions are required:
15  * "mdss_phys"
16  * "vbif_phys"
17- interrupts: The interrupt signal from MDSS.
18- interrupt-controller: identifies the node as an interrupt controller.
19- #interrupt-cells: specifies the number of cells needed to encode an interrupt
20  source, should be 1.
21- power-domains: a power domain consumer specifier according to
22  Documentation/devicetree/bindings/power/power_domain.txt
23- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
24- clock-names: the following clocks are required.
25  * "iface"
26  * "bus"
27  * "vsync"
28- #address-cells: number of address cells for the MDSS children. Should be 1.
29- #size-cells: Should be 1.
30- ranges: parent bus address space is the same as the child bus address space.
31
32Optional properties:
33- clock-names: the following clocks are optional:
34  * "lut"
35
36MDP5:
37Required properties:
38- compatible:
39  * "qcom,mdp5" - MDP5
40- reg: Physical base address and length of the controller's registers.
41- reg-names: The names of register regions. The following regions are required:
42  * "mdp_phys"
43- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
44- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
45- clock-names: the following clocks are required.
46-   * "bus"
47-   * "iface"
48-   * "core"
49-   * "vsync"
50- ports: contains the list of output ports from MDP. These connect to interfaces
51  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
52  special case since it is a part of the MDP block itself).
53
54  Each output port contains an endpoint that describes how it is connected to an
55  external interface. These are described by the standard properties documented
56  here:
57	Documentation/devicetree/bindings/graph.txt
58	Documentation/devicetree/bindings/media/video-interfaces.txt
59
60  The availability of output ports can vary across SoC revisions:
61
62  For MSM8974 and APQ8084:
63	 Port 0 -> MDP_INTF0 (eDP)
64	 Port 1 -> MDP_INTF1 (DSI1)
65	 Port 2 -> MDP_INTF2 (DSI2)
66	 Port 3 -> MDP_INTF3 (HDMI)
67
68  For MSM8916:
69	 Port 0 -> MDP_INTF1 (DSI1)
70
71  For MSM8994 and MSM8996:
72	 Port 0 -> MDP_INTF1 (DSI1)
73	 Port 1 -> MDP_INTF2 (DSI2)
74	 Port 2 -> MDP_INTF3 (HDMI)
75
76Optional properties:
77- clock-names: the following clocks are optional:
78  * "lut"
79
80Example:
81
82/ {
83	...
84
85	mdss: mdss@1a00000 {
86		compatible = "qcom,mdss";
87		reg = <0x1a00000 0x1000>,
88		      <0x1ac8000 0x3000>;
89		reg-names = "mdss_phys", "vbif_phys";
90
91		power-domains = <&gcc MDSS_GDSC>;
92
93		clocks = <&gcc GCC_MDSS_AHB_CLK>,
94			 <&gcc GCC_MDSS_AXI_CLK>,
95			 <&gcc GCC_MDSS_VSYNC_CLK>;
96		clock-names = "iface",
97			      "bus",
98			      "vsync"
99
100		interrupts = <0 72 0>;
101
102		interrupt-controller;
103		#interrupt-cells = <1>;
104
105		#address-cells = <1>;
106		#size-cells = <1>;
107		ranges;
108
109		mdp: mdp@1a01000 {
110			compatible = "qcom,mdp5";
111			reg = <0x1a01000 0x90000>;
112			reg-names = "mdp_phys";
113
114			interrupt-parent = <&mdss>;
115			interrupts = <0 0>;
116
117			clocks = <&gcc GCC_MDSS_AHB_CLK>,
118				 <&gcc GCC_MDSS_AXI_CLK>,
119				 <&gcc GCC_MDSS_MDP_CLK>,
120				 <&gcc GCC_MDSS_VSYNC_CLK>;
121			clock-names = "iface",
122				      "bus",
123				      "core",
124				      "vsync";
125
126			ports {
127				#address-cells = <1>;
128				#size-cells = <0>;
129
130				port@0 {
131					reg = <0>;
132					mdp5_intf1_out: endpoint {
133						remote-endpoint = <&dsi0_in>;
134					};
135				};
136			};
137		};
138
139		dsi0: dsi@1a98000 {
140			...
141			ports {
142				...
143				port@0 {
144					reg = <0>;
145					dsi0_in: endpoint {
146						remote-endpoint = <&mdp5_intf1_out>;
147					};
148				};
149				...
150			};
151			...
152		};
153
154		dsi_phy0: dsi-phy@1a98300 {
155			...
156		};
157	};
158};
159