1Qualcomm adreno/snapdragon MDP4 display controller
2
3Description:
4
5This is the bindings documentation for the MDP4 display controller found in
6SoCs like MSM8960, APQ8064 and MSM8660.
7
8Required properties:
9- compatible:
10  * "qcom,mdp4" - mdp4
11- reg: Physical base address and length of the controller's registers.
12- interrupts: The interrupt signal from the display controller.
13- clocks: device clocks
14  See ../clocks/clock-bindings.txt for details.
15- clock-names: the following clocks are required.
16  * "core_clk"
17  * "iface_clk"
18  * "bus_clk"
19  * "lut_clk"
20  * "hdmi_clk"
21  * "tv_clk"
22- ports: contains the list of output ports from MDP. These connect to interfaces
23  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
24  special case since it is a part of the MDP block itself).
25
26  Each output port contains an endpoint that describes how it is connected to an
27  external interface. These are described by the standard properties documented
28  here:
29	Documentation/devicetree/bindings/graph.txt
30	Documentation/devicetree/bindings/media/video-interfaces.txt
31
32  The output port mappings are:
33	Port 0 -> LCDC/LVDS
34	Port 1 -> DSI1 Cmd/Video
35	Port 2 -> DSI2 Cmd/Video
36	Port 3 -> DTV
37
38Optional properties:
39- clock-names: the following clocks are optional:
40  * "lut_clk"
41- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be
42  used for LCDC. This is only valid for 18bpp panels.
43
44Example:
45
46/ {
47	...
48
49	hdmi: hdmi@4a00000 {
50		...
51		ports {
52			...
53			port@0 {
54				reg = <0>;
55				hdmi_in: endpoint {
56					remote-endpoint = <&mdp_dtv_out>;
57				};
58			};
59			...
60		};
61		...
62	};
63
64	...
65
66	mdp: mdp@5100000 {
67		compatible = "qcom,mdp4";
68		reg = <0x05100000 0xf0000>;
69		interrupts = <GIC_SPI 75 0>;
70		clock-names =
71		    "core_clk",
72		    "iface_clk",
73		    "lut_clk",
74		    "hdmi_clk",
75		    "tv_clk";
76		clocks =
77		    <&mmcc MDP_CLK>,
78		    <&mmcc MDP_AHB_CLK>,
79		    <&mmcc MDP_AXI_CLK>,
80		    <&mmcc MDP_LUT_CLK>,
81		    <&mmcc HDMI_TV_CLK>,
82		    <&mmcc MDP_TV_CLK>;
83
84		ports {
85			#address-cells = <1>;
86			#size-cells = <0>;
87
88				port@0 {
89					reg = <0>;
90					mdp_lvds_out: endpoint {
91					};
92				};
93
94				port@1 {
95					reg = <1>;
96					mdp_dsi1_out: endpoint {
97					};
98				};
99
100				port@2 {
101					reg = <2>;
102					mdp_dsi2_out: endpoint {
103					};
104				};
105
106				port@3 {
107					reg = <3>;
108					mdp_dtv_out: endpoint {
109						remote-endpoint = <&hdmi_in>;
110					};
111				};
112		};
113	};
114};
115