1Qualcomm Technologies Inc. adreno/snapdragon DSI output
2
3DSI Controller:
4Required properties:
5- compatible:
6  * "qcom,mdss-dsi-ctrl"
7- reg: Physical base address and length of the registers of controller
8- reg-names: The names of register regions. The following regions are required:
9  * "dsi_ctrl"
10- interrupts: The interrupt signal from the DSI block.
11- power-domains: Should be <&mmcc MDSS_GDSC>.
12- clocks: Phandles to device clocks.
13- clock-names: the following clocks are required:
14  * "mdp_core"
15  * "iface"
16  * "bus"
17  * "core_mmss"
18  * "byte"
19  * "pixel"
20  * "core"
21  For DSIv2, we need an additional clock:
22   * "src"
23  For DSI6G v2.0 onwards, we need also need the clock:
24   * "byte_intf"
25- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27  by a DSI PHY block. See [1] for details on clock bindings.
28- vdd-supply: phandle to vdd regulator device node
29- vddio-supply: phandle to vdd-io regulator device node
30- vdda-supply: phandle to vdda regulator device node
31- phys: phandle to DSI PHY device node
32- phy-names: the name of the corresponding PHY device
33- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34- ports: Contains 2 DSI controller ports as child nodes. Each port contains
35  an endpoint subnode as defined in [2] and [3].
36
37Optional properties:
38- panel@0: Node of panel connected to this DSI controller.
39  See files in [4] for each supported panel.
40- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41  driving a panel which needs 2 DSI links.
42- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43  the master link of the 2-DSI panel.
44- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45  driving a 2-DSI panel whose 2 links need receive command simultaneously.
46- pinctrl-names: the pin control state names; should contain "default"
47- pinctrl-0: the default pinctrl state (active)
48- pinctrl-n: the "sleep" pinctrl state
49- ports: contains DSI controller input and output ports as children, each
50  containing one endpoint subnode.
51
52  DSI Endpoint properties:
53  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
54    input endpoint. For port@1, set to the MDP interface output. See [2] for
55    device graph info.
56
57  - data-lanes: this describes how the physical DSI data lanes are mapped
58    to the logical lanes on the given platform. The value contained in
59    index n describes what physical lane is mapped to the logical lane n
60    (DATAn, where n lies between 0 and 3). The clock lane position is fixed
61    and can't be changed. Hence, they aren't a part of the DT bindings. See
62    [3] for more info on the data-lanes property.
63
64    For example:
65
66    data-lanes = <3 0 1 2>;
67
68    The above mapping describes that the logical data lane DATA0 is mapped to
69    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
70    to phys DATA1 and logic DATA3 to phys DATA2.
71
72    There are only a limited number of physical to logical mappings possible:
73    <0 1 2 3>
74    <1 2 3 0>
75    <2 3 0 1>
76    <3 0 1 2>
77    <0 3 2 1>
78    <1 0 3 2>
79    <2 1 0 3>
80    <3 2 1 0>
81
82DSI PHY:
83Required properties:
84- compatible: Could be the following
85  * "qcom,dsi-phy-28nm-hpm"
86  * "qcom,dsi-phy-28nm-lp"
87  * "qcom,dsi-phy-20nm"
88  * "qcom,dsi-phy-28nm-8960"
89  * "qcom,dsi-phy-14nm"
90  * "qcom,dsi-phy-10nm"
91  * "qcom,dsi-phy-10nm-8998"
92- reg: Physical base address and length of the registers of PLL, PHY. Some
93  revisions require the PHY regulator base address, whereas others require the
94  PHY lane base address. See below for each PHY revision.
95- reg-names: The names of register regions. The following regions are required:
96  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
97  * "dsi_pll"
98  * "dsi_phy"
99  * "dsi_phy_regulator"
100  For DSI 14nm and 10nm PHYs:
101  * "dsi_pll"
102  * "dsi_phy"
103  * "dsi_phy_lane"
104- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
105  2 clocks: A byte clock (index 0), and a pixel clock (index 1).
106- power-domains: Should be <&mmcc MDSS_GDSC>.
107- clocks: Phandles to device clocks. See [1] for details on clock bindings.
108- clock-names: the following clocks are required:
109  * "iface"
110  * "ref" (only required for new DTS files/entries)
111  For 28nm HPM/LP, 28nm 8960 PHYs:
112- vddio-supply: phandle to vdd-io regulator device node
113  For 20nm PHY:
114- vddio-supply: phandle to vdd-io regulator device node
115- vcca-supply: phandle to vcca regulator device node
116  For 14nm PHY:
117- vcca-supply: phandle to vcca regulator device node
118  For 10nm PHY:
119- vdds-supply: phandle to vdds regulator device node
120
121Optional properties:
122- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
123  regulator is wanted.
124- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
125					panels in microseconds. Driver uses this number to adjust
126					the clock rate according to the expected transfer time.
127					Increasing this value would slow down the mdp processing
128					and can result in slower performance.
129					Decreasing this value can speed up the mdp processing,
130					but this can also impact power consumption.
131					As a rule this time should not be higher than the time
132					that would be expected with the processing at the
133					dsi link rate since anyways this would be the maximum
134					transfer time that could be achieved.
135					If ping pong split is enabled, this time should not be higher
136					than two times the dsi link rate time.
137					If the property is not specified, then the default value is 14000 us.
138
139[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
140[2] Documentation/devicetree/bindings/graph.txt
141[3] Documentation/devicetree/bindings/media/video-interfaces.txt
142[4] Documentation/devicetree/bindings/display/panel/
143
144Example:
145	dsi0: dsi@fd922800 {
146		compatible = "qcom,mdss-dsi-ctrl";
147		qcom,dsi-host-index = <0>;
148		interrupt-parent = <&mdp>;
149		interrupts = <4 0>;
150		reg-names = "dsi_ctrl";
151		reg = <0xfd922800 0x200>;
152		power-domains = <&mmcc MDSS_GDSC>;
153		clock-names =
154			"bus",
155			"byte",
156			"core",
157			"core_mmss",
158			"iface",
159			"mdp_core",
160			"pixel";
161		clocks =
162			<&mmcc MDSS_AXI_CLK>,
163			<&mmcc MDSS_BYTE0_CLK>,
164			<&mmcc MDSS_ESC0_CLK>,
165			<&mmcc MMSS_MISC_AHB_CLK>,
166			<&mmcc MDSS_AHB_CLK>,
167			<&mmcc MDSS_MDP_CLK>,
168			<&mmcc MDSS_PCLK0_CLK>;
169
170		assigned-clocks =
171				 <&mmcc BYTE0_CLK_SRC>,
172				 <&mmcc PCLK0_CLK_SRC>;
173		assigned-clock-parents =
174				 <&dsi_phy0 0>,
175				 <&dsi_phy0 1>;
176
177		vdda-supply = <&pma8084_l2>;
178		vdd-supply = <&pma8084_l22>;
179		vddio-supply = <&pma8084_l12>;
180
181		phys = <&dsi_phy0>;
182		phy-names ="dsi-phy";
183
184		qcom,dual-dsi-mode;
185		qcom,master-dsi;
186		qcom,sync-dual-dsi;
187
188		qcom,mdss-mdp-transfer-time-us = <12000>;
189
190		pinctrl-names = "default", "sleep";
191		pinctrl-0 = <&dsi_active>;
192		pinctrl-1 = <&dsi_suspend>;
193
194		ports {
195			#address-cells = <1>;
196			#size-cells = <0>;
197
198			port@0 {
199				reg = <0>;
200				dsi0_in: endpoint {
201					remote-endpoint = <&mdp_intf1_out>;
202				};
203			};
204
205			port@1 {
206				reg = <1>;
207				dsi0_out: endpoint {
208					remote-endpoint = <&panel_in>;
209					data-lanes = <0 1 2 3>;
210				};
211			};
212		};
213
214		panel: panel@0 {
215			compatible = "sharp,lq101r1sx01";
216			reg = <0>;
217			link2 = <&secondary>;
218
219			power-supply = <...>;
220			backlight = <...>;
221
222			port {
223				panel_in: endpoint {
224					remote-endpoint = <&dsi0_out>;
225				};
226			};
227		};
228	};
229
230	dsi_phy0: dsi-phy@fd922a00 {
231		compatible = "qcom,dsi-phy-28nm-hpm";
232		qcom,dsi-phy-index = <0>;
233		reg-names =
234			"dsi_pll",
235			"dsi_phy",
236			"dsi_phy_regulator";
237		reg =   <0xfd922a00 0xd4>,
238			<0xfd922b00 0x2b0>,
239			<0xfd922d80 0x7b>;
240		clock-names = "iface";
241		clocks = <&mmcc MDSS_AHB_CLK>;
242		#clock-cells = <1>;
243		vddio-supply = <&pma8084_l12>;
244
245		qcom,dsi-phy-regulator-ldo-mode;
246	};
247