1Mediatek HDMI Encoder
2=====================
3
4The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
5its parallel input.
6
7Required properties:
8- compatible: Should be "mediatek,<chip>-hdmi".
9- reg: Physical base address and length of the controller's registers
10- interrupts: The interrupt signal from the function block.
11- clocks: device clocks
12  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
14- phys: phandle link to the HDMI PHY node.
15  See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
16- phy-names: must contain "hdmi"
17- mediatek,syscon-hdmi: phandle link and register offset to the system
18  configuration registers. For mt8173 this must be offset 0x900 into the
19  MMSYS_CONFIG region: <&mmsys 0x900>.
20- ports: A node containing input and output port nodes with endpoint
21  definitions as documented in Documentation/devicetree/bindings/graph.txt.
22- port@0: The input port in the ports node should be connected to a DPI output
23  port.
24- port@1: The output port in the ports node should be connected to the input
25  port of a connector node that contains a ddc-i2c-bus property, or to the
26  input port of an attached bridge chip, such as a SlimPort transmitter.
27
28HDMI CEC
29========
30
31The HDMI CEC controller handles hotplug detection and CEC communication.
32
33Required properties:
34- compatible: Should be "mediatek,<chip>-cec"
35- reg: Physical base address and length of the controller's registers
36- interrupts: The interrupt signal from the function block.
37- clocks: device clock
38
39HDMI DDC
40========
41
42The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
43The Mediatek's I2C controller is used to interface with I2C devices.
44
45Required properties:
46- compatible: Should be "mediatek,<chip>-hdmi-ddc"
47- reg: Physical base address and length of the controller's registers
48- clocks: device clock
49- clock-names: Should be "ddc-i2c".
50
51HDMI PHY
52========
53
54The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
55output and drives the HDMI pads.
56
57Required properties:
58- compatible: "mediatek,<chip>-hdmi-phy"
59- reg: Physical base address and length of the module's registers
60- clocks: PLL reference clock
61- clock-names: must contain "pll_ref"
62- clock-output-names: must be "hdmitx_dig_cts" on mt8173
63- #phy-cells: must be <0>
64- #clock-cells: must be <0>
65
66Optional properties:
67- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
68- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
69
70Example:
71
72cec: cec@10013000 {
73	compatible = "mediatek,mt8173-cec";
74	reg = <0 0x10013000 0 0xbc>;
75	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
76	clocks = <&infracfg CLK_INFRA_CEC>;
77};
78
79hdmi_phy: hdmi-phy@10209100 {
80	compatible = "mediatek,mt8173-hdmi-phy";
81	reg = <0 0x10209100 0 0x24>;
82	clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
83	clock-names = "pll_ref";
84	clock-output-names = "hdmitx_dig_cts";
85	mediatek,ibias = <0xa>;
86	mediatek,ibias_up = <0x1c>;
87	#clock-cells = <0>;
88	#phy-cells = <0>;
89};
90
91hdmi_ddc0: i2c@11012000 {
92	compatible = "mediatek,mt8173-hdmi-ddc";
93	reg = <0 0x11012000 0 0x1c>;
94	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
95	clocks = <&pericfg CLK_PERI_I2C5>;
96	clock-names = "ddc-i2c";
97};
98
99hdmi0: hdmi@14025000 {
100	compatible = "mediatek,mt8173-hdmi";
101	reg = <0 0x14025000 0 0x400>;
102	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
103	clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
104		 <&mmsys CLK_MM_HDMI_PLLCK>,
105		 <&mmsys CLK_MM_HDMI_AUDIO>,
106		 <&mmsys CLK_MM_HDMI_SPDIF>;
107	clock-names = "pixel", "pll", "bclk", "spdif";
108	pinctrl-names = "default";
109	pinctrl-0 = <&hdmi_pin>;
110	phys = <&hdmi_phy>;
111	phy-names = "hdmi";
112	mediatek,syscon-hdmi = <&mmsys 0x900>;
113	assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
114	assigned-clock-parents = <&hdmi_phy>;
115
116	ports {
117		#address-cells = <1>;
118		#size-cells = <0>;
119
120		port@0 {
121			reg = <0>;
122
123			hdmi0_in: endpoint {
124				remote-endpoint = <&dpi0_out>;
125			};
126		};
127
128		port@1 {
129			reg = <1>;
130
131			hdmi0_out: endpoint {
132				remote-endpoint = <&hdmi_con_in>;
133			};
134		};
135	};
136};
137
138connector {
139	compatible = "hdmi-connector";
140	type = "a";
141	ddc-i2c-bus = <&hdmiddc0>;
142
143	port {
144		hdmi_con_in: endpoint {
145			remote-endpoint = <&hdmi0_out>;
146		};
147	};
148};
149