1* Renesas Clock Pulse Generator / Module Standby and Software Reset 2 3On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) 4and MSSR (Module Standby and Software Reset) blocks are intimately connected, 5and share the same register block. 6 7They provide the following functionalities: 8 - The CPG block generates various core clocks, 9 - The MSSR block provides two functions: 10 1. Module Standby, providing a Clock Domain to control the clock supply 11 to individual SoC devices, 12 2. Reset Control, to perform a software reset of individual SoC devices. 13 14Required Properties: 15 - compatible: Must be one of: 16 - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2) 17 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) 18 - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N) 19 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) 20 - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) 21 - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) 22 - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) 23 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) 24 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) 25 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) 26 - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) 27 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) 28 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) 29 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) 30 - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) 31 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) 32 - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) 33 - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3) 34 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) 35 36 - reg: Base address and length of the memory resource used by the CPG/MSSR 37 block 38 39 - clocks: References to external parent clocks, one entry for each entry in 40 clock-names 41 - clock-names: List of external parent clock names. Valid names are: 42 - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, 43 r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, 44 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990, 45 r8a77995) 46 - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) 47 - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, 48 r8a7793, r8a7794) 49 50 - #clock-cells: Must be 2 51 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 52 and a core clock reference, as defined in 53 <dt-bindings/clock/*-cpg-mssr.h>. 54 - For module clocks, the two clock specifier cells must be "CPG_MOD" and 55 a module number, as defined in the datasheet. 56 57 - #power-domain-cells: Must be 0 58 - SoC devices that are part of the CPG/MSSR Clock Domain and can be 59 power-managed through Module Standby should refer to the CPG device 60 node in their "power-domains" property, as documented by the generic PM 61 Domain bindings in 62 Documentation/devicetree/bindings/power/power_domain.txt. 63 64 - #reset-cells: Must be 1 65 - The single reset specifier cell must be the module number, as defined 66 in the datasheet. 67 68 69Examples 70-------- 71 72 - CPG device node: 73 74 cpg: clock-controller@e6150000 { 75 compatible = "renesas,r8a7795-cpg-mssr"; 76 reg = <0 0xe6150000 0 0x1000>; 77 clocks = <&extal_clk>, <&extalr_clk>; 78 clock-names = "extal", "extalr"; 79 #clock-cells = <2>; 80 #power-domain-cells = <0>; 81 #reset-cells = <1>; 82 }; 83 84 85 - CPG/MSSR Clock Domain member device node: 86 87 scif2: serial@e6e88000 { 88 compatible = "renesas,scif-r8a7795", "renesas,scif"; 89 reg = <0 0xe6e88000 0 64>; 90 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&cpg CPG_MOD 310>; 92 clock-names = "fck"; 93 dmas = <&dmac1 0x13>, <&dmac1 0x12>; 94 dma-names = "tx", "rx"; 95 power-domains = <&cpg>; 96 resets = <&cpg 310>; 97 }; 98