1* Samsung Exynos4 Clock Controller
2
3The Exynos4 clock controller generates and supplies clock to various controllers
4within the Exynos4 SoC. The clock binding described here is applicable to all
5SoC's in the Exynos4 family.
6
7Required Properties:
8
9- compatible: should be one of the following.
10  - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11  - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
12
13- reg: physical base address of the controller and length of memory mapped
14  region.
15
16- #clock-cells: should be 1.
17
18Each clock is assigned an identifier and client nodes can use this identifier
19to specify the clock which they consume.
20
21All available clocks are defined as preprocessor macros in
22dt-bindings/clock/exynos4.h header and can be used in device
23tree sources.
24
25Example 1: An example of a clock controller node is listed below.
26
27	clock: clock-controller@10030000 {
28		compatible = "samsung,exynos4210-clock";
29		reg = <0x10030000 0x20000>;
30		#clock-cells = <1>;
31	};
32
33Example 2: UART controller node that consumes the clock generated by the clock
34	   controller. Refer to the standard clock bindings for information
35	   about 'clocks' and 'clock-names' property.
36
37	serial@13820000 {
38		compatible = "samsung,exynos4210-uart";
39		reg = <0x13820000 0x100>;
40		interrupts = <0 54 0>;
41		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
42		clock-names = "uart", "clk_uart_baud0";
43	};
44
45Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
46subsystem. Registers for those clocks are located in the ISP power domain.
47Because those registers are also located in a different memory region than
48the main clock controller, a separate clock controller has to be defined for
49handling them.
50
51Required Properties:
52
53- compatible: should be "samsung,exynos4412-isp-clock".
54
55- reg: physical base address of the ISP clock controller and length of memory
56  mapped region.
57
58- #clock-cells: should be 1.
59
60- clocks: list of the clock controller input clock identifiers,
61  from common clock bindings, should point to CLK_ACLK200 and
62  CLK_ACLK400_MCUISP clocks from the main clock controller.
63
64- clock-names: list of the clock controller input clock names,
65  as described in clock-bindings.txt, should be "aclk200" and
66  "aclk400_mcuisp".
67
68- power-domains: a phandle to ISP power domain node as described by
69  generic PM domain bindings.
70
71Example 3: The clock controllers bindings for Exynos4412 SoCs.
72
73	clock: clock-controller@10030000 {
74		compatible = "samsung,exynos4412-clock";
75		reg = <0x10030000 0x18000>;
76		#clock-cells = <1>;
77	};
78
79	isp_clock: clock-controller@10048000 {
80		compatible = "samsung,exynos4412-isp-clock";
81		reg = <0x10048000 0x1000>;
82		#clock-cells = <1>;
83		power-domains = <&pd_isp>;
84		clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
85		clock-names = "aclk200", "aclk400_mcuisp";
86	};
87