1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Freescale MPC5200 PSC DMA
4 // ALSA SoC Platform driver
5 //
6 // Copyright (C) 2008 Secret Lab Technologies Ltd.
7 // Copyright (C) 2009 Jon Smirl, Digispeaker
8
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/slab.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16
17 #include <sound/soc.h>
18
19 #include <linux/fsl/bestcomm/bestcomm.h>
20 #include <linux/fsl/bestcomm/gen_bd.h>
21 #include <asm/mpc52xx_psc.h>
22
23 #include "mpc5200_dma.h"
24
25 #define DRV_NAME "mpc5200_dma"
26
27 /*
28 * Interrupt handlers
29 */
psc_dma_status_irq(int irq,void * _psc_dma)30 static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
31 {
32 struct psc_dma *psc_dma = _psc_dma;
33 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
34 u16 isr;
35
36 isr = in_be16(®s->mpc52xx_psc_isr);
37
38 /* Playback underrun error */
39 if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
40 psc_dma->stats.underrun_count++;
41
42 /* Capture overrun error */
43 if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
44 psc_dma->stats.overrun_count++;
45
46 out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT);
47
48 return IRQ_HANDLED;
49 }
50
51 /**
52 * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
53 * @s: pointer to stream private data structure
54 *
55 * Enqueues another audio period buffer into the bestcomm queue.
56 *
57 * Note: The routine must only be called when there is space available in
58 * the queue. Otherwise the enqueue will fail and the audio ring buffer
59 * will get out of sync
60 */
psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream * s)61 static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
62 {
63 struct bcom_bd *bd;
64
65 /* Prepare and enqueue the next buffer descriptor */
66 bd = bcom_prepare_next_buffer(s->bcom_task);
67 bd->status = s->period_bytes;
68 bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
69 bcom_submit_next_buffer(s->bcom_task, NULL);
70
71 /* Update for next period */
72 s->period_next = (s->period_next + 1) % s->runtime->periods;
73 }
74
75 /* Bestcomm DMA irq handler */
psc_dma_bcom_irq(int irq,void * _psc_dma_stream)76 static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
77 {
78 struct psc_dma_stream *s = _psc_dma_stream;
79
80 spin_lock(&s->psc_dma->lock);
81 /* For each finished period, dequeue the completed period buffer
82 * and enqueue a new one in it's place. */
83 while (bcom_buffer_done(s->bcom_task)) {
84 bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
85
86 s->period_current = (s->period_current+1) % s->runtime->periods;
87 s->period_count++;
88
89 psc_dma_bcom_enqueue_next_buffer(s);
90 }
91 spin_unlock(&s->psc_dma->lock);
92
93 /* If the stream is active, then also inform the PCM middle layer
94 * of the period finished event. */
95 if (s->active)
96 snd_pcm_period_elapsed(s->stream);
97
98 return IRQ_HANDLED;
99 }
100
101 /**
102 * psc_dma_trigger: start and stop the DMA transfer.
103 *
104 * This function is called by ALSA to start, stop, pause, and resume the DMA
105 * transfer of data.
106 */
psc_dma_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)107 static int psc_dma_trigger(struct snd_soc_component *component,
108 struct snd_pcm_substream *substream, int cmd)
109 {
110 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
111 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
112 struct snd_pcm_runtime *runtime = substream->runtime;
113 struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
114 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
115 u16 imr;
116 unsigned long flags;
117 int i;
118
119 switch (cmd) {
120 case SNDRV_PCM_TRIGGER_START:
121 dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
122 substream->pstr->stream, runtime->frame_bits,
123 (int)runtime->period_size, runtime->periods);
124 s->period_bytes = frames_to_bytes(runtime,
125 runtime->period_size);
126 s->period_next = 0;
127 s->period_current = 0;
128 s->active = 1;
129 s->period_count = 0;
130 s->runtime = runtime;
131
132 /* Fill up the bestcomm bd queue and enable DMA.
133 * This will begin filling the PSC's fifo.
134 */
135 spin_lock_irqsave(&psc_dma->lock, flags);
136
137 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
138 bcom_gen_bd_rx_reset(s->bcom_task);
139 else
140 bcom_gen_bd_tx_reset(s->bcom_task);
141
142 for (i = 0; i < runtime->periods; i++)
143 if (!bcom_queue_full(s->bcom_task))
144 psc_dma_bcom_enqueue_next_buffer(s);
145
146 bcom_enable(s->bcom_task);
147 spin_unlock_irqrestore(&psc_dma->lock, flags);
148
149 out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT);
150
151 break;
152
153 case SNDRV_PCM_TRIGGER_STOP:
154 dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
155 substream->pstr->stream, s->period_count);
156 s->active = 0;
157
158 spin_lock_irqsave(&psc_dma->lock, flags);
159 bcom_disable(s->bcom_task);
160 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
161 bcom_gen_bd_rx_reset(s->bcom_task);
162 else
163 bcom_gen_bd_tx_reset(s->bcom_task);
164 spin_unlock_irqrestore(&psc_dma->lock, flags);
165
166 break;
167
168 default:
169 dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
170 substream->pstr->stream, cmd);
171 return -EINVAL;
172 }
173
174 /* Update interrupt enable settings */
175 imr = 0;
176 if (psc_dma->playback.active)
177 imr |= MPC52xx_PSC_IMR_TXEMP;
178 if (psc_dma->capture.active)
179 imr |= MPC52xx_PSC_IMR_ORERR;
180 out_be16(®s->isr_imr.imr, psc_dma->imr | imr);
181
182 return 0;
183 }
184
185
186 /* ---------------------------------------------------------------------
187 * The PSC DMA 'ASoC platform' driver
188 *
189 * Can be referenced by an 'ASoC machine' driver
190 * This driver only deals with the audio bus; it doesn't have any
191 * interaction with the attached codec
192 */
193
194 static const struct snd_pcm_hardware psc_dma_hardware = {
195 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
196 SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
197 SNDRV_PCM_INFO_BATCH,
198 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
199 SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
200 .period_bytes_max = 1024 * 1024,
201 .period_bytes_min = 32,
202 .periods_min = 2,
203 .periods_max = 256,
204 .buffer_bytes_max = 2 * 1024 * 1024,
205 .fifo_size = 512,
206 };
207
psc_dma_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)208 static int psc_dma_open(struct snd_soc_component *component,
209 struct snd_pcm_substream *substream)
210 {
211 struct snd_pcm_runtime *runtime = substream->runtime;
212 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
213 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
214 struct psc_dma_stream *s;
215 int rc;
216
217 dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
218
219 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
220 s = &psc_dma->capture;
221 else
222 s = &psc_dma->playback;
223
224 snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
225
226 rc = snd_pcm_hw_constraint_integer(runtime,
227 SNDRV_PCM_HW_PARAM_PERIODS);
228 if (rc < 0) {
229 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
230 return rc;
231 }
232
233 s->stream = substream;
234 return 0;
235 }
236
psc_dma_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)237 static int psc_dma_close(struct snd_soc_component *component,
238 struct snd_pcm_substream *substream)
239 {
240 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
241 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
242 struct psc_dma_stream *s;
243
244 dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
245
246 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
247 s = &psc_dma->capture;
248 else
249 s = &psc_dma->playback;
250
251 if (!psc_dma->playback.active &&
252 !psc_dma->capture.active) {
253
254 /* Disable all interrupts and reset the PSC */
255 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
256 out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
257 }
258 s->stream = NULL;
259 return 0;
260 }
261
262 static snd_pcm_uframes_t
psc_dma_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)263 psc_dma_pointer(struct snd_soc_component *component,
264 struct snd_pcm_substream *substream)
265 {
266 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
267 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
268 struct psc_dma_stream *s;
269 dma_addr_t count;
270
271 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
272 s = &psc_dma->capture;
273 else
274 s = &psc_dma->playback;
275
276 count = s->period_current * s->period_bytes;
277
278 return bytes_to_frames(substream->runtime, count);
279 }
280
psc_dma_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)281 static int psc_dma_new(struct snd_soc_component *component,
282 struct snd_soc_pcm_runtime *rtd)
283 {
284 struct snd_card *card = rtd->card->snd_card;
285 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
286 struct snd_pcm *pcm = rtd->pcm;
287 size_t size = psc_dma_hardware.buffer_bytes_max;
288 int rc;
289
290 dev_dbg(component->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
291 card, dai, pcm);
292
293 rc = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
294 if (rc)
295 return rc;
296
297 return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, card->dev,
298 size);
299 }
300
301 static const struct snd_soc_component_driver mpc5200_audio_dma_component = {
302 .name = DRV_NAME,
303 .open = psc_dma_open,
304 .close = psc_dma_close,
305 .pointer = psc_dma_pointer,
306 .trigger = psc_dma_trigger,
307 .pcm_construct = psc_dma_new,
308 };
309
mpc5200_audio_dma_create(struct platform_device * op)310 int mpc5200_audio_dma_create(struct platform_device *op)
311 {
312 phys_addr_t fifo;
313 struct psc_dma *psc_dma;
314 struct resource res;
315 int size, irq, rc;
316 const __be32 *prop;
317 void __iomem *regs;
318 int ret;
319
320 /* Fetch the registers and IRQ of the PSC */
321 irq = irq_of_parse_and_map(op->dev.of_node, 0);
322 if (of_address_to_resource(op->dev.of_node, 0, &res)) {
323 dev_err(&op->dev, "Missing reg property\n");
324 return -ENODEV;
325 }
326 regs = ioremap(res.start, resource_size(&res));
327 if (!regs) {
328 dev_err(&op->dev, "Could not map registers\n");
329 return -ENODEV;
330 }
331
332 /* Allocate and initialize the driver private data */
333 psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
334 if (!psc_dma) {
335 ret = -ENOMEM;
336 goto out_unmap;
337 }
338
339 /* Get the PSC ID */
340 prop = of_get_property(op->dev.of_node, "cell-index", &size);
341 if (!prop || size < sizeof *prop) {
342 ret = -ENODEV;
343 goto out_free;
344 }
345
346 spin_lock_init(&psc_dma->lock);
347 mutex_init(&psc_dma->mutex);
348 psc_dma->id = be32_to_cpu(*prop);
349 psc_dma->irq = irq;
350 psc_dma->psc_regs = regs;
351 psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
352 psc_dma->dev = &op->dev;
353 psc_dma->playback.psc_dma = psc_dma;
354 psc_dma->capture.psc_dma = psc_dma;
355 snprintf(psc_dma->name, sizeof(psc_dma->name), "PSC%d", psc_dma->id);
356
357 /* Find the address of the fifo data registers and setup the
358 * DMA tasks */
359 fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
360 psc_dma->capture.bcom_task =
361 bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
362 psc_dma->playback.bcom_task =
363 bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
364 if (!psc_dma->capture.bcom_task ||
365 !psc_dma->playback.bcom_task) {
366 dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
367 ret = -ENODEV;
368 goto out_free;
369 }
370
371 /* Disable all interrupts and reset the PSC */
372 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
373 /* reset receiver */
374 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
375 /* reset transmitter */
376 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
377 /* reset error */
378 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
379 /* reset mode */
380 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
381
382 /* Set up mode register;
383 * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
384 * Second write: register Normal mode for non loopback
385 */
386 out_8(&psc_dma->psc_regs->mode, 0);
387 out_8(&psc_dma->psc_regs->mode, 0);
388
389 /* Set the TX and RX fifo alarm thresholds */
390 out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
391 out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
392 out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
393 out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
394
395 /* Lookup the IRQ numbers */
396 psc_dma->playback.irq =
397 bcom_get_task_irq(psc_dma->playback.bcom_task);
398 psc_dma->capture.irq =
399 bcom_get_task_irq(psc_dma->capture.bcom_task);
400
401 rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
402 "psc-dma-status", psc_dma);
403 rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
404 "psc-dma-capture", &psc_dma->capture);
405 rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
406 "psc-dma-playback", &psc_dma->playback);
407 if (rc) {
408 ret = -ENODEV;
409 goto out_irq;
410 }
411
412 /* Save what we've done so it can be found again later */
413 dev_set_drvdata(&op->dev, psc_dma);
414
415 /* Tell the ASoC OF helpers about it */
416 return devm_snd_soc_register_component(&op->dev,
417 &mpc5200_audio_dma_component, NULL, 0);
418 out_irq:
419 free_irq(psc_dma->irq, psc_dma);
420 free_irq(psc_dma->capture.irq, &psc_dma->capture);
421 free_irq(psc_dma->playback.irq, &psc_dma->playback);
422 out_free:
423 kfree(psc_dma);
424 out_unmap:
425 iounmap(regs);
426 return ret;
427 }
428 EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
429
mpc5200_audio_dma_destroy(struct platform_device * op)430 int mpc5200_audio_dma_destroy(struct platform_device *op)
431 {
432 struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
433
434 dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
435
436 bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
437 bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
438
439 /* Release irqs */
440 free_irq(psc_dma->irq, psc_dma);
441 free_irq(psc_dma->capture.irq, &psc_dma->capture);
442 free_irq(psc_dma->playback.irq, &psc_dma->playback);
443
444 iounmap(psc_dma->psc_regs);
445 kfree(psc_dma);
446 dev_set_drvdata(&op->dev, NULL);
447
448 return 0;
449 }
450 EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
451
452 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
453 MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
454 MODULE_LICENSE("GPL");
455