1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
4 *
5 * Copyright (C) 2005 SAN People
6 * Copyright (C) 2008 Atmel
7 *
8 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
9 * ATMEL CORP.
10 *
11 * Based on at91-ssc.c by
12 * Frank Mandarino <fmandarino@endrelia.com>
13 * Based on pxa2xx Platform drivers by
14 * Liam Girdwood <lrg@slimlogic.co.uk>
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/atmel_pdc.h>
24
25 #include <linux/atmel-ssc.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
31
32 #include "atmel-pcm.h"
33 #include "atmel_ssc_dai.h"
34
35
36 #define NUM_SSC_DEVICES 3
37
38 /*
39 * SSC PDC registers required by the PCM DMA engine.
40 */
41 static struct atmel_pdc_regs pdc_tx_reg = {
42 .xpr = ATMEL_PDC_TPR,
43 .xcr = ATMEL_PDC_TCR,
44 .xnpr = ATMEL_PDC_TNPR,
45 .xncr = ATMEL_PDC_TNCR,
46 };
47
48 static struct atmel_pdc_regs pdc_rx_reg = {
49 .xpr = ATMEL_PDC_RPR,
50 .xcr = ATMEL_PDC_RCR,
51 .xnpr = ATMEL_PDC_RNPR,
52 .xncr = ATMEL_PDC_RNCR,
53 };
54
55 /*
56 * SSC & PDC status bits for transmit and receive.
57 */
58 static struct atmel_ssc_mask ssc_tx_mask = {
59 .ssc_enable = SSC_BIT(CR_TXEN),
60 .ssc_disable = SSC_BIT(CR_TXDIS),
61 .ssc_endx = SSC_BIT(SR_ENDTX),
62 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
63 .ssc_error = SSC_BIT(SR_OVRUN),
64 .pdc_enable = ATMEL_PDC_TXTEN,
65 .pdc_disable = ATMEL_PDC_TXTDIS,
66 };
67
68 static struct atmel_ssc_mask ssc_rx_mask = {
69 .ssc_enable = SSC_BIT(CR_RXEN),
70 .ssc_disable = SSC_BIT(CR_RXDIS),
71 .ssc_endx = SSC_BIT(SR_ENDRX),
72 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
73 .ssc_error = SSC_BIT(SR_OVRUN),
74 .pdc_enable = ATMEL_PDC_RXTEN,
75 .pdc_disable = ATMEL_PDC_RXTDIS,
76 };
77
78
79 /*
80 * DMA parameters.
81 */
82 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
83 {{
84 .name = "SSC0 PCM out",
85 .pdc = &pdc_tx_reg,
86 .mask = &ssc_tx_mask,
87 },
88 {
89 .name = "SSC0 PCM in",
90 .pdc = &pdc_rx_reg,
91 .mask = &ssc_rx_mask,
92 } },
93 {{
94 .name = "SSC1 PCM out",
95 .pdc = &pdc_tx_reg,
96 .mask = &ssc_tx_mask,
97 },
98 {
99 .name = "SSC1 PCM in",
100 .pdc = &pdc_rx_reg,
101 .mask = &ssc_rx_mask,
102 } },
103 {{
104 .name = "SSC2 PCM out",
105 .pdc = &pdc_tx_reg,
106 .mask = &ssc_tx_mask,
107 },
108 {
109 .name = "SSC2 PCM in",
110 .pdc = &pdc_rx_reg,
111 .mask = &ssc_rx_mask,
112 } },
113 };
114
115
116 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
117 {
118 .name = "ssc0",
119 .dir_mask = SSC_DIR_MASK_UNUSED,
120 .initialized = 0,
121 },
122 {
123 .name = "ssc1",
124 .dir_mask = SSC_DIR_MASK_UNUSED,
125 .initialized = 0,
126 },
127 {
128 .name = "ssc2",
129 .dir_mask = SSC_DIR_MASK_UNUSED,
130 .initialized = 0,
131 },
132 };
133
134
135 /*
136 * SSC interrupt handler. Passes PDC interrupts to the DMA
137 * interrupt handler in the PCM driver.
138 */
atmel_ssc_interrupt(int irq,void * dev_id)139 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
140 {
141 struct atmel_ssc_info *ssc_p = dev_id;
142 struct atmel_pcm_dma_params *dma_params;
143 u32 ssc_sr;
144 u32 ssc_substream_mask;
145 int i;
146
147 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
148 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
149
150 /*
151 * Loop through the substreams attached to this SSC. If
152 * a DMA-related interrupt occurred on that substream, call
153 * the DMA interrupt handler function, if one has been
154 * registered in the dma_params structure by the PCM driver.
155 */
156 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
157 dma_params = ssc_p->dma_params[i];
158
159 if ((dma_params != NULL) &&
160 (dma_params->dma_intr_handler != NULL)) {
161 ssc_substream_mask = (dma_params->mask->ssc_endx |
162 dma_params->mask->ssc_endbuf);
163 if (ssc_sr & ssc_substream_mask) {
164 dma_params->dma_intr_handler(ssc_sr,
165 dma_params->
166 substream);
167 }
168 }
169 }
170
171 return IRQ_HANDLED;
172 }
173
174 /*
175 * When the bit clock is input, limit the maximum rate according to the
176 * Serial Clock Ratio Considerations section from the SSC documentation:
177 *
178 * The Transmitter and the Receiver can be programmed to operate
179 * with the clock signals provided on either the TK or RK pins.
180 * This allows the SSC to support many slave-mode data transfers.
181 * In this case, the maximum clock speed allowed on the RK pin is:
182 * - Peripheral clock divided by 2 if Receiver Frame Synchro is input
183 * - Peripheral clock divided by 3 if Receiver Frame Synchro is output
184 * In addition, the maximum clock speed allowed on the TK pin is:
185 * - Peripheral clock divided by 6 if Transmit Frame Synchro is input
186 * - Peripheral clock divided by 2 if Transmit Frame Synchro is output
187 *
188 * When the bit clock is output, limit the rate according to the
189 * SSC divider restrictions.
190 */
atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)191 static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params,
192 struct snd_pcm_hw_rule *rule)
193 {
194 struct atmel_ssc_info *ssc_p = rule->private;
195 struct ssc_device *ssc = ssc_p->ssc;
196 struct snd_interval *i = hw_param_interval(params, rule->var);
197 struct snd_interval t;
198 struct snd_ratnum r = {
199 .den_min = 1,
200 .den_max = 4095,
201 .den_step = 1,
202 };
203 unsigned int num = 0, den = 0;
204 int frame_size;
205 int mck_div = 2;
206 int ret;
207
208 frame_size = snd_soc_params_to_frame_size(params);
209 if (frame_size < 0)
210 return frame_size;
211
212 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
213 case SND_SOC_DAIFMT_CBM_CFS:
214 if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE)
215 && ssc->clk_from_rk_pin)
216 /* Receiver Frame Synchro (i.e. capture)
217 * is output (format is _CFS) and the RK pin
218 * is used for input (format is _CBM_).
219 */
220 mck_div = 3;
221 break;
222
223 case SND_SOC_DAIFMT_CBM_CFM:
224 if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK)
225 && !ssc->clk_from_rk_pin)
226 /* Transmit Frame Synchro (i.e. playback)
227 * is input (format is _CFM) and the TK pin
228 * is used for input (format _CBM_ but not
229 * using the RK pin).
230 */
231 mck_div = 6;
232 break;
233 }
234
235 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
236 case SND_SOC_DAIFMT_CBS_CFS:
237 r.num = ssc_p->mck_rate / mck_div / frame_size;
238
239 ret = snd_interval_ratnum(i, 1, &r, &num, &den);
240 if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) {
241 params->rate_num = num;
242 params->rate_den = den;
243 }
244 break;
245
246 case SND_SOC_DAIFMT_CBM_CFS:
247 case SND_SOC_DAIFMT_CBM_CFM:
248 t.min = 8000;
249 t.max = ssc_p->mck_rate / mck_div / frame_size;
250 t.openmin = t.openmax = 0;
251 t.integer = 0;
252 ret = snd_interval_refine(i, &t);
253 break;
254
255 default:
256 ret = -EINVAL;
257 break;
258 }
259
260 return ret;
261 }
262
263 /*-------------------------------------------------------------------------*\
264 * DAI functions
265 \*-------------------------------------------------------------------------*/
266 /*
267 * Startup. Only that one substream allowed in each direction.
268 */
atmel_ssc_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)269 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
270 struct snd_soc_dai *dai)
271 {
272 struct platform_device *pdev = to_platform_device(dai->dev);
273 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
274 struct atmel_pcm_dma_params *dma_params;
275 int dir, dir_mask;
276 int ret;
277
278 pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n",
279 ssc_readl(ssc_p->ssc->regs, SR));
280
281 /* Enable PMC peripheral clock for this SSC */
282 pr_debug("atmel_ssc_dai: Starting clock\n");
283 clk_enable(ssc_p->ssc->clk);
284 ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk);
285
286 /* Reset the SSC unless initialized to keep it in a clean state */
287 if (!ssc_p->initialized)
288 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
289
290 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
291 dir = 0;
292 dir_mask = SSC_DIR_MASK_PLAYBACK;
293 } else {
294 dir = 1;
295 dir_mask = SSC_DIR_MASK_CAPTURE;
296 }
297
298 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
299 SNDRV_PCM_HW_PARAM_RATE,
300 atmel_ssc_hw_rule_rate,
301 ssc_p,
302 SNDRV_PCM_HW_PARAM_FRAME_BITS,
303 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
304 if (ret < 0) {
305 dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret);
306 return ret;
307 }
308
309 dma_params = &ssc_dma_params[pdev->id][dir];
310 dma_params->ssc = ssc_p->ssc;
311 dma_params->substream = substream;
312
313 ssc_p->dma_params[dir] = dma_params;
314
315 snd_soc_dai_set_dma_data(dai, substream, dma_params);
316
317 if (ssc_p->dir_mask & dir_mask)
318 return -EBUSY;
319
320 ssc_p->dir_mask |= dir_mask;
321
322 return 0;
323 }
324
325 /*
326 * Shutdown. Clear DMA parameters and shutdown the SSC if there
327 * are no other substreams open.
328 */
atmel_ssc_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)329 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
330 struct snd_soc_dai *dai)
331 {
332 struct platform_device *pdev = to_platform_device(dai->dev);
333 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
334 struct atmel_pcm_dma_params *dma_params;
335 int dir, dir_mask;
336
337 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
338 dir = 0;
339 else
340 dir = 1;
341
342 dma_params = ssc_p->dma_params[dir];
343
344 if (dma_params != NULL) {
345 dma_params->ssc = NULL;
346 dma_params->substream = NULL;
347 ssc_p->dma_params[dir] = NULL;
348 }
349
350 dir_mask = 1 << dir;
351
352 ssc_p->dir_mask &= ~dir_mask;
353 if (!ssc_p->dir_mask) {
354 if (ssc_p->initialized) {
355 free_irq(ssc_p->ssc->irq, ssc_p);
356 ssc_p->initialized = 0;
357 }
358
359 /* Reset the SSC */
360 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
361 /* Clear the SSC dividers */
362 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
363 ssc_p->forced_divider = 0;
364 }
365
366 /* Shutdown the SSC clock. */
367 pr_debug("atmel_ssc_dai: Stopping clock\n");
368 clk_disable(ssc_p->ssc->clk);
369 }
370
371
372 /*
373 * Record the DAI format for use in hw_params().
374 */
atmel_ssc_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)375 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
376 unsigned int fmt)
377 {
378 struct platform_device *pdev = to_platform_device(cpu_dai->dev);
379 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
380
381 ssc_p->daifmt = fmt;
382 return 0;
383 }
384
385 /*
386 * Record SSC clock dividers for use in hw_params().
387 */
atmel_ssc_set_dai_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)388 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
389 int div_id, int div)
390 {
391 struct platform_device *pdev = to_platform_device(cpu_dai->dev);
392 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
393
394 switch (div_id) {
395 case ATMEL_SSC_CMR_DIV:
396 /*
397 * The same master clock divider is used for both
398 * transmit and receive, so if a value has already
399 * been set, it must match this value.
400 */
401 if (ssc_p->dir_mask !=
402 (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
403 ssc_p->cmr_div = div;
404 else if (ssc_p->cmr_div == 0)
405 ssc_p->cmr_div = div;
406 else
407 if (div != ssc_p->cmr_div)
408 return -EBUSY;
409 ssc_p->forced_divider |= BIT(ATMEL_SSC_CMR_DIV);
410 break;
411
412 case ATMEL_SSC_TCMR_PERIOD:
413 ssc_p->tcmr_period = div;
414 ssc_p->forced_divider |= BIT(ATMEL_SSC_TCMR_PERIOD);
415 break;
416
417 case ATMEL_SSC_RCMR_PERIOD:
418 ssc_p->rcmr_period = div;
419 ssc_p->forced_divider |= BIT(ATMEL_SSC_RCMR_PERIOD);
420 break;
421
422 default:
423 return -EINVAL;
424 }
425
426 return 0;
427 }
428
429 /* Is the cpu-dai master of the frame clock? */
atmel_ssc_cfs(struct atmel_ssc_info * ssc_p)430 static int atmel_ssc_cfs(struct atmel_ssc_info *ssc_p)
431 {
432 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
433 case SND_SOC_DAIFMT_CBM_CFS:
434 case SND_SOC_DAIFMT_CBS_CFS:
435 return 1;
436 }
437 return 0;
438 }
439
440 /* Is the cpu-dai master of the bit clock? */
atmel_ssc_cbs(struct atmel_ssc_info * ssc_p)441 static int atmel_ssc_cbs(struct atmel_ssc_info *ssc_p)
442 {
443 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
444 case SND_SOC_DAIFMT_CBS_CFM:
445 case SND_SOC_DAIFMT_CBS_CFS:
446 return 1;
447 }
448 return 0;
449 }
450
451 /*
452 * Configure the SSC.
453 */
atmel_ssc_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)454 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
455 struct snd_pcm_hw_params *params,
456 struct snd_soc_dai *dai)
457 {
458 struct platform_device *pdev = to_platform_device(dai->dev);
459 int id = pdev->id;
460 struct atmel_ssc_info *ssc_p = &ssc_info[id];
461 struct ssc_device *ssc = ssc_p->ssc;
462 struct atmel_pcm_dma_params *dma_params;
463 int dir, channels, bits;
464 u32 tfmr, rfmr, tcmr, rcmr;
465 int ret;
466 int fslen, fslen_ext, fs_osync, fs_edge;
467 u32 cmr_div;
468 u32 tcmr_period;
469 u32 rcmr_period;
470
471 /*
472 * Currently, there is only one set of dma params for
473 * each direction. If more are added, this code will
474 * have to be changed to select the proper set.
475 */
476 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
477 dir = 0;
478 else
479 dir = 1;
480
481 /*
482 * If the cpu dai should provide BCLK, but noone has provided the
483 * divider needed for that to work, fall back to something sensible.
484 */
485 cmr_div = ssc_p->cmr_div;
486 if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_CMR_DIV)) &&
487 atmel_ssc_cbs(ssc_p)) {
488 int bclk_rate = snd_soc_params_to_bclk(params);
489
490 if (bclk_rate < 0) {
491 dev_err(dai->dev, "unable to calculate cmr_div: %d\n",
492 bclk_rate);
493 return bclk_rate;
494 }
495
496 cmr_div = DIV_ROUND_CLOSEST(ssc_p->mck_rate, 2 * bclk_rate);
497 }
498
499 /*
500 * If the cpu dai should provide LRCLK, but noone has provided the
501 * dividers needed for that to work, fall back to something sensible.
502 */
503 tcmr_period = ssc_p->tcmr_period;
504 rcmr_period = ssc_p->rcmr_period;
505 if (atmel_ssc_cfs(ssc_p)) {
506 int frame_size = snd_soc_params_to_frame_size(params);
507
508 if (frame_size < 0) {
509 dev_err(dai->dev,
510 "unable to calculate tx/rx cmr_period: %d\n",
511 frame_size);
512 return frame_size;
513 }
514
515 if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_TCMR_PERIOD)))
516 tcmr_period = frame_size / 2 - 1;
517 if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_RCMR_PERIOD)))
518 rcmr_period = frame_size / 2 - 1;
519 }
520
521 dma_params = ssc_p->dma_params[dir];
522
523 channels = params_channels(params);
524
525 /*
526 * Determine sample size in bits and the PDC increment.
527 */
528 switch (params_format(params)) {
529 case SNDRV_PCM_FORMAT_S8:
530 bits = 8;
531 dma_params->pdc_xfer_size = 1;
532 break;
533 case SNDRV_PCM_FORMAT_S16_LE:
534 bits = 16;
535 dma_params->pdc_xfer_size = 2;
536 break;
537 case SNDRV_PCM_FORMAT_S24_LE:
538 bits = 24;
539 dma_params->pdc_xfer_size = 4;
540 break;
541 case SNDRV_PCM_FORMAT_S32_LE:
542 bits = 32;
543 dma_params->pdc_xfer_size = 4;
544 break;
545 default:
546 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
547 return -EINVAL;
548 }
549
550 /*
551 * Compute SSC register settings.
552 */
553
554 fslen_ext = (bits - 1) / 16;
555 fslen = (bits - 1) % 16;
556
557 switch (ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) {
558
559 case SND_SOC_DAIFMT_LEFT_J:
560 fs_osync = SSC_FSOS_POSITIVE;
561 fs_edge = SSC_START_RISING_RF;
562
563 rcmr = SSC_BF(RCMR_STTDLY, 0);
564 tcmr = SSC_BF(TCMR_STTDLY, 0);
565
566 break;
567
568 case SND_SOC_DAIFMT_I2S:
569 fs_osync = SSC_FSOS_NEGATIVE;
570 fs_edge = SSC_START_FALLING_RF;
571
572 rcmr = SSC_BF(RCMR_STTDLY, 1);
573 tcmr = SSC_BF(TCMR_STTDLY, 1);
574
575 break;
576
577 case SND_SOC_DAIFMT_DSP_A:
578 /*
579 * DSP/PCM Mode A format
580 *
581 * Data is transferred on first BCLK after LRC pulse rising
582 * edge.If stereo, the right channel data is contiguous with
583 * the left channel data.
584 */
585 fs_osync = SSC_FSOS_POSITIVE;
586 fs_edge = SSC_START_RISING_RF;
587 fslen = fslen_ext = 0;
588
589 rcmr = SSC_BF(RCMR_STTDLY, 1);
590 tcmr = SSC_BF(TCMR_STTDLY, 1);
591
592 break;
593
594 default:
595 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
596 ssc_p->daifmt);
597 return -EINVAL;
598 }
599
600 if (!atmel_ssc_cfs(ssc_p)) {
601 fslen = fslen_ext = 0;
602 rcmr_period = tcmr_period = 0;
603 fs_osync = SSC_FSOS_NONE;
604 }
605
606 rcmr |= SSC_BF(RCMR_START, fs_edge);
607 tcmr |= SSC_BF(TCMR_START, fs_edge);
608
609 if (atmel_ssc_cbs(ssc_p)) {
610 /*
611 * SSC provides BCLK
612 *
613 * The SSC transmit and receive clocks are generated from the
614 * MCK divider, and the BCLK signal is output
615 * on the SSC TK line.
616 */
617 rcmr |= SSC_BF(RCMR_CKS, SSC_CKS_DIV)
618 | SSC_BF(RCMR_CKO, SSC_CKO_NONE);
619
620 tcmr |= SSC_BF(TCMR_CKS, SSC_CKS_DIV)
621 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS);
622 } else {
623 rcmr |= SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
624 SSC_CKS_PIN : SSC_CKS_CLOCK)
625 | SSC_BF(RCMR_CKO, SSC_CKO_NONE);
626
627 tcmr |= SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
628 SSC_CKS_CLOCK : SSC_CKS_PIN)
629 | SSC_BF(TCMR_CKO, SSC_CKO_NONE);
630 }
631
632 rcmr |= SSC_BF(RCMR_PERIOD, rcmr_period)
633 | SSC_BF(RCMR_CKI, SSC_CKI_RISING);
634
635 tcmr |= SSC_BF(TCMR_PERIOD, tcmr_period)
636 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING);
637
638 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
639 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
640 | SSC_BF(RFMR_FSOS, fs_osync)
641 | SSC_BF(RFMR_FSLEN, fslen)
642 | SSC_BF(RFMR_DATNB, (channels - 1))
643 | SSC_BIT(RFMR_MSBF)
644 | SSC_BF(RFMR_LOOP, 0)
645 | SSC_BF(RFMR_DATLEN, (bits - 1));
646
647 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
648 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
649 | SSC_BF(TFMR_FSDEN, 0)
650 | SSC_BF(TFMR_FSOS, fs_osync)
651 | SSC_BF(TFMR_FSLEN, fslen)
652 | SSC_BF(TFMR_DATNB, (channels - 1))
653 | SSC_BIT(TFMR_MSBF)
654 | SSC_BF(TFMR_DATDEF, 0)
655 | SSC_BF(TFMR_DATLEN, (bits - 1));
656
657 if (fslen_ext && !ssc->pdata->has_fslen_ext) {
658 dev_err(dai->dev, "sample size %d is too large for SSC device\n",
659 bits);
660 return -EINVAL;
661 }
662
663 pr_debug("atmel_ssc_hw_params: "
664 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
665 rcmr, rfmr, tcmr, tfmr);
666
667 if (!ssc_p->initialized) {
668 if (!ssc_p->ssc->pdata->use_dma) {
669 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
670 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
671 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
672 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
673
674 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
675 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
676 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
677 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
678 }
679
680 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
681 ssc_p->name, ssc_p);
682 if (ret < 0) {
683 printk(KERN_WARNING
684 "atmel_ssc_dai: request_irq failure\n");
685 pr_debug("Atmel_ssc_dai: Stopping clock\n");
686 clk_disable(ssc_p->ssc->clk);
687 return ret;
688 }
689
690 ssc_p->initialized = 1;
691 }
692
693 /* set SSC clock mode register */
694 ssc_writel(ssc_p->ssc->regs, CMR, cmr_div);
695
696 /* set receive clock mode and format */
697 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
698 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
699
700 /* set transmit clock mode and format */
701 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
702 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
703
704 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
705 return 0;
706 }
707
708
atmel_ssc_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)709 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
710 struct snd_soc_dai *dai)
711 {
712 struct platform_device *pdev = to_platform_device(dai->dev);
713 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
714 struct atmel_pcm_dma_params *dma_params;
715 int dir;
716
717 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
718 dir = 0;
719 else
720 dir = 1;
721
722 dma_params = ssc_p->dma_params[dir];
723
724 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
725 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
726
727 pr_debug("%s enabled SSC_SR=0x%08x\n",
728 dir ? "receive" : "transmit",
729 ssc_readl(ssc_p->ssc->regs, SR));
730 return 0;
731 }
732
atmel_ssc_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)733 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
734 int cmd, struct snd_soc_dai *dai)
735 {
736 struct platform_device *pdev = to_platform_device(dai->dev);
737 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
738 struct atmel_pcm_dma_params *dma_params;
739 int dir;
740
741 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
742 dir = 0;
743 else
744 dir = 1;
745
746 dma_params = ssc_p->dma_params[dir];
747
748 switch (cmd) {
749 case SNDRV_PCM_TRIGGER_START:
750 case SNDRV_PCM_TRIGGER_RESUME:
751 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
752 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
753 break;
754 default:
755 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
756 break;
757 }
758
759 return 0;
760 }
761
762 #ifdef CONFIG_PM
atmel_ssc_suspend(struct snd_soc_component * component)763 static int atmel_ssc_suspend(struct snd_soc_component *component)
764 {
765 struct atmel_ssc_info *ssc_p;
766 struct platform_device *pdev = to_platform_device(component->dev);
767
768 if (!snd_soc_component_active(component))
769 return 0;
770
771 ssc_p = &ssc_info[pdev->id];
772
773 /* Save the status register before disabling transmit and receive */
774 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
775 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
776
777 /* Save the current interrupt mask, then disable unmasked interrupts */
778 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
779 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
780
781 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
782 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
783 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
784 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
785 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
786
787 return 0;
788 }
789
atmel_ssc_resume(struct snd_soc_component * component)790 static int atmel_ssc_resume(struct snd_soc_component *component)
791 {
792 struct atmel_ssc_info *ssc_p;
793 struct platform_device *pdev = to_platform_device(component->dev);
794 u32 cr;
795
796 if (!snd_soc_component_active(component))
797 return 0;
798
799 ssc_p = &ssc_info[pdev->id];
800
801 /* restore SSC register settings */
802 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
803 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
804 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
805 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
806 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
807
808 /* re-enable interrupts */
809 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
810
811 /* Re-enable receive and transmit as appropriate */
812 cr = 0;
813 cr |=
814 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
815 cr |=
816 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
817 ssc_writel(ssc_p->ssc->regs, CR, cr);
818
819 return 0;
820 }
821 #else /* CONFIG_PM */
822 # define atmel_ssc_suspend NULL
823 # define atmel_ssc_resume NULL
824 #endif /* CONFIG_PM */
825
826 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
827 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
828
829 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
830 .startup = atmel_ssc_startup,
831 .shutdown = atmel_ssc_shutdown,
832 .prepare = atmel_ssc_prepare,
833 .trigger = atmel_ssc_trigger,
834 .hw_params = atmel_ssc_hw_params,
835 .set_fmt = atmel_ssc_set_dai_fmt,
836 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
837 };
838
839 static struct snd_soc_dai_driver atmel_ssc_dai = {
840 .playback = {
841 .channels_min = 1,
842 .channels_max = 2,
843 .rates = SNDRV_PCM_RATE_CONTINUOUS,
844 .rate_min = 8000,
845 .rate_max = 384000,
846 .formats = ATMEL_SSC_FORMATS,},
847 .capture = {
848 .channels_min = 1,
849 .channels_max = 2,
850 .rates = SNDRV_PCM_RATE_CONTINUOUS,
851 .rate_min = 8000,
852 .rate_max = 384000,
853 .formats = ATMEL_SSC_FORMATS,},
854 .ops = &atmel_ssc_dai_ops,
855 };
856
857 static const struct snd_soc_component_driver atmel_ssc_component = {
858 .name = "atmel-ssc",
859 .suspend = atmel_ssc_suspend,
860 .resume = atmel_ssc_resume,
861 };
862
asoc_ssc_init(struct device * dev)863 static int asoc_ssc_init(struct device *dev)
864 {
865 struct ssc_device *ssc = dev_get_drvdata(dev);
866 int ret;
867
868 ret = devm_snd_soc_register_component(dev, &atmel_ssc_component,
869 &atmel_ssc_dai, 1);
870 if (ret) {
871 dev_err(dev, "Could not register DAI: %d\n", ret);
872 return ret;
873 }
874
875 if (ssc->pdata->use_dma)
876 ret = atmel_pcm_dma_platform_register(dev);
877 else
878 ret = atmel_pcm_pdc_platform_register(dev);
879
880 if (ret) {
881 dev_err(dev, "Could not register PCM: %d\n", ret);
882 return ret;
883 }
884
885 return 0;
886 }
887
888 /**
889 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
890 * @ssc_id: SSD ID in [0, NUM_SSC_DEVICES[
891 */
atmel_ssc_set_audio(int ssc_id)892 int atmel_ssc_set_audio(int ssc_id)
893 {
894 struct ssc_device *ssc;
895 int ret;
896
897 /* If we can grab the SSC briefly to parent the DAI device off it */
898 ssc = ssc_request(ssc_id);
899 if (IS_ERR(ssc)) {
900 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
901 PTR_ERR(ssc));
902 return PTR_ERR(ssc);
903 } else {
904 ssc_info[ssc_id].ssc = ssc;
905 }
906
907 ret = asoc_ssc_init(&ssc->pdev->dev);
908
909 return ret;
910 }
911 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
912
atmel_ssc_put_audio(int ssc_id)913 void atmel_ssc_put_audio(int ssc_id)
914 {
915 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
916
917 ssc_free(ssc);
918 }
919 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
920
921 /* Module information */
922 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
923 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
924 MODULE_LICENSE("GPL");
925
